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circuits  data  fault injection  format  intermittent faults  mixed signal  paper  scan test  scan  standard  test data  test  yield 
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Preview: Design & Test of Computers, IEEE - new TOC

Design & Test of Computers, IEEE - new TOC

TOC Alert for Publication# 54


Digitally intensive wireless transceivers

Dec. 2012

In this review article, the author revisits the digitization journey of wireless systems and the motivations that have driven this research field, gives a brief yet concise summary of state-of-the-art solutions, and offers insights for future developments.

Mixed-Signal SoCs With In Situ Self-Healing Circuitry

Dec. 2012

This article discusses the goals and recent achievements of the HEALICs program. The program's aim is to enhance wireless systems with sensors, actuators, and mixed-signal control loops in order to improve their performance yield.

Bringing up a chip on the cheap

Dec. 2012

Booting and debugging the functionality of silicon samples are known to be challenging and time-consuming tasks, even more so in cost-constrained environments. The authors describe their creative solutions used to bring up Stanford Smart Memories (SSM), a 55-million transistor research chip.

Analyzing the Impact of Intermittent Faults on Microprocessors Applying Fault Injection

Dec. 2012

Intermittent faults, being serious concerns for deep-submicron integrated circuits, are not well studied in the literature. This paper performs fault injection simulation to analyze the impact of intermittent faults, which is an important step towards the development of mitigation techniques for such threats.

Surrogate Model-Based Self-Calibrated Design for Process and Temperature Compensation in Analog/RF Circuits

Dec. 2012

Analog circuits designed in submicrometer nodes suffer from process variations, typically requiring calibration in order to center their performance parameters and to recover yield loss. This article presents a design flow to find appropriate tuning knob settings to compensate for different process variation scenarios.

OpenDFM Bridging the Gap Between DRC and DFM

Dec. 2012

This paper presents the details of a standard, named OpenDFM, which describes an efficient method to ensure manufacturability of integrated circuits that are designed at advanced technology nodes of today and one that can scale to address similar issues at future nodes as well. OpenDFM uses a meta-language format to capture and improve critical patterns that must be tested to ensure correct manufacturing and thus enhance yield.

Employing the STDF V4-2007 Standard for Scan Test Data Logging

Dec. 2012

This paper focuses on the V4-2007 extension of the Standard Test Data Format (STDF). STDF has been used as the standard representation for logging test data from automatic test equipment (ATE). This format however lacked a key capability, i.e., storing scan test results. The V4-2007 extension of this standard, as described in this paper, provides details on its ability in efficiently storing scan test results. Thus this standard now provides a complete and unified repository to store the results of parametric tests, functional tests and scan tests, all in a consistent format to aid in fault diagnosis and yield learning. This has in turn simplified the test flow and tracking of all necessary data to ensure more time-efficient testing and failure diagnosis.