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Preview: IBM developerWorks : Multicore acceleration

IBM developerWorks : Multicore acceleration

The latest content from IBM developerWorks

Published: 23 Oct 2016 10:18:59 +0000

Copyright: Copyright 2004 IBM Corporation.

Installing Red Hat Enterprise Linux 7.2 on IBM POWER8 and x86 in bare metal mode: A comparison

07 Jan 2016 05:00:00 +0000

This article can help administrators who need to install Red Hat Enterprise Linux on an IBM® POWER8™ processor-based system in bare metal mode by comparing the process of installation on an x86 system.

IBM Entrepreneur Week

15 Jan 2014 05:00:00 +0000

IBM Entrepreneur Week is a one-of-a-kind opportunity for you to meet, interact, and connect with entrepreneurs, venture capitalists, industry leaders, and academics from around the world. If you're a startup or entrepreneur, join us onlne for our inaugural IBM Entrepreneur Week, 3-7 Feb 2014. There will be events taking place online and in locations worldwide, including face-to-face and virtual mentoring sessions, a women entrepreneur-focused event, and a LiveStream broadcast of the SmartCamp Global Finals in San Francisco.

developerWorks Cell/B.E. resource center and multicore acceleration zone changes

12 Apr 2011 04:00:00 +0000

The Cell/B.E. resource center and the multicore acceleration zone on developerWorks are no longer available.

How to improve the performance of programs calling mathematical functions

13 Apr 2010 04:00:00 +0000

This article introduces the IBM MASS high-performance mathematical libraries, and demonstrates how to benefit from them - without the need for source program changes - by using the auto-vectorization capability of the IBM XL C/C++ and XL Fortran compilers. After introducing the concept of auto-vectorization and the associated compiler options, a case study of a discrete Fourier transform program is offered as a real life example of auto-vectorization. Timing results demonstrate that speedups of up to 8.94 times are obtained by the compilers on the example program, via the automatic invocation of MASS by auto-vectorization.

IBM PowerPC 405 Evaluation Kit with CoreConnect SystemC TLMs

29 Jul 2009 04:00:00 +0000

The PowerPC Evaluation Kit is no longer available from developerWorks.

Automating deployment and activation of virtual appliances for IBM AIX and Power Systems

29 Apr 2009 04:00:00 +0000

Server virtualization enables you to rapidly provision new environments by using libraries of virtual image templates, or virtual appliances. Automated provisioning requires the management of operating system, network, and application-specific customization. This article provides a sample framework for automating virtual image deployment and activation on Power Systems, with a downloadable example that demonstrates how to provision a virtual appliance made up of IBM WebSphere Application Server V7.0 running on AIX V5.3.

developerWorks Multicore acceleration zone changes

13 Mar 2009 04:00:00 +0000

The Multicore acceleration zone on developerWorks is no longer publishing weekly content.

Complex networking using Linux on Power blades

05 Aug 2008 04:00:00 +0000

Blades are an excellent choice for many applications and services, especially in the telecommunications service provider industry. But the unique requirements of these provider networks often require configurations that are complex and need up-front focus and planning so all the stringent functional requirements are met. In this article, learn how to plan and set up the necessary network configurations for a POWER6 JS22 blade deployment.

Cell/B.E. SDK: Code sample directory

15 Jul 2008 04:00:00 +0000

In this article, you'll find tables indicating the locations of code samples that illustrate how to use the IBM SDK for Multicore Acceleration. This article will be updated with new code samples.

IBM BladeCenter QS21 hardware performance glossary

06 May 2008 04:00:00 +0000

Although there is extensive published data about the hardware performance features of a single Cell Broadband Engine(TM) (Cell/B.E.) processor (and about the performance of a multitude of applications ported to it), there is little on the specific hardware performance features of the IBM BladeCenter(R) QS21 using a coherent SMP node of two Cell/B.E processors as well as an elaborate IO subsystem. This glossary goes with the article "Evaluating IBM BladeCenter QS21 hardware performance." In that article, the authors close the performance gap by providing information about basic latencies, throughputs, and relative execution times for some key computational benchmark kernels, such as Linpack and SPEC2000. The article also delivers a basic architectural overview of the system. And, you can get tips on how to optimize application performance.

The little broadband engine that could: Reviewing the newest little SDK that installs natively on PS3

19 Feb 2008 05:00:00 +0000

Come along on a little train tour of the SDK for Multicore Acceleration 3.0 to see what's different for developers and how you can make good use of the SDK, including native installation on PS3, support for FC7 and RHEL 5.1, enhanced compilers, Fortran and Ada support, BLAS, ALF, and DaCS--oh my!

The little broadband engine that could: Mailboxes and interrupts

03 Jul 2007 04:00:00 +0000

Meet two more means of communication between the SPE and the PPE -- mailboxes and signal notification. Mailboxes are special-purpose registers, similar to the I/O registers used to communicate with peripheral devices on some systems, available on the SPEs and the PPE. Signal notification registers are registers which can be read or written to by the PPE, but which the SPE can only read.

Tech tips: SPU vector intrinsics at your fingertips

01 May 2007 04:00:00 +0000

Know these common C/C++ language extensions intrinsics and greatly simplify the arduous task of using the SPU's assembly language.

Assembly language for Power Architecture, Part 4: Function calls and the PowerPC 64-bit ABI

28 Feb 2007 05:00:00 +0000

The ABI, or Application Binary Interface, is the set of conventions that allow programs written in different languages or compiled by different compilers to call each other's functions. This article, the last in a four-part series, discusses the PowerPC ABI for 64-bit ELF (UNIX-like) systems and how to write and call functions using it. Knowing in detail how the 64-bit PowerPC ABI works will help you write 64-bit programs for the POWER5 and other PowerPC-based processors more effectively, whether you program in assembly language or not. There is also a 32-bit ABI that is not covered in this article.

Assembly language for Power Architecture, Part 3: Programming with the PowerPC branch processor

17 Jan 2007 05:00:00 +0000

The last two articles discussed the outline of how programs on the POWER5 processor work using the 64-bit PowerPC instruction set, how the PowerPC instruction set addresses memory, and how to do position-independent code. This article focuses on the very powerful condition and branch instructions available in the PowerPC instruction set.

Assembly language for Power Architecture, Part 2: The art of loading and storing on PowerPC

29 Nov 2006 05:00:00 +0000

The previous article in this series introduced assembly language programming using the 64-bit PowerPC instruction set on POWER5 and other processors that use these instructions. This article drills down and discusses the specifics of 64-bit PowerPC assembly language programming on Linux and UNIX-like operating systems, focusing on data access methods and position-independent code.

The Heath Robinson Rube Goldberg Computer, Part 1: Implementing a computer using a mixture of technologies from relays to fluidic logic

03 Oct 2006 04:00:00 +0000

Imagine a computer formed from a mixture of technologies ranging from relays to fluidic logic. Now imagine being able to create a single piece of such a computer (perhaps as small as a single word of memory) in the technology of your choice, and then using the Internet to run your masterpiece in conjunction with other portions of the system created by contributors located around the world! Author Clive (Max) Maxfield explains the creation of just such a computing engine and how you can be involved.

Assembly language for Power Architecture, Part 1: Programming concepts and beginning PowerPC instructions

03 Oct 2006 04:00:00 +0000

The POWER5 processor is a 64-bit workhorse used in a variety of settings. Starting with this introduction to assembly language concepts and the PowerPC instruction set, this series of articles introduces assembly language in general and specifically assembly language programming for the POWER5.

Standards and specs: Of RoHS and rushed standards

15 Aug 2006 04:00:00 +0000

When the ex cathedra RoHS Directive came down, it was missing a little crucial piece of information -- how manufacturers, distributors, and purchasers of parts could communicate to each other the RoHS status of every part.

Standards and specs: The Interchange File Format (IFF)

13 Jun 2006 04:00:00 +0000

The IFF file format had many of the features still sought today in modern file formats. This month's Standards and specs looks at the IFF file format and the lessons it has for modern file formats, such as XML.

SoC drawer: SoC design for hardware acceleration, Part 1

06 Jun 2006 04:00:00 +0000

System-on-chip (SoC) designs offer the opportunity to migrate functionality initially implemented in software and firmware into hardware acceleration engines and state machines. Reconfigurable SoCs based on processors in FPGA fabric, such as the PowerPC 405 in the Xilinx Virtex-4, provide a platform for rapid migration of functionality from PowerPC software and firmware to the FPGA logic. Configurable application-specific integrated circuit (ASIC) SoCs can be optimized similarly over product revisions as SoC ASIC roadmap configurations are defined. This article examines methods for software design, specification, and implementation that will simplify future efforts to offload software functionality to hardware. Basic video and image processing algorithms provide working example algorithms for this article and the next.

Standards and specs: Lies, statistics, and benchmarks

23 May 2006 04:00:00 +0000

Benchmarks can be an excellent tool for predicting performance and estimating requirements. They can also be misleading, possibly catastrophically so. Benchmark standardization helps distinguish between a good estimate and a meaningless number.

Cell Broadband Engine processor DMA engines, Part 2: From an SPE point of view

02 May 2006 04:00:00 +0000

The Cell Broadband Engine (Cell BE) architecture provides on-chip DMA capabilities between the PPE and the SPEs. Meet the SPE interface to the DMA capabilities of the processor, from channel allocation to communication.

The Cell Broadband Engine processor security architecture

24 Apr 2006 04:00:00 +0000

The unrelenting evolution toward an even more open and connected computing infrastructure requires robust security to thrive. Learn how the Cell Broadband Engine processor's security architecture is uniquely suited for the challenges of this digital future.

SPU pipeline examination in the IBM Full-System Simulator for the Cell Broadband Engine processor

17 Apr 2006 04:00:00 +0000

Find out the exact cycle where the SPE stalls, or identify a poor choice of branch predictions, using pipeline tracing in the Cell Broadband Engine (Cell BE) simulator.

SoC drawer: Detecting and correcting I/O and memory errors

21 Mar 2006 05:00:00 +0000

SoCs (systems-on-chips) are often deployed in communications, storage, network processing, and mission-critical embedded data processing systems. A reliable SoC-based system must mitigate and control environmentally induced errors in stored or transported data. It is impossible to fully prevent data loss, but engineering due diligence is required to ensure that systems are as safe as practically possible given current data coding methods for error detection and correction. This article examines methods to minimize potential data corruption and to maximize system safety when uncorrectable errors do occur.

Everything you ever wanted to know about C types, Part 3: Implementation details

19 Mar 2006 05:00:00 +0000

The C type system has changed a lot since the 1970s. Part 3 in the "Everything you ever wanted to know about C types" series reviews some of the quirks that particular implementations have had and discusses the changes the C99 language revision introduced.

Migrating from x86 to PowerPC, Part 9: Sensors, sensors, sensors!

14 Mar 2006 05:00:00 +0000

From schematics to code, get a leg up on building your own robot submarine. Building on previous successes, Lewin Edwards shows how to add more sensors to your submarine, looking at the design requirements of different sensors and ways of sanity checking the results they provide.

Standards and specs: Not by UNIX alone

08 Mar 2006 05:00:00 +0000

Technology professionals have loosely used the term "UNIX" since the first person had to explain the difference between the Berkeley and AT&T flavors, so it's not surprising to find as many UNIX standards as there are versions of the operating system. Peter Seebach wades through the wellspring of UNIX standards and sorts them out for you, concluding that the rumors of the death of UNIX are (as usual) greatly exaggerated.

Everything you ever wanted to know about C types, Part 1: What's in a type?

03 Jan 2006 05:00:00 +0000

This article, first in a four-part series, introduces the basics of the C type system, with an overview of what it means to talk about type and a discussion of the basic types (integer and floating point) in some detail.

SoC drawer: SoC concurrent development

20 Dec 2005 05:00:00 +0000

A system-on-a-chip (SoC) can be more complex in terms of hardware-software interfacing than many earlier embedded systems because an SoC often includes multiple processor cores and numerous I/ O interfaces. The process of integrating and testing the firmware-hardware interface can begin early, but without good management and testing, the mutability of firmware and early stages of hardware design simulation can lead to disastrous setbacks for a project. This article teaches system designers about tools and methods to minimize project churn.

Just like being there: Papers from the Fall Processor Forum 2005: Introducing the IBM PowerPC 970MP

14 Dec 2005 05:00:00 +0000

This Fall Processor Forum paper explores the PowerPC 970MP, a 90nm-process, dual-core version of the PowerPC 970FX with remarkable, dynamic power-saving features. It's like no 64-bit dual-core PowerPC processor you've ever met before. Read why.

Cell Broadband Engine processor DMA engines, Part 1: The little engines that move data

06 Dec 2005 05:00:00 +0000

A single Cell Broadband Engine (Cell BE) processor consists of one PowerPC core and eight SPEs each having their own DMA engine. The DMA engines are a key component of the overall Cell Broadband Engine Architecture (CBEA) as they move data between SPEs and the PowerPC core. Any operating system or application wishing to utilize the SPE depends on the DMA engines to manage work flow on behalf of the SPEs.

Meet the experts: David Krolak on the Cell Broadband Engine EIB bus

06 Dec 2005 05:00:00 +0000

Understanding the Element Interconnect Bus (EIB) is an essential component to maximizing performance on the Cell Broadband Engine (Cell BE) Architecture. The lead designer and EIB project manager sit down for an hour with developerWorks' Meet The Experts to discuss ring versus interconnect buses, data arbiters, and bus protocols.

Cell Broadband Engine Architecture and its first implementation

29 Nov 2005 05:00:00 +0000

Explore the first implementation of the Cell Broadband Engine (Cell BE) Architecture, developed jointly by Sony, Toshiba, and IBM, and get an up-close look at its performance figures and characteristics.

PowerPC Architecture Book

16 Nov 2005 05:00:00 +0000

This three-volume set defines the instruction and registers used by application programs, the storage models, privileged facilities, and related instructions.

PowerPC Architecture Book, Version 2.02

16 Nov 2005 05:00:00 +0000

This 3 volume set, Version 2.02, defines the instruction and registers used by application programs, the storage models, privileged facilities, and related instructions for the IBM POWER5 processor family. Verson 2.01 describes POWER4 and POWER4+ processors.

Debugging simulated hardware on Linux, Part 1: Device driver debugging

02 Nov 2005 05:00:00 +0000

This two-part series is geared toward easing device driver development. This first part illustrates proven methods you can use to test the complete code flow of a device driver during the design, development, and debugging stages.

Standards and specs: Early adopters

18 Oct 2005 04:00:00 +0000

Whether a standard will succeed and be widely adopted is ambiguous at first, regardless of who endorses it -- a major player or a fringe element. So why would people put all their eggs in a standards basket when that basket might not exist tomorrow? Join Peter Seebach as he shows the potential advantages of adopting a standard before it becomes one. (Of course, he hasn't forgotten the potential disadvantages, too.)

Meet the experts: On open source firmware development

11 Oct 2005 04:00:00 +0000

Slimline Open Firmware (SLOF) provides a largely machine-independent BIOS, illustrating what is needed to initialize and boot Linux, a hypervisor, or any other operating system or virtualization layer on PowerPC-based machines based on the de-facto industry Open Firmware boot standard. Join three experts as they discuss the decisions in developing SLOF and where they'd use it and provide a picture of the boot-up process under SLOF.

Standards and specs: The ATX case and power supply

13 Sep 2005 04:00:00 +0000

The ATX standard allows power supplies and cases to be commodity parts, dramatically reducing the cost of computer design. Lessons learned from the success of this standard show why standardizing parts is important. The BTX standard builds on this, and the standards work should do likewise.

Migrating from x86 to PowerPC, Part 7: Basic design of the vehicle control module

06 Sep 2005 04:00:00 +0000

Get an overview of some design decisions involved in configuring a secondary processor to handle maintenance tasks on your robot submarine, and see some of the setup code allowing the subordinate processor to interact with the main system.

Five minutes with: Stanley Kwong on the first Power Architecture-related technical briefings

02 Sep 2005 04:00:00 +0000

This question and answer session features Stanley Kwong, the person in charge of worldwide technical briefings for IBM. Stan handles developerWorks briefings and is about to orchestrate the first-ever briefing on the Power Architecture-related dW event in the People's Republic of China. Hear him as he talks about the briefing and comments on technology development in one of the world's most rapidly developing economies.

Cell Broadband Engine Architecture from 20,000 feet

24 Aug 2005 04:00:00 +0000

The Cell Broadband Engine Architecture (CBEA, or, informally, "Cell") defines a new processor structure based upon the 64-bit Power Architecture technology, but with unique features directed toward distributed processing and media-rich applications. The Cell architecture defines a single-chip multiprocessor consisting of one or more Power Processor Elements (PPEs) and multiple high-performance SIMD Synergistic Processor Elements (SPEs). While each SPE is an independent processor running its own application programs, a shared, coherent memory and a rich set of DMA commands provide for seamless and efficient communications between all Cell processing elements. This article provides a concise view inside the Cell's architecture.

Five minutes with: Dan Greenberg on plans for Cell

24 Aug 2005 04:00:00 +0000

Power Everywhere systems offerings program director Dan Greenberg talks about where the Cell Broadband Engine Architecture is going, how IBM intends to encourage collaboration with developers in its deployment, and what collaboration services are already available for Cell development. Plus, he introduces five new detailed developer resources -- an overview of the architecture, the instruction set architecture for the SPU, and three language datasheets.

Meet the experts: Arnd Bergmann on the Cell BE processor

25 Jun 2005 04:00:00 +0000

This question and answer article features Arnd Bergmann of IBM: a kernel hacker with the IBM Linux Technology Center, the Linux on Cell Broadband Engine (Cell BE) processor kernel maintainer, and author of the spufs file system.

Standards and specs: Naturally occurring standards

12 Apr 2005 04:00:00 +0000

What makes a standard viable without the formal blessing of a standards organization? Should you use such informal standards, or ignore them? Learn more about de facto standards in this month's Standards and specs.

MySQL for Linux on POWER, Part 1: Introduction to creating a database

05 Apr 2005 04:00:00 +0000

Learn about the availability of MySQL Database Server for Linux(R) running on IBM(R) POWER(TM) and PowerPC(R) processor-based servers (collectively referred to as Linux on POWER). As a brief guide for application developers using MySQL on Linux on POWER, this paper is intended for MySQL developers and database administrators who are familiar with their system environment, networks, media devices, and disk resources. In Part 2 of this article, read about developing applications for MySQL using PHP, C/C++, Java, Perl, and Python.

Unrolling AltiVec, Part 2: Optimize code for SIMD processing

16 Mar 2005 05:00:00 +0000

In this second article of a three-part series, Peter Seebach looks closer at AltiVec, the PowerPC SIMD unit. He explains further how you can effectively use AltiVec, discussing the choice between C and assembly, and shows some of the issues you'll face when trying to get the best performance out of an AltiVec processor.

Unrolling AltiVec, Part 1: Introducing the PowerPC SIMD unit

01 Mar 2005 05:00:00 +0000

AltiVec? Velocity Engine? VMX? If you've only been casually following PowerPC development, you might be confused by the various guises of this vector processing SIMD technology. In this first installment of a three-part series, Peter Seebach gives you the basics on what AltiVec is, what it does -- and how it stacks up against its competition.

Power Architecture author FAQ

18 Feb 2005 05:00:00 +0000

If you're interested enough in Power Architecture technology to read articles on our content area, then you just might have some knowledge to share with your fellow pros. Find out how you can submit your ideas to developerWorks.

Data alignment: Straighten up and fly right

08 Feb 2005 05:00:00 +0000

Data alignment is an important issue for all programmers who directly use memory. Data alignment affects how well your software performs, and even if your software runs at all. As this article illustrates, understanding the nature of alignment can also explain some of the "weird" behaviors of some processors.

Migrating from x86 to PowerPC, Part 2: Anatomy of the Linux boot process

08 Feb 2005 05:00:00 +0000

This installment of "Migrating from x86 to PowerPC" discusses detailed similarities and differences between booting Linux on an x86-based platform (typically a PC-compatible SBC) and a custom embedded platform based around PowerPC, ARM, and others. It discusses suggested hardware and software designs and highlights the tradeoffs of each. It also describes important design pitfalls and best practices.

Standards and specs: A house divided

25 Jan 2005 05:00:00 +0000

What happens when two coalitions within a standards committee come into conflict, and the dispute doesn't get resolved quickly? The ultrawideband technology standardization issue shows you.

Emulation and cross-development for PowerPC

18 Jan 2005 05:00:00 +0000

This article introduces PowerPC emulation and cross-compiling for developers without access to real hardware. It is intended for developers familiar with computer architecture who own an x86-based workstation but are interested in experimenting with PowerPC.

Meet the experts: Regina Darmoni

11 Jan 2005 05:00:00 +0000

This question and answer article features the IBM Program Director of PowerPC licensing, Regina Darmoni. Regina has led the PowerPC licensing effort from the concept stage to the present and talks about general license terms and what's available -- and what it's like to be the little guy.

From the stacks: Programming the cache on the PowerPC 750GX/FX

04 Jan 2005 05:00:00 +0000

Many programs can obtain acceptable performance by simply letting the processor manage its own caching -- however, programs with special requirements (for instance, bootware) may obtain dramatically improved performance by manipulating the cache directly. This excerpt from an IBM Microelectronics Technical Library Application Note discusses cache basics for the PowerPC 750GX and 750FX.

The year in Power Architecture technology: The year in microprocessors

22 Dec 2004 05:00:00 +0000

From spintronics to clockless CPUs, 2004 was a year of process and research in the microprocessor industry. This article offers a month-by-month look at the highlights of the 2004 microprocessor timeline.

Great moments in microprocessor history

22 Dec 2004 05:00:00 +0000

The evolution of the modern microprocessor is one of many surprising twists and turns. Who invented the first micro? Who had the first 32-bit single-chip design? You might be surprised at the answers. This article shows the defining decisions that brought the contemporary microprocessor to its present-day configuration.

Standards and specs, Special Edition: Introducing

15 Dec 2004 05:00:00 +0000

Major electronics companies have come together to form a new standards body focused on Power Architecture technology. This organization will create and promote a family of standards, reference designs, and more. This month's Standards and specs looks at how the new standards body will work, and what it will do.

PowerPC development from the bargain basement

14 Dec 2004 05:00:00 +0000

The Kuro Box promises something fairly interesting: a usable single-board PowerPC computer, for only US$160 -- when other PowerPC development boards often cost ten times as much. Peter Seebach guides you through setup and install in this developerWorks hardware howto.

Meet the experts: John McCalpin

23 Nov 2004 05:00:00 +0000

This question and answer article features IBM Senior Technical Staff Member John McCalpin on his work on the POWER5 and in high performance computing; on the Hypervisor and the size of POWER5 chips; on 128-bit computing -- and even on why he became a computer scientist instead of an entomologist.

Save your code from meltdown using PowerPC atomic instructions

02 Nov 2004 05:00:00 +0000

Something as simple as incrementing an integer can fail in a concurrent environment. This article illustrates the failure scenario and introduces the PowerPC's coping mechanism: atomic instructions. Learn how to use these assembly-level instructions to update memory correctly, even in the face of concurrency.

Standards and specs: Open Firmware -- the bridge between power-up and OS

26 Oct 2004 04:00:00 +0000

Open Firmware provides a reasonably standardized way for computers to find hardware, configure it, and boot an operating system. In this month's Standards and specs, author Peter Seebach looks at the Open Firmware spec, traces its history as a standard, examines how it works and some of its components, and discusses the benefits it offers.

From the stacks: Making the transition to 64 bits

19 Oct 2004 04:00:00 +0000

Developers porting applications to the 64-bit computing mode of the 970FX processor may face a number of issues; this excerpt from a longer Technical Library article covers some of the issues faced when porting existing 32-bit code to the new computing model -- or when embarking on new 64-bit development.

From the stacks: PowerPC 750FX/GX design and debug tips, Part 2

12 Oct 2004 04:00:00 +0000

In the second and final installment of this series, IBM Senior Engineer Dale Elson offers comprehensive tips on troubleshooting and debugging your PowerPC 750FX/GX systems. Part 1 focused on design best practices. This article also covers system qualification and lists the information to communicate when you need debugging help.

From the stacks: PowerPC 750FX/GX design and debug tips, Part 1

06 Oct 2004 04:00:00 +0000

Soak up some of the wisdom that the IBM PowerPC Applications Engineering team has accumulated from dozens of years of designing, troubleshooting, and debugging PowerPC systems. In the first of a two-part series, IBM Senior Engineer Dale Elson presents tips and best practices for designing applications for PowerPC 750FX/GX processors -- but you can extrapolate much of his advice to other systems as well.

Standards and specs: Standards

27 Sep 2004 04:00:00 +0000

Introducing a regular column on the specifications and standards affecting people involved in nearly every aspect of Power Architecture technology, Peter Seebach looks at the different kinds of standards in the industry today, as well as how to find out about and make the most effective use of standards in your own work.