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Method and system for dynamic distributed data caching

Tue, 08 Dec 2015 08:00:00 EST

A method and system for dynamic distributed data caching is presented. The system includes one or more peer members and a master member. The master member and the one or more peer members form cache community for data storage. The master member is operable to select one of the one or more peer members to become a new master member. The master member is operable to update a peer list for the cache community by removing itself from the peer list. The master member is operable to send a nominate master message and an updated peer list to a peer member selected by the master member to become the new master member.



Chaining move specification blocks

Tue, 20 Oct 2015 08:00:00 EDT

An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.



Using extended asynchronous data mover indirect data address words

Tue, 01 Sep 2015 08:00:00 EDT

An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.



Chaining move specification blocks

Tue, 25 Aug 2015 08:00:00 EDT

An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.



Using extended asynchronous data mover indirect data address words

Tue, 25 Aug 2015 08:00:00 EDT

An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.



Decentralized caching system

Tue, 28 Jul 2015 08:00:00 EDT

In a satellite communication system comprising at least a hub and a plurality of terminals, at least one terminal may include a cache for storing data objects. The cache may be based on a detachable memory device that may be inserted to or removed from the terminal at any given time, including after the terminal is deployed. Aspects are directed to preventing a prefetching of objects already stored in a cache of a remote terminal. In some embodiments, an efficient multicasting of content to terminals over an adaptive link may occur in a manner which may benefit terminals comprising a cache while not affecting or minimally affecting the performance of terminals that may not include a cache.



Data caching method

Tue, 07 Jul 2015 08:00:00 EDT

Data caching for use in a computer system including a lower cache memory and a higher cache memory. The higher cache memory receives a fetch request. It is then determined by the higher cache memory the state of the entry to be replaced next. If the state of the entry to be replaced next indicates that the entry is exclusively owned or modified, the state of the entry to be replaced next is changed such that a following cache access is processed at a higher speed compared to an access processed if the state would stay unchanged.



Management of multiple software images with shared memory blocks

Tue, 09 Jun 2015 08:00:00 EDT

A data processing entity that includes a mass memory with a plurality of memory locations for storing memory blocks. Each of a plurality of software images includes a plurality of memory blocks with corresponding image addresses within the software image. The memory blocks of software images stored in boot locations of a current software image are relocated. The boot blocks of the current software image are stored into the corresponding boot locations. The data processing entity is booted from the boot blocks of the current software image in the corresponding boot locations, thereby loading the access function. Each request to access a selected memory block of the current software image is served by the access function, with the access function accessing the selected memory block in the associated memory location provided by the control structure.



Dynamic consolidation of virtual machines

Tue, 26 May 2015 08:00:00 EDT

A method and apparatus are disclosed of monitoring a number of virtual machines operating in an enterprise network. One example method of operation may include identifying a number of virtual machines currently operating in an enterprise network and determining performance metrics for each of the virtual machines. The method may also include identifying at least one candidate virtual machine from the virtual machines to optimize its active application load and modifying the candidate virtual machine to change its active application load.



Identification and management of unsafe optimizations

Tue, 26 May 2015 08:00:00 EDT

Techniques for implementing identification and management of unsafe optimizations are disclosed. A method of the disclosure includes receiving, by a managed runtime environment (MRE) executed by a processing device, a notice of misprediction of optimized code, the misprediction occurring during a runtime of the optimized code, determining, by the MRE, whether a local misprediction counter (LMC) associated with a code region of the optimized code causing the misprediction exceeds a local misprediction threshold (LMT) value, and when the LMC exceeds the LMT value, compiling, by the MRE, native code of the optimized code to generate a new version of the optimized code, wherein the code region in the new version of the optimized code is not optimized.



Dynamically expandable and contractible fault-tolerant storage system with virtual hot spare

Tue, 26 May 2015 08:00:00 EDT

A dynamically expandable and contractible fault-tolerant storage system employs a virtual hot spare that is created from unused storage capacity across a plurality of storage devices. This unused storage capacity is available if and when a storage device fails for storage of data recovered from the remaining storage device(s). On an ongoing basis, the storage system may determine the amount of unused storage capacity that would be required for the virtual hot spare (e.g., based on the number of storage devices, the capacities of the various storage devices, the amount of data stored, and the manner in which the data is stored) and generate a signal if additional storage capacity is needed for a virtual hot spare.



Protecting visible data during computerized process usage

Tue, 26 May 2015 08:00:00 EDT

Embodiments of the present invention provide an approach for protecting visible data during computerized process usage. Specifically, in a typical embodiment, when a computerized process is identified, a physical page key (PPK) is generated (e.g., a unique PPK may be generated for each page of data) and stored in at least one table. Based on the PPK a virtual page key (VPK) is generated and stored in at least one register. When the process is later implemented, and a request to access a set of data associated the process is received, it will be determined whether the VPK is valid (based on the PPK). Based on the results of this determination, a data access determination is made.



Memory training results corresponding to a plurality of memory modules

Tue, 26 May 2015 08:00:00 EDT

Methods, apparatuses, and computer program products for improving memory training results corresponding to a plurality of memory modules are provided. Embodiments include detecting a hardware configuration change upon initiating a boot sequence of a system that includes the plurality of memory modules; generating for a plurality of training iterations, reference training values corresponding to aligning of a data strobe (DQS) signal with a data valid window of data (DQ) lines of the plurality of memory modules; identifying for each training iteration, any outer values within the reference training values generated for that training iteration; eliminating the identified outer values from the reference training values; generating a final reference training value based on an average of the remaining reference training values; and using the final reference training value as the DQ-DQS timing value for the boot sequence of the system.



Prefetch optimizer measuring execution time of instruction sequence cycling through each selectable hardware prefetch depth and cycling through disabling each software prefetch instruction of an instruction sequence of interest

Tue, 26 May 2015 08:00:00 EDT

A prefetch optimizer tool for an information handling system (IHS) may improve effective memory access time by controlling both hardware prefetch operations and software prefetch operations. The prefetch optimizer tool selectively disables prefetch instructions in an instruction sequence of interest within an application. The tool measures execution times of the instruction sequence of interest when different prefetch instructions are disabled. The tool may hold hardware prefetch depth constant while cycling through disabling different prefetch instructions and taking corresponding execution time measurements. Alternatively, for each disabled prefetch instruction in the instruction sequence of interest, the tool may cycle through different hardware prefetch depths and take corresponding execution time measurements at each hardware prefetch depth. The tool selects a combination of hardware prefetch depth and prefetch instruction disablement that may improve the execution time in comparison with a baseline execution time.



Apparatuses and methods for providing data from multiple memories

Tue, 26 May 2015 08:00:00 EDT

Apparatuses and methods for providing data are disclosed. An example apparatus includes a plurality of memories coupled to a data bus. The memories provide data to the data bus responsive, at least in part, to a first address. The plurality of memories further provide at least a portion of the data corresponding to the first address to the data bus during a sense operation for a second address provided to the plurality of memories after the first address. Each of the plurality of memories provides data to the data bus corresponding to the first address at different times. Moreover, a plurality of memories may provide at least 2N bits of data to the data bus responsive, at least in part, to an address, each of the plurality of memories provide N bits of data to the data bus at different times.



Memory management unit for a microprocessor system, microprocessor system and method for managing memory

Tue, 26 May 2015 08:00:00 EDT

The invention pertains to a memory management unit for a microprocessor system, the memory management unit being connected or connectable to at least one processor core of the microprocessor system and being connected or connectable to a physical memory of the microprocessor system. The memory management unit is adapted to selectively operate in a hypervisor mode or in a supervisor mode, the hypervisor mode and the supervisor mode having different privilege levels of access to hardware The memory management unit comprises a first register table indicating physical address information for mapping at least one logical physical address and at least one actual physical address onto each other; a second register table indicating an allowed address range of physical addresses accessible to a process running in or under supervisor mode; wherein the memory management unit is adapted to prevent write access to the second register table by a process not in hypervisor mode. The memory management unit is further adapted to allow write access to the first register table of a process running in or under supervisor mode to reconfigure the physical address information indicated in the first register table with memory mapping information relating to at least one physical address, if the at least one physical address is in the allowed address range, and to prevent write access to the first register table of the process running in or under supervisor mode if the at least one physical address is not in the allowed address range. The invention also pertains to a microprocessor system and a method for managing memory.



System and method for virtual machine conversion

Tue, 26 May 2015 08:00:00 EDT

System and method for conversion of virtual machine files without requiring copying of the virtual machine payload (data) from one location to another location. By eliminating this step, applicant's invention significantly enhances the efficiency of the conversion process. In one embodiment, a file system or storage system provides indirections to locations of data elements stored on a persistent storage media. A source virtual machine file includes hypervisor metadata (HM) data elements in one hypervisor file format, and virtual machine payload (VMP) data elements. The source virtual machine file is converted by transforming the HM data elements of the source file to create destination HM data elements in a destination hypervisor format different from the source hypervisor format; maintaining the locations of the VMP data elements stored on the persistent storage media constant during the conversion from source to destination file formats without reading or writing the VMP data elements; and creating indirections to reference the destination HM data elements in the destination hypervisor format and the existing stored VMP data elements.



Managing CPU resources for high availability micro-partitions

Tue, 26 May 2015 08:00:00 EDT

A partition manager relocates a logical partition from a primary shared processor pool to a secondary shared processor pool in response to a predetermined condition, such as a hardware failure. The relocated logical partition is allocated a smaller quantity of processing units from the secondary pool than it was allocated from the primary pool. A quantity of processing units reserved for a second logical partition is identified in the secondary shared processor pool, and a portion of those reserved processing units are allocated to the relocated logical partition. The reserved processing units may be redistributed among multiple relocated logical partitions.



Dispersed storage unit and method for configuration thereof

Tue, 26 May 2015 08:00:00 EDT

A dispersed storage (DS) unit for use within a dispersed storage network is capable of self-configuring using registry information provided to the DS unit. The registry information includes a slice name assignment indicating a range of slice names corresponding to a plurality of potential data slices of potential data objects to be stored in the DS unit. Based on the registry information, the DS unit allocates a portion of physical memory to store the potential data slices.



System and method for determining a level of success of operations on an abstraction of multiple logical data storage containers

Tue, 26 May 2015 08:00:00 EDT

Various systems and methods are described for configuring a logical data storage container. In one embodiment, an instruction to perform an operation to modify an attribute of the logical data storage container that is an abstraction of a plurality of pertinent storage containers is received. A translated instruction to perform a sub-operation associated with the operation is transmitted to each of a number of the plurality of pertinent storage containers. A level of success of the performing of the operation on the logical data storage container is detected based on a comparison of a threshold value to a level of success of the performing of the sub-operation on each of the number of the plurality of pertinent storage containers. A report of the detected level of success is communicated.



Automatically preventing large block writes from starving small block writes in a storage device

Tue, 26 May 2015 08:00:00 EDT

A mechanism is provided in a storage device for performing a write operation. The mechanism configures a write buffer memory with a plurality of write buffer portions. Each write buffer portion is dedicated to a predetermined block size category within a plurality of block size categories. For each write operation from an initiator, the mechanism determines a block size category of the write operation. The mechanism performs each write operation by writing to a write buffer portion within the plurality of write buffer portions corresponding to the block size category of the write operation.



Management apparatus and management method

Tue, 26 May 2015 08:00:00 EDT

Proposed are a management apparatus and a management method capable of improving the stability of the overall computer system. In a computer system which manages a storage area provided by each of a plurality of mutually connected storage apparatuses as a logical pool, provides to a host computer a virtual volume associated with the logical pool, and assigns a real storage area from the logical pool to the virtual volume when the host computer writes into the virtual volume, when a storage apparatus is added to the plurality of storage apparatuses, the host computer is controlled to switch the access path to the added storage apparatus.



System cache with quota-based control

Tue, 26 May 2015 08:00:00 EDT

Methods and apparatuses for implementing a system cache with quota-based control. Quotas may be assigned on a group ID basis to each group ID that is assigned to use the system cache. The quota does not reserve space in the system cache, but rather the quota may be used within any way within the system cache. The quota may prevent a given group ID from consuming more than a desired amount of the system cache. Once a group ID's quota has been reached, no additional allocation will be permitted for that group ID. The total amount of allocated quota for all group IDs can exceed the size of system cache, such that the system cache can be oversubscribed. The sticky state can be used to prioritize data retention within the system cache when oversubscription is being used.



Memory data management

Tue, 26 May 2015 08:00:00 EDT

A method and computer-readable storage media are provided for rearranging data in physical memory units. In one embodiment, a method may include monitoring utilization counters. The method may further include, comparing the utilization counters for a match with an instance in a first table containing one or more instances when data may be rearranged in the physical memory units. The table may further include where the data should be relocated by a rearrangement. The method may also include, continuing to monitor the utilization counters if a match is not found with an instance in the first table. The method may further include, rearranging the data in the physical memory units if a match between the utilization counters and an instance in the first table is found.



Moving blocks of data between main memory and storage class memory

Tue, 26 May 2015 08:00:00 EDT

An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.



Methods and systems for replicating an expandable storage volume

Tue, 26 May 2015 08:00:00 EDT

Machine implemented method and system for generating a disaster recovery copy of an expandable storage volume having a namespace for storing information for accessing data objects stored at a data constituent volume is provided. A transfer operation for transferring a point in time copy of the expandable storage volume from a first location to a second location is generated. Information regarding the expandable storage volume from the first location is retrieved and a destination expandable storage volume is resized to match components of the expandable storage volume at the first location. Thereafter, the point in time copy of the expandable storage volume is transferred from the first location to the second location and configuration information regarding the point in time copy is copied from the first location to the second location.



Method and apparatus for optically backing up data

Tue, 26 May 2015 08:00:00 EDT

An optical backup apparatus is provided and includes an optical storage device, an interface module to connect with at least one type of external storage medium, and a control unit to back up data from the external storage medium to the optical storage device in response to an external remote control operation.



Storage device and method for controlling data invalidation

Tue, 26 May 2015 08:00:00 EDT

A storage device according to an embodiment includes: a host interface connected to a host; a memory including a first buffer that stores a logical address range designated by an invalidation instruction received from the host via the host interface and a second buffer that stores an internal logical address range which is an area combination with the logical address range; a nonvolatile memory; and a controller. The controller includes: an invalidation instruction processor that stores the logical address range designated by the invalidation instruction in the first buffer; an area combination executor that generates the internal logical address range by the area combination with the logical address range and stores the internal logical address range in the second buffer; and an invalidation executor that executes invalidation processing on the nonvolatile memory based on the internal logical address range.



Memory system with fixed and variable pointers

Tue, 26 May 2015 08:00:00 EDT

A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller performs data transfer, stores management information including a storage position of the data stored in the second storing unit into the first storing unit, and performs data management while updating the management information. The second storing unit has a management information storage area for storing management information storage information including management information in a latest state and a storage position of the management information. The storage position information is read by the controller during a startup operation of the memory system and includes a second pointer indicating a storage position of management information in a latest state in the management information storage area and a first pointer indicating a storage position of the second pointer. The first pointer is stored in a fixed area in the second storing unit and the second pointer is stored in an area excluding the fixed area in the second storing unit.



Dynamically improving memory affinity of logical partitions

Tue, 26 May 2015 08:00:00 EDT

In a computer system that includes multiple nodes and multiple logical partitions, a dynamic partition manager computes current memory affinity and potential memory affinity to help determine whether a reallocation of resources between nodes may improve memory affinity for a logical partition or for the computer system. If so, the reallocation of resources is performed so memory affinity for the logical partition or computer system is improved. Memory affinity is computed relative to the physical layout of the resources according to a hardware domain hierarchy that includes a plurality of primary domains and a plurality of secondary domains.



Virtual machine trigger

Tue, 26 May 2015 08:00:00 EDT

A computing system includes a parent partition, child partitions, a hypervisor, shared memories each associated with one of the child partitions, and trigger pages each associated with one of the child partitions. The hypervisor receives a system event signal from one of the child partitions and, in response to receiving the system event signal, accesses the trigger page associated with that child partition. The hypervisor determines whether the trigger page indicates whether data is available to be read from the shared memory associated with the child partition. The hypervisor can send an indication to either the parent partition or the child partitions that data is available to be read from the shared memory associated with the child partition if the hypervisor determines that the trigger page indicates that data is available to be read from the shared memory associated with the child partition.



Storage device

Tue, 26 May 2015 08:00:00 EDT

To provide a storage device with low power consumption. The storage device includes a plurality of cache lines. Each of the cache lines includes a data field which stores cache data; a tag which stores address data corresponding the cache data; and a valid bit which stores valid data indicating whether the cache data stored in the data field is valid or invalid. Whether power is supplied to the tag and the data field in each of the cache lines is determined based on the valid data stored in the valid bit.



Distributed cache coherency protocol

Tue, 26 May 2015 08:00:00 EDT

Systems, methods, and other embodiments associated with a distributed cache coherency protocol are described. According to one embodiment, a method includes receiving a request from a requester for access to one or more memory blocks in a block storage device that is shared by at least two physical computing machines and determining if a caching right to any of the one or more memory blocks has been granted to a different requester. If the caching right has not been granted to the different requester, access is granted to the one or more memory blocks to the requester.



Block memory engine with memory corruption detection

Tue, 26 May 2015 08:00:00 EDT

Techniques for handling version information using a copy engine. In one embodiment, an apparatus comprises a copy engine configured to perform one or more operations associated with a block memory operation in response to a command. Examples of block memory operations may include copy, clear, move, and/or compress operations. In one embodiment, the copy engine is configured to handle version information associated with the block memory operation based on the command. The one or more operations may include operating on data in a cache and/or modifying entries in a memory. In one embodiment, the copy engine is configured to compare version information in the command with stored version information. The copy engine may overwrite or preserve version information based on the command. The copy engine may be a coprocessing element. The copy engine may be configured to maintain coherency with other copy engines and/or processing elements.



Data bus efficiency via cache line usurpation

Tue, 26 May 2015 08:00:00 EDT

Embodiments of the current invention permit a user to allocate cache memory to main memory more efficiently. The processor or a user allocates the cache memory and associates the cache memory to the main memory location, but suppresses or bypassing reading the main memory data into the cache memory. Some embodiments of the present invention permit the user to specify how many cache lines are allocated at a given time. Further, embodiments of the present invention may initialize the cache memory to a specified pattern. The cache memory may be zeroed or set to some desired pattern, such as all ones. Alternatively, a user may determine the initialization pattern through the processor.



Heterogeneous memory system

Tue, 26 May 2015 08:00:00 EDT

A heterogeneous memory system includes a main memory arrangement, a first-level cache, and a memory management unit (MMU). The first-level cache includes an SRAM arrangement and a DRAM arrangement. The MMU is configured and arranged to read first data from the main memory arrangement in response to a stored first value associated with the first data and indicative of a start time. The MMU selects one of the SRAM arrangement or the DRAM arrangement for storage of the first data and stores the first data in the selected one of the SRAM arrangement or DRAM arrangement. The MMU reads second data from one of the SRAM arrangement or DRAM arrangement and writes the data to the main memory arrangement in response to a stored second value associated with the second data and indicative of a duration.



Optimizing a cache back invalidation policy

Tue, 26 May 2015 08:00:00 EDT

A method, a system and a computer program product for enhancing a cache back invalidation policy by utilizing least recently used (LRU) bits and presence bits in selecting cache-lines for eviction. A cache back invalidation (CBI) utility evicts cache-lines by using presence bits to avoid replacing a cache-line in a lower level cache that is also present in a higher level cache. Furthermore, the CBI utility selects the cache-line for eviction from an LRU group. The CBI utility ensures that dormant cache-lines in the higher level caches do not retain corresponding presence bits set in the lower level caches by unsetting the presence bits in the lower level cache when a line is replaced in the higher level cache. Additionally, when a processor core becomes idle, the CBI utility invalidates the corresponding higher level cache by unsetting the corresponding presence bits in the lower level cache.



Single instance buffer cache method and system

Tue, 26 May 2015 08:00:00 EDT

Provided is a method and system for reducing duplicate buffers in buffer cache associated with a storage device. Reducing buffer duplication in a buffer cache includes accessing a file reference pointer associated with a file in a deduplicated filesystem when attempting to load a requested data block from the file into the buffer cache. To determine if the requested data block is already in the buffer cache, aspects of the invention compare a fingerprint that identifies the requested data block against one or more fingerprints identifying a corresponding one or more sharable data blocks in the buffer cache. A match between the fingerprint of the requested data block and the fingerprint from a sharable data block in the buffer cache indicates that the requested data block is already loaded in buffer cache. The sharable data block in buffer cache is used instead thereby reducing buffer duplication in the buffer cache.



Cache policies for uncacheable memory requests

Tue, 26 May 2015 08:00:00 EDT

Systems, processors, and methods for keeping uncacheable data coherent. A processor includes a multi-level cache hierarchy, and uncacheable load memory operations can be cached at any level of the cache hierarchy. If an uncacheable load misses in the L2 cache, then allocation of the uncacheable load will be restricted to a subset of the ways of the L2 cache. If an uncacheable store memory operation hits in the L1 cache, then the hit cache line can be updated with the data from the memory operation. If the uncacheable store misses in the L1 cache, then the uncacheable store is sent to a core interface unit. Multiple contiguous store misses are merged into larger blocks of data in the core interface unit before being sent to the L2 cache.



Leveraging transactional memory hardware to accelerate virtualization and emulation

Tue, 26 May 2015 08:00:00 EDT

Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. State isolation can be facilitated by providing isolated private state on transactional memory hardware and storing the stack of a host that is performing an emulation in the isolated private state. Memory accesses performed by a central processing unit can be monitored by software to detect that a guest being emulated has made a self modification to its own code sequence. Transactional memory hardware can be used to facilitate dispatch table updates in multithreaded environments by taking advantage of the atomic commit feature. An emulator is provided that uses a dispatch table stored in main memory to convert a guest program counter into a host program counter. The dispatch table is accessed to see if the dispatch table contains a particular host program counter for a particular guest program counter.



Systems and methods for operating a flash memory file system

Tue, 26 May 2015 08:00:00 EDT

A flash memory file system including a plurality of flash modules. Each of the plurality of flash modules includes a respective cache memory, a respective flash memory, and a respective flash controller in communication with the respective cache memory and the respective flash memory. A first flash module of the plurality of flash modules is configured to receive a file lookup message including a path name for file data stored on a second flash module of the plurality of flash modules. A third flash module of the plurality of flash modules is configured to select the second flash module based on the path name and a directory table, and generate a file metadata message responsive to the file lookup message. The file metadata message identifies the second flash module as containing the file data.



Efficient processing of cache segment waiters

Tue, 26 May 2015 08:00:00 EDT

For a plurality of input/output (I/O) operations waiting to assemble complete data tracks from data segments, a process, separate from a process responsible for the data assembly into the complete data tracks, is initiated for waking a predetermined number of the waiting I/O operations.



Adjustment of the number of task control blocks allocated for discard scans

Tue, 26 May 2015 08:00:00 EDT

A controller receives a request to perform a release space operation. A determination is made that a new discard scan has to be performed on a cache, in response to the received request to perform the release space operation. A determination is made as to how many task control blocks are to be allocated to the perform the new discard scan, based on how many task control blocks have already been allocated for performing one or more discard scans that are already in progress.



Memory storage apparatus, memory controller, and method for transmitting and identifying data stream

Tue, 26 May 2015 08:00:00 EDT

A memory storage apparatus, a memory controller and method for transmitting and identifying data streams are provided. The memory controller passes at least a portion of a data stream received from a host system to a smart card chip of the memory storage apparatus. Then, the host system accurately receives a response message from the smart card chip by executing a plurality of read commands. The memory controller is capable of adding a first verification code to a response data stream sent to the host system, and is capable of adding a write token to each of data segments of the response data stream. The host system confirms the accuracy of the response data stream by verifying the first verification code or by verifying the write token of each of the data segments.



Streaming content storage

Tue, 26 May 2015 08:00:00 EDT

A computing system includes a plurality of dispersed storage (DS) processing units operable to receive a continuous data stream, simultaneously disperse storage error encode the continuous data stream to produce a plurality of encoded data slices and store the plurality of encoded data slices in a DS memory.



Virtualized data storage in a network computing environment

Tue, 26 May 2015 08:00:00 EDT

Methods and systems for load balancing read/write requests of a virtualized storage system. In one embodiment, a storage system includes a plurality of physical storage devices and a storage module operable within a communication network to present the plurality of physical storage devices as a virtual storage device to a plurality of network computing elements that are coupled to the communication network. The virtual storage device comprises a plurality of virtual storage volumes, wherein each virtual storage volume is communicatively coupled to the physical storage devices via the storage module. The storage module comprises maps that are used to route read/write requests from the network computing elements to the virtual storage volumes. Each map links read/write requests from at least one network computing element to a respective virtual storage volume within the virtual storage device.



Sliding-window multi-class striping

Tue, 26 May 2015 08:00:00 EDT

A sequence of storage devices of a data store may include one or more stripesets for storing data stripes of different lengths and of different types. Each data stripe may be stored in a prefix or other portion of a stripeset. Each data stripe may be identified by an array of addresses that identify each page of the data stripe on each included storage device. When a first storage device of a stripeset becomes full, the stripeset may be shifted by removing the full storage device from the stripeset, and adding a next storage device of the data store to the stripeset. A class variable may be associated with storage devices of a stripeset to identify the type of data that the stripeset can store. The class variable may be increased (or otherwise modified) when a computer stores data of a different class in the stripeset.



Distributing capacity slices across storage system nodes

Tue, 26 May 2015 08:00:00 EDT

Various systems and methods are described for configuring a data storage system. In one embodiment, a plurality of actual capacities of a plurality of storage devices of the data storage system are identified and divided into a plurality of capacity slices. The plurality of capacity slices are combined into a plurality of chunks of capacity slices, each having a combination of characteristics of the underlying physical storage devices. The chunks of capacity slices are then mapped to a plurality of logical storage devices. A group of the plurality of logical storage devices is then organized into a redundant array of logical storage devices.



Writing of new data of a first block size in a raid array that stores both parity and data in a second block size

Tue, 26 May 2015 08:00:00 EDT

A Redundant Array of Independent Disks (RAID) controller receives new data that is to be written, wherein the new data is indicated in blocks of a first block size. The RAID controller reads old data, and old parity that corresponds to the old data, stored in blocks of a second block size that is larger in size than the first block size. The RAID controller computes new parity based on the new data, the old data, and the old parity. The RAID controller writes the new data and the new parity aligned to the blocks of the second block size, wherein portions of the old data that are not overwritten by the RAID controller are also written to the blocks of the second block size.



Writing of new data of a first block size in a raid array that stores both parity and data in a second block size

Tue, 26 May 2015 08:00:00 EDT

A Redundant Array of Independent Disks (RAID) controller receives new data that is to be written, wherein the new data is indicated in blocks of a first block size. The RAID controller reads old data, and old parity that corresponds to the old data, stored in blocks of a second block size that is larger in size than the first block size. The RAID controller computes new parity based on the new data, the old data, and the old parity. The RAID controller writes the new data and the new parity aligned to the blocks of the second block size, wherein portions of the old data that are not overwritten by the RAID controller are also written to the blocks of the second block size.