Thu, 03 Nov 2016 08:00:00 EDTAccording to various embodiments, an electrode may include at least one layer including a chemical compound including aluminum and titanium.
Thu, 03 Nov 2016 08:00:00 EDTA packaging device for manufacturing the OLED display screen comprises a filling chamber, a transition chamber and a glove box, the glove box is mounted in the filling chamber, a filling pipe is placed in the transition chamber, an isolated cover is provided for separated the transition chamber and the filling chamber, wherein a safe protective cover is further located inside the transition chamber and under the isolated cover, the filling pipe is placed under the safe protective cover in the transition chamber. The touch sensor on the safe protective cover is provided for sensing the position of the filling pipe. If the filling pipe is champed by the safe protective cover, then position of the filling pipe will be readjusted with alarming. The safe protective cover will act a double-protective effect. Then the filling pipe will not be champed by the isolated cover when the filling pipe is replacing.
Thu, 03 Nov 2016 08:00:00 EDTProvided is a method of manufacturing a mask including preparing a support plate, forming a light blocking layer on the support plate, curing a predetermined region of the light blocking layer, and removing other region of the light blocking layer, excluding the predetermined region.
Thu, 03 Nov 2016 08:00:00 EDTA mask frame assembly through which a deposition material to be deposited on a substrate passes, the mask frame assembly includes a frame including an opening, and a mask having first and second ends in a length direction thereof coupled to the frame, in which the mask includes a main body part having a first thickness and including a pattern part, the pattern part including pattern holes through which the deposition material passes and a support part having a second thickness greater than the first thickness and extending away from first and second ends of the main body part.
Thu, 03 Nov 2016 08:00:00 EDTThe fabrication and characterization of large scale inverted organic solar array fabricated using all-spray process is disclosed. Solar illumination has been demonstrated to improve transparent solar photovoltaic devices. The technology using SAM has potential to revolute current silicon-based photovoltaic technology by providing a complete solution processable manufacturing process. The semi-transparent property of the solar module allows for applications on windows and windshields. The inventive modules are more efficient than silicon solar cells in artificial light environments. This significantly expands their use in indoor applications. Additionally, these modules can be integrated into soft fabric substances such as tents, military back-packs or combat uniforms, providing a highly portable renewable power supply for deployed military forces.
Thu, 03 Nov 2016 08:00:00 EDTProvided are a magnetic sensor and a method of fabricating the same. The magnetic sensor includes: hall elements disposed in a substrate, a protection layer disposed on the substrate, a seed layer disposed on the protection layer, and an integrated magnetic concentrator (IMC) formed on the seed layer, the seed layer and the IMC each having an uneven surface.
Thu, 03 Nov 2016 08:00:00 EDTA method of manufacturing a light emitting device can be provided. The method includes: providing a package having side walls which define a recess; disposing a light emitting element in the recess; injecting a sealing material in the recess of the package, sedimenting centrifugally the fluorescent material particles toward a bottom surface in the recess to form a sealing member that comprises a first sealing member portion and a second sealing member portion; and curing the binder to form a cured sealing member. The sealing material includes a binder and fluorescent material particles that includes particles of fluoride fluorescent material that have a composition including tetravalent manganese ions, at least one selecting from the group consisting of alkali metal elements and NH4+ and at least one selecting from the group consisting of Group 4 elements and Group 14 elements. The first sealing member portion covers the light emitting element, and includes a first binder portion and the fluorescent material particles located in the first binder portion. The second sealing member portion covers the first sealing portion, and includes a second binder portion and substantially no fluorescent material particles located in the second binder portion. The particles of fluoride fluorescent material include a surface region and an inner region, both the surface region and the inner region comprising tetravalent manganese ions. A tetravalent manganese ion concentration of the surface region of the particles of fluoride fluorescent material is lower than a tetravalent manganese ion concentration of the inner region of the particles of fluoride fluorescent material.
Thu, 03 Nov 2016 08:00:00 EDTThe present application provides a method of continuous flow synthesis of core/shell quantum dots doped polymer mats (QD-MAT), including mixing a first core precursor with a second core precursor and feeding the reaction mixture into a first furnace to obtain quantum dot cores; feeding a first shell precursor and a second shell precursor into a second furnace and simultaneously injecting the quantum dot cores to obtain core/shell quantum dots; mixing the core/shell quantum dots with a polymer solution to obtain a QD-polymer composite; and introducing the QD-polymer composite to an electrospinning system to fabricate the core/shell quantum dots doped polymer mats. The present application also provides a method of correcting emission spectrum of light emitting devices with the core/shell quantum dots doped polymer mats with light diffusing properties which can be used to replace the diffuser layer of light emitting devices.
Thu, 03 Nov 2016 08:00:00 EDTThe invention relates to a method for forming at least one metal contact on a surface of a semiconductor and a device with at least one metal contact. The method is used for forming at least one metal contact (60) on a surface (11) of a semiconductor (10) and comprises the steps of: applying a metal layer (20) onto the semiconductor surface (11), applying a mask (40, 50) onto the metal layer (20), and structuring at least the metal layer (20) using the mask (40, 50), wherein lateral deposits (21) of the metal are produced on the mask by the structuring so that the mask is embedded between the deposits (21) and the structured metal layer (20′) after the structuring. The method is characterized by a conductive hard mask.Since the mask is conductive, it can remain embedded in the metal. It is not necessary to remove the deposits. The deposits and the mask form a part of the contact.
Thu, 03 Nov 2016 08:00:00 EDTA method of making a CZTS/inorganic thin-film tandem solar cell including depositing a textured buffer layer on a substrate, depositing a metal-inorganic film from a eutectic alloy on the buffer layer, and depositing additional elements in CZTS forming a CZTS layer based on the metal from the metal-inorganic film, the metal being incorporated into the CZTS film.
Thu, 03 Nov 2016 08:00:00 EDTEmbodiments relate to the detection of semiconductor tampering with a light-sensitive circuit. A tamper detection device for an integrated circuit includes a light-sensitive circuit disposed within a package of an integrated circuit. The light-sensitive circuit closes in response to an exposure to a light source, indicating a tamper condition.
Thu, 03 Nov 2016 08:00:00 EDTA photovoltaic cell having a graded doped region such as a graded emitter and methods of making photovoltaic cells having graded doped regions such as a graded emitter are disclosed. Doping is adjusted across a surface to minimize resistive (I2R) power losses. The graded emitters provide a gradual change in sheet resistance over the entire distance between the lines. The graded emitter profile may have a lower sheet resistance near the metal lines and a higher sheet resistance farther from the metal line edges. The sheet resistance is graded such that the sheet resistance is lower where I2R power losses are highest due to current crowding. One advantage of graded emitters over selective emitters is improved efficiency. An additional advantage of graded emitters over selective emitters is improved ease of aligning metallization to the low sheet resistance regions.
Thu, 03 Nov 2016 08:00:00 EDTAn encapsulated integrated photodetector waveguide structures with alignment tolerance and methods of manufacture are disclosed. The method includes forming a waveguide structure bounded by one or more shallow trench isolation (STI) structure(s). The method further includes forming a photodetector fully landed on the waveguide structure.
Thu, 03 Nov 2016 08:00:00 EDTProvided is a method of manufacturing a semiconductor device according to the present invention, a ring-shaped electrode plate 18 with an opening having a diameter smaller than a diameter of a semiconductor wafer W is disposed between a first electrode plate 14 and a second electrode plate 16, the semiconductor wafer W is arranged between the ring-shaped electrode plate 18 and the second electrode plate 16, and a glass film is formed on a glass film forming scheduled surface in a state where a potential lower than a potential V2 of the second electrode plate 16 is applied to the ring-shaped electrode plate 18. According to the method of manufacturing a semiconductor device of the present invention, even when the glass film forming step is performed using the semiconductor wafer where the base insulating film is formed on the glass film forming scheduled surface as the semiconductor wafer, lowering of deposition efficiency of fine glass particles on the outer peripheral portion of the semiconductor wafer can be suppressed and hence, highly reliable semiconductor devices can be manufactured with high productivity.
Thu, 03 Nov 2016 08:00:00 EDTEmbodiments of the invention provide a method of forming a group III-V material utilized in thin film transistor devices. In one embodiment, a gallium arsenide based (GaAs) layer with or without dopants formed from a solution based precursor may be utilized in thin film transistor devices. The gallium arsenide based (GaAs) layer formed from the solution based precursor may be incorporated in thin film transistor devices to improve device performance and device speed. In one embodiment, a thin film transistor structure includes a gate insulator layer disposed on a substrate, a GaAs based layer disposed over the gate insulator layer, and a source-drain metal electrode layer disposed adjacent to the GaAs based layer.
Thu, 03 Nov 2016 08:00:00 EDTA method for producing a semiconductor device includes forming a first fin-shaped silicon layer and a second fin-shaped silicon layer on a substrate using a sidewall formed around a dummy pattern on the substrate. A first insulating film is formed around the first fin-shaped silicon layer and the second fin-shaped silicon layer. A first pillar-shaped silicon layer is formed in an upper portion of the first fin-shaped silicon layer, and a second pillar-shaped silicon layer is formed in an upper portion of the second fin-shaped silicon layer.
Thu, 03 Nov 2016 08:00:00 EDTA fin-like field-effect transistor (FinFET) device is disclosed. The device includes a semiconductor substrate having a source/drain region, a plurality of isolation regions over the semiconductor substrate and a source/drain feature in the source/drain region. The source/drain feature includes a multiple plug-type portions over the substrate and each of plug-type portion is isolated each other by a respective isolation region. The source/drain feature also includes a single upper portion over the isolation regions. Here the single upper portion is merged from the multiple plug-type portions. The single upper portion has a flat top surface facing away from a top surface of the isolation region.
Thu, 03 Nov 2016 08:00:00 EDTMethods of forming a layer of silicon germanium include forming an epitaxial layer of Si1-xGex on a silicon substrate, wherein the epitaxial layer of Si1-xGex has a thickness that is less than a critical thickness, hc, at which threading dislocations form in Si1-xGex on silicon; etching the epitaxial layer of Si1-xGex to form Si1-xGex pillars that define a trench in the epitaxial layer of Si1-xGex, wherein the trench has a height and a width, wherein the trench has an aspect ratio of height to width of at least 1.5; and epitaxially growing a suspended layer of Si1-xGex from upper portions of the Si1-xGex pillars, wherein the suspended layer defines an air gap in the trench beneath the suspended layer of Si1-xGex.
Thu, 03 Nov 2016 08:00:00 EDTA semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well.
Thu, 03 Nov 2016 08:00:00 EDTSome embodiments include methods of forming charge storage transistor gates and standard FET gates in Which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.
Thu, 03 Nov 2016 08:00:00 EDTA semiconductor device includes a first fin structure for a first fin field effect transistor (FET). The first fin structure includes a first base layer protruding from a substrate, a first intermediate layer disposed over the first base layer and a first channel layer disposed over the first intermediate layer. The first fin structure further includes a first protective layer made of a material that prevents an underlying layer from oxidation. The first channel layer is made of SiGe, the first intermediate layer includes a first semiconductor (e.g., SiGe) layer disposed over the first base layer and a second semiconductor layer (e.g., Si) disposed over the first semiconductor layer. The first protective layer covers side walls of the first base layer, side walls of the first semiconductor layer and side walls of the second semiconductor layer.
Thu, 03 Nov 2016 08:00:00 EDTA method of manufacturing a fin field effect transistor is provided. A double spacer protective layer comprising an outer spacer (the first spacer) and an inner spacer (the second spacer) is formed on both sides of the gate, and the thickness of the outer spacer can be adjusted to accurately control the distance between the source/drain ion implantation area and the channel, so as to solve the problem of the hot carrier injection effect caused by the distance being too close between the channel and the source/drain area; in addition, the outer spacers and the inner spacers can be formed by only two film deposition and etching processes without adding a photolithography mask, which can effectively prevent the contact between the gate and the source/drain, so as to substantially reduce the parasitic capacitance.
Thu, 03 Nov 2016 08:00:00 EDTThis invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.
Thu, 03 Nov 2016 08:00:00 EDTAn organic light emitting diode (OLED) display includes a substrate in which an emission area and a non-emission area are defined, an OLED disposed in the emission area. The OLED display further includes a thin film transistor disposed in the non-emission area, a first insulation layer overlapping the thin film transistor in the non-emission area, a first storage capacitance electrode disposed in the emission area on the first insulation layer, a second insulation layer disposed to cover the first storage capacitance electrode and the thin film transistor except a portion of the thin film transistor, said portion of the thin film transistor being exposed through the second insulation later. The OLED display further includes an organic protective layer disposed on the second insulation layer, and an anode electrode of the OLED disposed on the second insulation layer, the anode electrode electrically connected to the thin film transistor.
Thu, 03 Nov 2016 08:00:00 EDTEmbodiments of the present disclosure provide a method for producing a TFT array substrate and a method for producing a display apparatus. The method for producing the TFT array substrate includes forming a semiconductor layer onto a substrate, and forming a shading pattern onto the semiconductor layer at a position at least corresponding to a channel region of the semiconductor layer, wherein the shading pattern contacts with the semiconductor layer; forming a transparent electrode of ITO material onto the substrate formed with the shading pattern, and removing the shading pattern after forming the transparent electrode.
Thu, 03 Nov 2016 08:00:00 EDTA method of manufacturing a semiconductor device includes forming on a lower structure, a first stack structure in which first material layers and second material layers are alternately stacked, forming, on the first stack structure, a second stack structure in which third material layers and fourth material layers are alternately stacked, forming preliminary holes penetrating the second stack structure, forming a fifth material layer covering the preliminary holes on the second stack structure to define a first air-gap inside the preliminary holes, and forming through holes connected to the preliminary holes by penetrating from the fifth material layer overlapping the preliminary holes to the first stack structure.
Thu, 03 Nov 2016 08:00:00 EDTA method of forming narrow and wide lines includes forming mandrels separated by wider gaps and narrower gaps, forming sidewall spacers on sides of the gaps, and then removing the mandrels. Subsequent anisotropic etching extends through an underlying mask layer at locations between sidewall spacers that were formed in wider gaps, to thereby separate narrow line portions of the mask layer, without extending through the mask layer at locations between sidewall spacers that were formed in narrower gaps, thereby leaving wide line portions of the mask layer under the second sidewall spacers.
Thu, 03 Nov 2016 08:00:00 EDTEmbodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with three-dimensional (3D) integration of multiple dies, as well as corresponding fabrication methods and systems incorporating such 3D IC package assemblies. A bumpless build-up layer (BBUL) package substrate may be formed on a first die, such as a microprocessor die. Laser radiation may be used to form an opening in a die backside film to expose TSV pads on the back side of the first die. A second die, such as a memory die stack, may be coupled to the first die by die interconnects formed between corresponding TSVs of the first and second dies. Underfill material may be applied to fill some or all of any remaining gap between the first and second dies, and/or an encapsulant may be applied over the second die and/or package substrate. Other embodiments may be described and/or claimed.
Thu, 03 Nov 2016 08:00:00 EDTA method of making a semiconductor component package can include providing a substrate comprising conductive traces, soldering a surface mount device (SMD) to the substrate with solder, encapsulating the SMD on the substrate with a first mold compound over and around the SMD to form a component assembly, and mounting the component assembly to a temporary carrier with a first side of the component assembly oriented towards the temporary carrier. The method can further include mounting a semiconductor die comprising a conductive interconnect to the temporary carrier adjacent the component assembly, encapsulating the component assembly and the semiconductor die with a second mold compound to form a reconstituted panel, and exposing the conductive interconnect and the conductive traces at the first side and the second side of the component assembly with respect to the second mold compound.
Thu, 03 Nov 2016 08:00:00 EDTA method of forming a package on package (PoP) structure includes forming a first die package, and bonding an external connector of a second die package to a solder paste layer of the first die package. The forming the first die package includes forming a contact pad over a substrate, attaching a metal ball with a convex surface to the contact pad, and applying a solder paste layer over a distal end of the metal ball and leaving at least a portion of the metal ball without solder paste. The forming the first die package also includes attaching a semiconductor die to the substrate, and forming a molding compound between the semiconductor die and the metal ball, where the solder paste layer has a first portion extending above an upper surface of the molding compound and a second portion extending below the upper surface of the molding compound.
Thu, 03 Nov 2016 08:00:00 EDTA method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.
Thu, 03 Nov 2016 08:00:00 EDTA method for manufacturing a semiconductor device according to the present invention includes: (a) disposing, on a substrate (insulating substrate), a bonding material having a sheet shape and having sinterability; (b) disposing a semiconductor element on the bonding material after the (a); and (c) sintering the bonding material while applying pressure to the bonding material between the substrate and the semiconductor clement. The bonding material includes particles of Ag or Cu, and the particles are coated with an organic film.
Thu, 03 Nov 2016 08:00:00 EDTA method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface.
Thu, 03 Nov 2016 08:00:00 EDTA method of forming a solder bump on a substrate includes: forming a conductive layer(s) on the substrate having a surface on which an electrode pad is prepared; forming a resist layer on the conductive layer(s) having an opening over the electrode pad; forming a metal pillar in the opening of the resist layer, wherein the metal pillar includes a first conductive material; forming a space between sidewalls of the resist layer and the metal pillar; forming a metal barrier layer in the space and on a top surface of the metal pillar, the metal barrier layer including a second conductive material that is different from the first conductive material of the metal pillar; forming a solder layer on the metal barrier layer over the top surface of the metal pillar; removing the resist layer; removing the conductive layer(s); and forming the solder bump by reflowing the solder layer.
Thu, 03 Nov 2016 08:00:00 EDTA process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces.
Thu, 03 Nov 2016 08:00:00 EDTA semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer.
Thu, 03 Nov 2016 08:00:00 EDTIn a method of forming a mark pattern according to the embodiments, a film to be processed on a substrate is coated with a photosensitive film, and the photosensitive film is irradiated with exposure light via a mask. On the mask, a first circuit pattern having a first transmittance and a mark having a second transmittance and used to measure a superposition between films are arranged. By irradiating with the exposure light, a second circuit pattern having a first film thickness and a mark pattern having a second film thickness thinner than the first film thickness are formed on the substrate.
Thu, 03 Nov 2016 08:00:00 EDTSome novel features pertain to an integrated device package that includes a die, an electromagnetic (EM) passive device, an encapsulation layer covering the die and the EM passive device, and a redistribution portion coupling the die and the EM passive device. In some implementations, the EM passive device includes an electromagnetic (EM) passive device. The EM passive device includes a base layer, a via traversing the base layer, a pad coupled to the via, and at least redistribution layer configured to operate as electromagnetic (EM) passive component, where the redistribution layer is coupled to the pad. The redistribution portion of the EM passive device includes at least one redistribution layer that is configured to electrically couple the die to the EM passive device. The redistribution portion includes at least one redistribution layer that is configured as an electromagnetic (EM) shield.
Thu, 03 Nov 2016 08:00:00 EDTA method is for making an electronic device and includes forming an interconnect layer stack on a sacrificial substrate and having a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers. The method also includes laminating and electrically joining through an intermetallic bond a liquid crystal polymer (LCP) substrate to the interconnect layer stack on a side thereof opposite the sacrificial substrate. The method further includes removing the sacrificial substrate to expose a lowermost patterned electrical conductor layer, and electrically coupling at least one first device to the lowermost patterned electrical conductor layer.
Thu, 03 Nov 2016 08:00:00 EDTA device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device.
Thu, 03 Nov 2016 08:00:00 EDTForming a semiconductor arrangement includes non-destructively determining a first spacer height of a first sidewall spacer adjacent a dummy gate and a second spacer height of a second sidewall spacer adjacent the dummy gate based upon a height of a photoresist as measured using optical critical dimension (OCD) spectroscopy. When the photoresist is sufficiently uniform, a hard mask etch is performed to remove a hard mask from the dummy gate and to remove portions of sidewall spacers of the dummy gate. A gate electrode is formed between the first sidewall spacer and the second sidewall spacer to form a substantially uniform gate. Controlling gate formation based upon photoresist height as measured by OCD spectroscopy provides a non-destructive manner of promoting uniformity.
Thu, 03 Nov 2016 08:00:00 EDTA method for correcting a surface profile on a substrate is described. In particular, the method includes receiving a substrate having a heterogeneous layer composed of a first material and a second material, wherein the heterogeneous layer has an initial upper surface exposing the first material and the second material, and defining a first surface profile across the substrate. The method further includes setting a target surface profile for the heterogeneous layer, selectively removing at least a portion of the first material using a gas cluster ion beam (GCIB) etching process, and recessing the first material beneath the second material, and thereafter, selectively removing at least a portion of the second material to achieve a final upper surface exposing the first material and the second material, and defining a second surface profile, wherein the second surface profile is within a pre-determined tolerance of the target surface profile.
Thu, 03 Nov 2016 08:00:00 EDTA semiconductor fin including a single crystalline semiconductor material is formed on a dielectric layer. A semiconductor shell including an epitaxial semiconductor material is formed on all physically exposed surfaces of the semiconductor fin by selective epitaxy, which deposits the semiconductor material only on semiconductor surfaces and not on dielectric surfaces. The epitaxial semiconductor material can be different from the single crystalline semiconductor material, and the semiconductor shell can be bilaterally strained due to lattice mismatch. A fin field effect transistor including a strained channel can be formed. Further, the semiconductor shell can advantageously alter properties of the source and drain regions, for example, by allowing incorporation of more dopants or by facilitating a metallization process.
Thu, 03 Nov 2016 08:00:00 EDTImpurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.
Thu, 03 Nov 2016 08:00:00 EDTA method for producing a semiconductor device includes forming a first fin-shaped semiconductor layer and a second fin-shaped semiconductor layer on a substrate using a sidewall formed around a dummy pattern on the substrate. A first insulating film is formed around the first fin-shaped semiconductor layer and the second fin-shaped semiconductor layer. A first pillar-shaped semiconductor layer is formed in an upper portion of the first fin-shaped semiconductor layer, and a second pillar-shaped semiconductor layer is formed in an upper portion of the second fin-shaped semiconductor layer.
Thu, 03 Nov 2016 08:00:00 EDTThe present application relates to an optical planarizing layer etch process. Embodiments include forming fins separated by a dielectric layer; forming a recess in the dielectric layer on each side of each fin, each recess being for a metal gate; forming sidewall spacers on each side of each recess; depositing a high-k dielectric liner in each recess and on a top surface of each of the fins; depositing a metal liner over the high-k dielectric layer; depositing a non-conformal organic layer (NCOL) over a top surface of the dielectric layer to pinch-off a top of each recess; depositing an OPL and ARC over the NCOL; etching the OPL, ARC and NCOL over a portion of the dielectric layer and recesses in a first region; and etching the portion of the recesses to remove residual NCOL present at a bottom of each recess of the portion of the recesses.
Thu, 03 Nov 2016 08:00:00 EDTGuiding pattern portions are formed on a surface of a lithographic material stack that is disposed on a surface of a semiconductor substrate. A copolymer layer is then formed between each neighboring pair of guiding pattern portions and thereafter a directed self-assembly process is performed that causes phase separation of the various polymeric domains of the copolymer layer. Each guiding pattern portion is selectively removed, followed by the removal of each first phase separated polymeric domain. Each second phase separated polymeric domain remains and is used as an etch mask in forming semiconductor fins in an upper semiconductor material portion of the semiconductor substrate.
Thu, 03 Nov 2016 08:00:00 EDTA performance optimized CMOS FET structure and methods of manufacture are disclosed. The method includes forming source and drain regions for a first type device and a second type device. The method further includes lowering the source and drain regions for the first type device, while protecting the source and drain regions for the second type device. The method further includes performing silicide processes to form silicide regions on the lowered source and drain regions for the first type device and the source and drain regions for the second type device.
Thu, 03 Nov 2016 08:00:00 EDTMethods and systems for fabricating bidirectional devices on both surfaces of a semiconductor wafer. Separation of the second handle wafer is accomplished by patterning a seal layer to form a grid before the second handle wafer is separated.
Thu, 03 Nov 2016 08:00:00 EDTWe disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer. A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.
Thu, 03 Nov 2016 08:00:00 EDTA semiconductor device includes a substrate including a first region and a second region, first conductive patterns disposed on the first region and spaced apart from each other by a first distance, second conductive patterns disposed on the second region and spaced apart from each other by a second distance greater than the first distance, and an interlayer insulating layer disposed between the second conductive patterns and including at least one recess region having a width corresponding to the first distance.
Thu, 03 Nov 2016 08:00:00 EDTDisclosed is a rear surface-protective film making it possible to watch, across this rear surface-protective film, a crack of a semiconductor element through an infrared camera, and the like. is the invention relates to a rear surface-protective film for protecting a rear surface of a semiconductor element, the film having a parallel light transmittance of 15% or more at a wavelength of 800 nm. The ratio of the parallel light transmittance at a wavelength of 800 nm to the parallel light transmittance at a wavelength of 532 nm in the rear surface-protective film is preferably 2 or more.
Thu, 03 Nov 2016 08:00:00 EDTThe film for a semiconductor device has a plurality of films with attached dicing tape for the backside of a flip-chip type semiconductor arranged on a separator at a prescribed interval and an outer sheet arranged outside the film with attached dicing tape for the backside of a flip-chip type semiconductor; the film with attached dicing tape for the backside of a flip-chip type semiconductor has a dicing tape and a film for the backside of a flip-chip type semiconductor; and when the length of the narrowest portion of the outer sheet is set to G and the length from the long side of the separator to the dicing tape is set to F, G is within the range from 0.2 times to 0.95 times F.
Thu, 03 Nov 2016 08:00:00 EDTMethods and apparatus for processing a substrate are provided herein. In some embodiments, an apparatus for processing a substrate includes a process chamber having an internal processing volume disposed beneath a dielectric lid of the process chamber; a substrate support disposed in the process chamber and having a support surface to support a substrate; an inductive coil disposed above the dielectric lid to inductively couple RF energy into the internal processing volume to form a plasma above the substrate support; and a first inductive applicator ring coupled to a lift mechanism to position the first inductive applicator ring within the internal processing volume.
Thu, 03 Nov 2016 08:00:00 EDTA method of forming a molding layer includes the following operations: forming a substrate having at least one column structure thereon; flipping over the substrate having the column structure such that the column structure is beneath the substrate; dipping the column structure of the flipped substrate into a molding material fluid contained in a container; and separating the column structure of the flipped substrate from the container to form a molding layer covering and in contact with the column structure.
Thu, 03 Nov 2016 08:00:00 EDTThe present invention provides a process for selectively etching molybdenum or titanium relative to a oxide semiconductor film, including providing a substrate comprising a layer of oxide semiconductor and a layer comprising molybdenum or titanium on the layer of oxide semiconductor; preparing the substrate by applying a photoresist layer over the layer comprising molybdenum or titanium, and then patterning and developing the photoresist layer to form an exposed portion of the layer comprising molybdenum or titanium; providing a composition comprising ammonia or ammonium hydroxide, a quaternary ammonium hydroxide and a peroxide; and applying the composition to the exposed portion for a time sufficient to etch and remove the exposed portion of the layer comprising molybdenum or titanium, wherein the etching selectively removes the molybdenum or titanium relative to the oxide semiconductor.
Thu, 03 Nov 2016 08:00:00 EDTEmbodiments of methods and apparatus for correcting substrate deformity are provided herein. In some embodiments, a substrate flattening system includes: a first process chamber having a first substrate support and a first showerhead, wherein the first substrate support does not include a chucking mechanism; a first heater disposed in the first substrate support to heat a substrate placed on a first support surface of the first substrate support; a second heater configured to heat a process gas flowing through the first showerhead into a first processing volume of the first process chamber; and a second process chamber having a second substrate support, wherein the second substrate support is not heated, and wherein the first process chamber and the cooling chamber are both non-vacuum chambers.
Thu, 03 Nov 2016 08:00:00 EDTA method and composition for removing bulk and/or ion-implanted resist material from microelectronic devices have been developed. The compositions effectively remove the ion-implanted resist material while not damaging the silicon-containing or germanium-containing materials.
Thu, 03 Nov 2016 08:00:00 EDTIn accordance with an embodiment, a manufacturing method of a semiconductor device includes forming, on a substrate, protruding portions with first films on the surfaces thereof, respectively, forming a second film different from the first films so as to fill a depressed portion between the protruding portions and to cover the protruding portions, processing in such a manner that the top surface of the second film on the depressed portion is higher than the top surface of the second film on the protruding portions after forming the second film to cover the protruding portions, and polishing the second film on the depressed and protruding portions to expose the first films.
Thu, 03 Nov 2016 08:00:00 EDTA method for etching a silicon film formed on a substrate includes supplying HBr gas, NF3 gas, and O2 gas into a chamber and performing a plurality of etching processes on the silicon film with a plasma generated by the supplied HBr gas, NF3 gas, and O2 gas, gradually reducing a flow rate of the HBr gas during the plurality of etching processes, and adjusting a flow rate of the O2 gas according to the reduction of the HBr gas.
Thu, 03 Nov 2016 08:00:00 EDTMethods for selectively depositing a metal silicide layer are provided herein. In some embodiments, a method of selectively depositing a metal silicide layer includes: (a) providing a substrate having a first layer to a process chamber, wherein the first layer comprises a first surface and a feature formed in the first surface comprising an opening defined by one or more sidewalls and a bottom surface wherein the sidewalls comprise one of silicon oxide or silicon nitride and wherein the bottom surface comprises at least one of silicon or germanium; (b) exposing the substrate to a precursor gas comprising a metal halide; (c) purging the precursor gas from the process chamber using an inert gas; (d) exposing the substrate to a silicon containing gas; (e) purging the silicon containing gas from the process chamber using an inert gas; (f) repeating (b)-(e) to selectively deposit a metal silicide along the bottom surface to a predetermined thickness; and (g) annealing the substrate after depositing the metal silicide layer.
Thu, 03 Nov 2016 08:00:00 EDTThe present invention provides methods for using single source organometallic precursors in the fabrication of polycrystalline Group III-Group V compounds, preferably semiconductor compounds. The present invention teaches how to select organometallic ligands in single-source precursors in order to control the stoichiometry of the corresponding Group III-Group V compounds derived from these precursors. The present invention further teaches how to anneal precursors in the presence of one or more flux agents in order to increase the crystalline grain size of polycrystalline Group III-Group V compounds derived from organometallic precursors. This helps to provide Group III-Group V semiconductors with better electronic properties. The flux layer also helps to control the stoichiometry of the Group III-Group V compounds.
Thu, 03 Nov 2016 08:00:00 EDTA method of forming a semiconducting material includes depositing a graded buffer on a substrate to form a graded layer of an indium (In) containing III-V material, the In containing III-V material being indium-gallium-arsenic (InGaAs) or indium-aluminum-arsenic (InAlAs) and comprising In in an increasing atomic gradient up to 35 atomic % (at. %) based on total atomic weight of InGa or InAl; and forming a layer of InGaAs on the graded layer, the layer of InGaAs comprising about 25 to about 100 at. % In based on total atomic weight of InGa.
Thu, 03 Nov 2016 08:00:00 EDTA film forming method for forming a nitride film on a workpiece substrate accommodated within a process vessel, including: performing a first reaction of supplying a first precursor gas to the workpiece substrate accommodated within the process vessel; performing a second reaction of supplying a second precursor gas to the workpiece substrate accommodated within the process vessel; performing a modification of generating plasma of a modifying gas just above the workpiece substrate by supplying the modifying gas into the process vessel and supplying microwaves from an antenna into the process vessel, and plasma-processing, by the plasma thus generated, a surface of the workpiece substrate subjected to the first and second reactions using the first and second precursor gases.
Thu, 03 Nov 2016 08:00:00 EDTA substrate processing apparatus including: a reaction tube configured to process a plurality of substrates; a heater configured to heat an inside of the reaction tube; a holder configured to arrange and hold the plurality of substrates within the reaction tube; a hydrogen-containing gas supply system including a first nozzle disposed in an area which horizontally surrounds a substrate arrangement area where the plurality of substrates are arranged, and configured to supply a hydrogen-containing gas from a plurality of locations of the area into the reaction tube; an oxygen-containing gas supply system including a second nozzle disposed in the area which horizontally surrounds the substrate arrangement area, and configured to supply an oxygen-containing gas from a plurality of locations of the area into the reaction tube; a pressure controller configured to control a pressure inside the reaction tube to be lower than an atmospheric pressure; and a controller configured to control the heater, the hydrogen-containing gas supply system, the oxygen-containing gas supply system and the pressure controller such that the hydrogen-containing gas and the oxygen-containing gas are supplied simultaneously into the reaction tube accommodating the plurality of substrates and being under a heated atmosphere having a pressure lower than an atmospheric pressure through the first nozzle and the second nozzle, respectively, so that the hydrogen-containing gas and the oxygen-containing gas react with each other in the area which horizontally surrounds the substrate arrangement area to form a reactive species in the reaction tube, thereby thermally oxidizing each of the plurality of substrates by the reactive species, wherein the first nozzle is provided with a plurality of first gas ejection holes, and the second nozzle is provided with as many second gas ejection holes as at least the plurality of substrates such that at least each of the second gas ejection holes corresponds to each of the plurality of substrates is disclosed.
Thu, 03 Nov 2016 08:00:00 EDTA polymer includes a first moiety represented by Chemical Formula 1, and a second moiety including a substituted or unsubstituted C6 to C60 cyclic group, a substituted or unsubstituted C6 to C60 hetero cyclic group, or a combination thereof: In Chemical Formula 1, X is phosphorus (P), nitrogen (N), boron (B), or P═O, Y1 and Y2 are independently hydrogen or a moiety including at least one substituted or unsubstituted benzene ring, provided that at least one of Y1 and Y2 is the moiety including at least one substituted or unsubstituted benzene ring, Y3 is another moiety including at least one substituted or unsubstituted benzene ring, and * is a linking point.
Thu, 03 Nov 2016 08:00:00 EDTMethods and systems for depositing material layers with gap variation between film deposition operations. One method includes depositing a material layer over a substrate. The depositing is performed in a plasma chamber having a bottom electrode and a top electrode. The method includes providing a substrate over the bottom electrode in the plasma chamber. The method sets a first gap between the bottom and top electrodes and performs plasma deposition to deposit a first film of the material layer over the substrate while the first gap is set between the bottom and top electrodes. The method then sets a second gap between the bottom a top electrodes and performs plasma deposition to deposit a second film of the material layer over the substrate while the second gap is set between the bottom and top electrodes. The material layer is defined by the first and second films and the first gap is varied to the second gap to offset expected non-uniformities when depositing the first film followed by the second film.
Thu, 03 Nov 2016 08:00:00 EDTMethods for the formation of SiCN, SiCO and SiCON films comprising cyclical exposure of a substrate surface to a silicon-containing gas, a carbon-containing gas and a plasma. Some embodiments further comprise the addition of an oxidizing agent prior to at least the plasma exposure.
Thu, 03 Nov 2016 08:00:00 EDTMethods of depositing a film selectively onto a first substrate surface relative to a second substrate surface. Methods include soaking a substrate surface comprising hydroxyl-terminations with a silylamine to form silyl ether-terminations and depositing a film onto a surface other than the silyl ether-terminated surface.
Thu, 03 Nov 2016 08:00:00 EDTA film where a first layer and a second layer are laminated is formed on a substrate by performing: forming the first layer by performing a first cycle a predetermined number of times, the first cycle including non-simultaneously performing: supplying a source to the substrate, and supplying a reactant to the substrate, under a first temperature at which neither the source nor the reactant is thermally decomposed when the source and the reactant are present alone, respectively; and forming the second layer by performing a second cycle a predetermined number of times, the second cycle including non-simultaneously performing: supplying the source to the substrate, and supplying the reactant to the substrate, under a second temperature at which neither the source nor the reactant is thermally decomposed when the source and the reactant are present alone, respectively, the second temperature being different from the first temperature.
Thu, 03 Nov 2016 08:00:00 EDTAn ICP A plasma reactor having an enclosure wherein at least part of the ceiling forms a dielectric window. A substrate support is positioned within the enclosure below the dielectric window. An RF power applicator is positioned above the dielectric window to radiate RF power through the dielectric window and into the enclosure. A plurality of gas injectors are distributed uniformly above the substrate support to supply processing gas into the enclosure. A circular baffle is situated inside the enclosure and positioned above the substrate support but below the plurality of gas injectors so as to redirect the flow of the processing gas.
Thu, 03 Nov 2016 08:00:00 EDTA method of making a non-toxic perovskite/inorganic thin-film tandem solar cell including the steps of depositing a textured oxide buffer layer on an inexpensive substrate, depositing a metal-inorganic film from a eutectic alloy on the buffer layer; and depositing perovskite elements on the metal-inorganic film, thus forming a perovskite layer based on a metal from the metal-inorganic film, incorporating the metal into the perovskite layer.
Thu, 03 Nov 2016 08:00:00 EDTA method of making a non-toxic perovskite/inorganic thin-film tandem solar cell including the steps of depositing a textured oxide buffer layer on an inexpensive substrate, depositing a metal-inorganic film from a eutectic alloy on the buffer layer; and depositing perovskite elements on the metal-inorganic film, thus forming a perovskite layer based on a metal from the metal-inorganic film, incorporating the metal into the perovskite layer.
Thu, 03 Nov 2016 08:00:00 EDTA method includes patterning a layer over a substrate with a first metal pattern; using a cut mask in a first position relative to the substrate to perform a first cut patterning for removing material from a first region within the first pattern; and using the same cut mask to perform a second cut patterning while in a second position relative to the same layer over the substrate, for removing material from a second region in a second metal pattern of the same layer over the substrate.
Thu, 03 Nov 2016 08:00:00 EDTA method for producing a semiconductor device, which includes forming an underlayer film on a semiconductor substrate with a resist underlayer film forming composition that contains a solvent, and a polymer containing a unit structure of Formula (2): O—Ar2—O—Ar3-T-Ar4 Formula (2) where Ar2, Ar3, and Ar4 are individually a C6-50 arylene group or an organic group containing a heterocyclic group; at least one of Ar3 and Ar4 is a phenylene group; and T is a carbonyl group. The resist underlayer film forming composition has a solid content of 0.1 to 70 mass % of a total mass of the composition.
Thu, 03 Nov 2016 08:00:00 EDTA patterned photoresist is provided atop a substrate. A hardening agent is applied to the patterned photoresist to provide a polymeric coated patterned photoresist. The polymeric coated patterned photoresist is baked to provide a hardened photoresist, and subsequent the baking step, the polymeric coating is removed from the hardened photoresist by rinsing. The hardened photoresist can be removed anytime during the patterning of the substrate by an aqueous resist developer.
Thu, 03 Nov 2016 08:00:00 EDTA manufacturing method of a liquid crystal display includes: providing a thin film transistor on a substrate; providing a pixel electrode connected to the thin film transistor; providing a microcavity layer including a liquid crystal material on the pixel electrode; providing a supporting member layer on the microcavity layer; patterning the supporting member layer to form a plurality of recess portions therein; and providing a plurality of touch signal lines for transmitting a touch signal in the plurality of recess portions.
Thu, 03 Nov 2016 08:00:00 EDTAn optical coupling may involve orienting a waveguide and a lens such that light rays are focused on a surface. The lens may involve the use of a material having a variable refractive index to focus rays of light along first axis and a curved surface to focus the rays of light along a second axis.
Thu, 03 Nov 2016 08:00:00 EDTThe present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a substrate, a transistor structure having a treated layer adjacent to the channel region, an isolation layer, and a dielectric layer in an opening of the isolation layer on the treated layer. The dielectric layer and the treated layer are disposed on opposite side of the transistor from a gate structure. The treated layer may be a lightly doped channel layer or a depleted layer.
Thu, 03 Nov 2016 08:00:00 EDTA polishing agent comprises: a fluid medium; an abrasive grain containing a hydroxide of a tetravalent metal element; a first additive; a second additive; and a third additive, wherein: the first additive is at least one selected from the group consisting of a compound having a polyoxyalkylene chain and a vinyl alcohol polymer; the second additive is a cationic polymer; and the third additive is an amino group-containing sulfonic acid compound.
Thu, 03 Nov 2016 08:00:00 EDTA method for manufacturing a MEMS device is disclosed. Moreover a MEMS device and a module including a MEMS device are disclosed. An embodiment includes a method for manufacturing MEMS devices includes forming a MEMS stack on a first main surface of a substrate, forming a polymer layer on a second main surface of the substrate and forming a first opening in the polymer layer and the substrate such that the first opening abuts the MEMS stack.
Thu, 03 Nov 2016 08:00:00 EDTA process for manufacturing a semiconductor package having a hollow chamber includes providing a bottom substrate having a bottom plate, a ring wall and a slot, wherein the ring wall and the bottom plate form the slot; forming an under ball metallurgy layer on a surface of the ring wall; bumping a plurality of solder balls on a surface of the under ball metallurgy layer, each of the solder balls comprises a diameter, wherein a spacing is spaced apart between two adjacent solder balls; performing reflow soldering to the solder balls for making the solder balls melting and interconnecting to form a connection layer; connecting a top substrate to the bottom substrate, wherein the lot of the bottom substrate is sealed by the top substrate to form a hollow chamber used for accommodating an electronic device.
Thu, 03 Nov 2016 08:00:00 EDTA method and system for preparing a semiconductor wafer are disclosed. In a first aspect, the method comprises providing a passivation layer over a patterned top metal on the semiconductor wafer, etching the passivation layer to open a bond pad in the semiconductor wafer using a first mask, depositing a protection layer on the semiconductor wafer, patterning the protective layer using a second mask, and etching the passivation layer to open other electrodes in the semiconductor wafer using a third mask. The system comprises a MEMS device that further comprises a first substrate and a second substrate bonded to the first substrate, wherein the second substrate is prepared by the aforementioned steps of the method.