Thu, 25 Aug 2016 08:00:00 EDTA deposition apparatus comprises a chamber, a deposition material supplier positioned in the chamber and configured to contain and supply a deposition material, a substrate holder disposed in the chamber and configured to hold a substrate such that a major surface of the substrate faces the deposition material supplier; and a mask retainer disposed in the chamber and configured to retain a mask disposed over the major surface of the substrate. The mask retainer comprises a base, and a plurality of magnets coupled to the base, at least one of the plurality of magnets being movable with respect to the base, the plurality of magnets being configured to apply magnetic force to the mask such that the mask is fixed to the substrate without substantial movement of the mask with respect to the substrate during deposition of the deposition material.
Thu, 25 Aug 2016 08:00:00 EDTIn an aspect, an organic light-emitting display apparatus and a method of manufacturing the same are provided. The organic light-emitting display apparatus may include a substrate; a display unit formed on the substrate; and a thin film encapsulating layer encapsulating the display unit. The thin film encapsulating layer may include a plurality of organic layers and inorganic layers that are laminated alternately. At least one of the plurality of the inorganic films may include a first layer formed of a first material, a second layer formed of a second material other than the first material, and an intermediate layer provided between the first and second layers.
Thu, 25 Aug 2016 08:00:00 EDTThe present invention provides a substrate packaging method, comprising steps of: step 1: providing a base substrate and a packaging substrate; step 2: disposing a circle of inorganic insulation film on the packaging substrate; step 3: disposing a circle of ultraviolet (UV) sealant outside the circle of inorganic insulation film on the packaging substrate; step 4: oppositely adhering the packaging substrate to the base substrate; and step 5, utilizing an ultraviolet (UV) light source to irradiate the UV sealant so as to cure the UV sealant in order to package the packaging substrate and the base substrate. The packaging method can improve the packaging effect, increase the ability for resisting the water vapor and the oxygen, and extend the life of the OLED device.
Thu, 25 Aug 2016 08:00:00 EDTThere is provided a peeling method capable of preventing a damage to a layer to be peeled. Thus, not only a layer to be peeled having a small area but also a layer to be peeled having a large area can be peeled over the entire surface at a high yield. Processing for partially reducing contact property between a first material layer (11) and a second material layer (12) (laser light irradiation, pressure application, or the like) is performed before peeling, and then peeling is conducted by physical means. Therefore, sufficient separation can be easily conducted in an inner portion of the second material layer (12) or an interface thereof.
Thu, 25 Aug 2016 08:00:00 EDTAn embodiment of the present invention provides a method for producing a flexible display panel. The method includes the following steps of: providing a bearing substrate and a transparent substrate arranged with the flexible display panel; setting a laser irradiation path and irradiating the bearing substrate by using a laser along the set laser irradiation path to form a mark region on the bearing substrate; placing the flexible display panel on the mark region correspondingly; irradiating from a side of the transparent substrate by re-using the laser along the set laser irradiation path, to peel off the flexible display panel from the transparent substrate; and separating the flexible display panel from the mark region on the bearing substrate to obtain the flexible display panel.
Thu, 25 Aug 2016 08:00:00 EDTA method of manufacturing a mask includes aligning a mask substrate comprising a thin film at a processing position, forming a coating layer comprising a cleaning solution material on a first surface of the mask substrate, forming a deposition pattern on a second surface of the mask substrate, and removing the coating layer from the mask substrate comprising the deposition pattern.
Thu, 25 Aug 2016 08:00:00 EDTSome embodiments include a memory array having a first series of access/sense lines which extend along a first direction, a second series of access/sense lines over the first series of access/sense lines and which extend along a second direction substantially orthogonal to the first direction, and memory cells vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. The memory cells have programmable material. At least some of the programmable material within each memory cell is a polygonal structure having a sidewall that extends along a third direction which is different from the first and second directions. Some embodiments include methods of forming memory arrays.
Thu, 25 Aug 2016 08:00:00 EDTThe present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode; a spacer surrounding the capping layer; and, a top electrode on the capping layer having a smaller width than the resistive material layer. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer.
Thu, 25 Aug 2016 08:00:00 EDTA memory device includes: a memory layer that is isolated for each memory cell and stores information by a variation of a resistance value; an ion source layer that is formed to be isolated for each memory cell and to be laminated on the memory layer, and contains at least one kind of element selected from Cu, Ag, Zn, Al and Zr and at least one kind of element selected from Te, S and Se; an insulation layer that isolates the memory layer and the ion source layer for each memory cell; and a diffusion preventing barrier that is provided at a periphery of the memory layer and the ion source layer of each memory cell to prevent the diffusion of the element.
Thu, 25 Aug 2016 08:00:00 EDTA technique relates magnetoresistive random access memory (MRAM). A dielectric layer is disposed on a transistor, and the transistor is formed in a uniform crystalline substrate. A hole is formed through the dielectric layer to reach the transistor. A polycrystalline material is disposed in the hole by using selective epitaxial growth (SEG), and the polycrystalline material is annealed to create an epitaxial stud. A magnetic tunnel junction (MTJ) is disposed on the epitaxial stud (SEG).
Thu, 25 Aug 2016 08:00:00 EDTA semiconductor device includes a piezoelectric layer interposed between a first metal layer and a hardmask layer. A first trench extends through the hardmask layer, the piezoelectric layer and the first metal layer. A self-limiting second trench extends through the hardmask layer and the piezoelectric layer without reaching the first metal layer.
Thu, 25 Aug 2016 08:00:00 EDTMethods for fabricating a piezoelectric device are provided. The methods can include providing a substrate and forming a nanocrystalline diamond layer on a first surface of the substrate. The methods can also include depositing a piezoelectric layer on a first surface of the nanocrystalline diamond layer.
Thu, 25 Aug 2016 08:00:00 EDTSingle source precursors, methods to synthesize single source precursors and methods to deposit nanowire based thin films using single source precursors for high efficiency thermoelectric devices are provided herein. In some embodiments, a method of forming a single source precursor includes mixing a first compound with one of SbX3, SbX5, Sb2(SO4)3 or with one of BiX3, Bi(NO3)3, Bi(OTf)3, Bi(PO4), Bi(OAc)3, wherein the first compound is one of a lithium selenolate, a lithium tellurolate, a monoselenide, or a monotelluride.
Thu, 25 Aug 2016 08:00:00 EDTTo provide a semiconductor element that can have the high adhesion between a substrate made of an oxide or the like and a metal film, a semiconductor element includes a substrate made of an oxide, a semiconductor element structure provided on an upper surface of the substrate, and a metal film provided on a lower surface of the substrate, in which the metal film contains nanoparticles made of an oxide.
Thu, 25 Aug 2016 08:00:00 EDTA method of producing a semiconductor component includes providing an optoelectronic semiconductor chip; applying a molding compound for an optical element, wherein the molding compound is based on a highly refractive polymer material; precuring the molding compound at a temperature of at most 50° C.; and curing the molding compound.
Thu, 25 Aug 2016 08:00:00 EDTA Light-Emitting Diode (LED) includes a light-emitting structure having a passivation layer disposed on vertical sidewalls across a first doped layer, an active layer, and a second doped layer that completely covers at least the sidewalls of the active layer. The passivation layer is formed by plasma bombardment or ion implantation of the light-emitting structure. It protects the sidewalls during subsequent processing steps and prevents current leakage around the active layer.
Thu, 25 Aug 2016 08:00:00 EDTA method of manufacturing a horizontal power LED device includes constructing a light-emitting structure on a substrate, etching the light-emitting structure, fabricating an electrode, forming an insulating film, forming a metal substrate, removing the substrate from the light-emitting structure, and forming an n-pad. A high-power and high-efficiency horizontal LED device is manufactured by the method of manufacturing the same.
Thu, 25 Aug 2016 08:00:00 EDTThere is provided a method for producing a Group III nitride semiconductor light-emitting device having a low driving voltage, which is realized by steeply increasing the concentration of Mg within a p-type semiconductor layer. This production method includes the steps of forming an n-type contact layer, forming an n-side high electrostatic breakdown voltage layer, forming an n-side superlattice layer, forming a light-emitting layer, forming a p-type cladding layer, forming a p-type intermediate layer, and forming a p-type contact layer. The step of forming the p-type cladding layer includes supplying a dopant gas without supplying a first raw material gas (TMG) containing a Group III element during a first period TA1 and supplying the first raw material gas (TMG) and the dopant gas during a second period TA2 after the first period TA1 so as to grow a semiconductor layer.
Thu, 25 Aug 2016 08:00:00 EDTA method for designing and fabricating a device that forces atoms to emit spectrums. The method utilizes a proton-electron pair theory and the shell orbit velocity-radius product law based on Rydberg formula which has been confirmed experimentally with Hydrogen Gas Lamp refuting not only Bohr's photon emission hypothesis but also band gap theory. The method improves not only the performance and quality of LED but also reduces heat loss as well as production costs thereof.
Thu, 25 Aug 2016 08:00:00 EDTPhotovoltaic modules may include multiple flexible thin film photovoltaic cells electrically connected in series, and laminated to a substantially transparent top sheet having a conductive grid pattern facing the cells. Methods of manufacturing photovoltaic modules including integrated multi-cell interconnections are provided. Methods may include steps of coordinating, integrating, and registering multiple rolls of substrates in continuous processes.
Thu, 25 Aug 2016 08:00:00 EDTThe invention disclosed an additive for preparing suede on a polycrystalline silicon chip. The invention also provides a suede preparation liquid for preparing suede on a polycrystalline silicon chip, comprising: an acid solution and the aforementioned additive for preparing suede on a polycrystalline silicon chip. The invention also provides a method for preparing suede on a polycrystalline silicon chip, by using which suede can be prepared on the surface of a polycrystalline silicon chip with the foregoing suede preparation liquid.
Thu, 25 Aug 2016 08:00:00 EDTA method for manufacturing polysilicon thin film transistor is disclosed, and the method comprises the following steps: forming a semiconductor material layer on a prefabricated substrate; forming an intermediate layer on the semiconductor material layer; forming a photoresist layer on the intermediate layer, and exposing the photoresist layer with a photomask for a first time; moving the prefabricated substrate in a predetermined direction relative to the photomask, and exposing the photoresist layer with the photomask for a second time; forming a photoresist region which comprises a central part and a wing part and a hollowed-out region which contains no photoresist material in the photoresist layer; and forming an ion lightly doped region corresponding to the wing part and an ion heavily doped region corresponding to the hollowed-out region in the semiconductor material layer.
Thu, 25 Aug 2016 08:00:00 EDTAn improvement is achieved in the reliability of a semiconductor device. Over a semiconductor substrate, a silicon film, for the memory gate electrode of a memory cell in a nonvolatile memory is formed via an insulating film so as to cover the control gate electrode of the memory cell. After the silicon film and the insulating film are removed from a peripheral circuit region, a silicon film for the gate electrode of a MISFET is formed over the silicon film over a memory cell region of the semiconductor substrate and over the peripheral circuit region thereof. After the silicon film is patterned to form a gate electrode over the peripheral circuit region, the insulating film is removed from the memory cell region. Then, over the silicon film over the memory cell region, an oxide film is formed. Subsequently, the oxide film, and, the silicon film over the silicon film over the memory cell region are etched back to form the memory gate electrode adjacent to the control gate electrode via the insulating film.
Thu, 25 Aug 2016 08:00:00 EDTPower Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.
Thu, 25 Aug 2016 08:00:00 EDTIn a semiconductor device including an oxide semiconductor, the amount of oxygen vacancies is reduced. Moreover, electrical characteristics of a semiconductor device including an oxide semiconductor are improved. The semiconductor device includes a transistor including a gate electrode over a substrate, a gate insulating film covering the gate electrode, an oxide semiconductor film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the oxide semiconductor film; and over the transistor, a first insulating film covering the gate insulating film, the oxide semiconductor film, and the pair of electrodes; and a second insulating film covering the first insulating film. An etching rate of the first insulating film is lower than or equal to 10 nm/min and lower than an etching rate of the second insulating film when etching is performed at 25° C. with 0.5 weight % of hydrofluoric acid.
Thu, 25 Aug 2016 08:00:00 EDTThe present disclosure provides devices and methods which provide for strained epitaxial regions. A method of semiconductor fabrication is provided that includes forming a gate structure over a fin of a semiconductor substrate and forming a recess in the fin adjacent the gate structure. A sidewall of the recess is then altered. Exemplary alterations include having an altered profile, treating the sidewall, and forming a layer on the sidewall. An epitaxial region is then grown in the recess. The epitaxial region interfaces the altered sidewall of the recess and is a strained epitaxial region.
Thu, 25 Aug 2016 08:00:00 EDTA FinFET and methods for forming a FinFET are disclosed. A method includes forming trenches in a semiconductor substrate to form a fin, depositing an insulating material within the trenches, and removing a portion of the insulating material to expose sidewalls of the fin. The method also includes recessing a portion of the exposed sidewalls of the fin to form multiple recessed surfaces on the exposed sidewalls of the fin, wherein adjacent recessed surfaces of the multiple recessed surfaces are separated by a lattice shift. The method also includes depositing a gate dielectric on the recessed portion of the sidewalls of the fin and depositing a gate electrode on the gate dielectric.
Thu, 25 Aug 2016 08:00:00 EDTThis invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.
Thu, 25 Aug 2016 08:00:00 EDTThe high-voltage transistor device comprises a semiconductor substrate (1) with a source region (2) of a first type of electrical conductivity, a body region (3) including a channel region (4) of a second type of electrical conductivity opposite to the first type of conductivity, a drift region (5) of the first type of conductivity, and a drain region (6) of the first type of conductivity extending longitudinally in striplike fashion from the channel region (4) to the drain region (6) and laterally confined by isolation regions (9). The drift region (5) comprises a doping of the first type of conductivity and includes an additional region (8) with a net doping of the second type of conductivity to adjust the electrical properties of the drift region (5). The drift region depth and the additional region depth do not exceed the maximal depth (17) of the isolation regions (9).
Thu, 25 Aug 2016 08:00:00 EDTA method of making a semiconductor device is provided. The method includes forming a deep well (DWELL) and a well (WELL) in a first region of a substrate, the WELL adjacent a surface of the substrate so that an interface between the WELL and DWELL is exposed on the surface of the substrate. A channel for a DEMOS transistor is formed in the first region over the interface and includes a first channel formed in the WELL and a second channel formed in the DWELL. A gate layer is deposited and patterned to concurrently form in the first region a first gate for the DEMOS transistor and in a second region a second gate for an ESD device. Dopants are implanted in the first and second regions to concurrently form a drain extension of the DEMOS transistor, and an ESD diffusion region of the ESD device.
Thu, 25 Aug 2016 08:00:00 EDTA lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.
Thu, 25 Aug 2016 08:00:00 EDTA method for preventing damage to the insulator layer of a semiconductor device during creation of fin field effect transistor (FinFET) includes obtaining a material stack having an active semiconductor layer, an insulator layer, and an etch stop layer between the active semiconductor layer and the insulator layer; forming a fin-array from the active semiconductor layer; patterning the fin-array; and fabricating a FinFET device from the patterned fin-array; where the etch stop layer is resistant to processes the etch stop layer is exposed to during the forming, patterning, and fabricating operations, such that the etch stop layer and the insulator layer are not damaged during the forming, patterning, and fabricating operations.
Thu, 25 Aug 2016 08:00:00 EDTAn integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates.
Thu, 25 Aug 2016 08:00:00 EDTA first organic resin layer is formed over a first substrate; a first insulating film is formed over the first organic resin layer; a first element layer is formed over the first insulating film; a second organic resin layer is formed over a second substrate; a second insulating film is formed over the second organic resin layer; a second element layer is formed over the second insulating film; the first substrate and the second substrate are bonded; a first separation step in which adhesion between the first organic resin layer and the first substrate is reduced; the first organic resin layer and a first flexible substrate are bonded with a first bonding layer; a second separation step in which adhesion between the second organic resin layer and the second substrate is reduced; and the second organic resin layer and a second flexible substrate are bonded with a second bonding layer.
Thu, 25 Aug 2016 08:00:00 EDTA RRAM device having a diode device structure coupled to a variable resistance layer is disclosed. The diode device structure can either be embedded into or fabricated over the substrate. A memory device having an array of said RRAM devices can be fabricated with multiple common bit lines and common word lines.
Thu, 25 Aug 2016 08:00:00 EDTA color filter array and micro-lens structure for imaging system and method of forming the color filter array and micro-lens structure. A micro-lens material is used to fill the space between the color filters to re-direct incident radiation, and form a convex micro-lens structure above a top surface of the color filters.
Thu, 25 Aug 2016 08:00:00 EDTAn inorganic film is dry-etched using plasma with a photoresist pattern serving as a mask, and an organic film is dry-etched using plasma with the photoresist pattern serving as a mask without exposing a pad electrode. The photoresist pattern is removed using a stripping solution. After the removal of the photoresist pattern using a stripping solution, the organic film is etched to expose the pad electrode with the inorganic film that remains after the dry etching of the inorganic film using plasma serving as a mask.
Thu, 25 Aug 2016 08:00:00 EDTA method for manufacturing a thin film transistor array substrate includes: forming a polysilicon layer on the substrate; forming a gate insulating layer on the polysilicon layer; forming a metal oxide layer on the gate insulating layer; forming a gate metal layer on the metal oxide layer; etching the metal oxide layer to define a gate; using the gate as a second mask and etching the metal oxide layer excluding a scope of the second mask; performing ion-implantation by using the gate and a remainder of the metal oxide layer as a third mask to form two lightly doped drain regions at opposite sides of the polysilicon layer; forming an insulating layer on the gate and the gate insulating layer respectively; forming a metal layer on the insulating layer and defining a drain and a source which connect to the doped drain region and the doped source region respectively.
Thu, 25 Aug 2016 08:00:00 EDTAn array substrate manufacturing method, including: forming an active layer of a thin film transistor, in which photoresist with a partial thickness at a location corresponding to a channel area between source/drain electrodes of the thin film transistor on the active layer is reserved; forming a source/drain metal layer, and further forming source/drain electrodes; lifting off the photoresist with the partial thickness on the channel area between the source/drain electrodes, The array substrate manufacturing method can avoid damaging the metal oxide layer in the etching process for source/drain electrodes, and lower production cost, simplify processes, and increase yield and product profit.
Thu, 25 Aug 2016 08:00:00 EDTThree-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.
Thu, 25 Aug 2016 08:00:00 EDTA method of arranging a multiplicity of LEDs in packaging units includes defining a desired range for at least one photometric measurement variable for each of the packaging units; selecting an LED from the multiplicity of LEDs not yet arranged in one of the packaging units; measuring the at least one photometric measurement variable for the selected LED; equipping one of the packaging units containing fewer than N−1 LEDs with the selected LED; storing a measured value and a position of the selected LED in the packaging unit in a memory; repeating until the packaging units are equipped with N−1 LEDs; repeating and calculating the average value of the photometric measurement variable, equipping a packaging unit for which the calculated average value of the variable lies in a defined range with the selected LED; and storing the measured value and the position of the selected LED.
Thu, 25 Aug 2016 08:00:00 EDTEmbodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.
Thu, 25 Aug 2016 08:00:00 EDTA method of manufacturing an array of semiconductor device packages includes placing a plurality of semiconductor chips on a temporary carrier, covering the plurality of semiconductor chips with an encapsulation material to form an encapsulation body, providing a plurality of microwave components each including at least one electrically conducting wall structure integrated in the encapsulation body, forming a plurality of electrical interconnects each configured to electrically couple a semiconductor chip and a microwave component, and separating the encapsulation body into single semiconductor device packages each including a semiconductor chip, a microwave component and an electrical interconnect.
Thu, 25 Aug 2016 08:00:00 EDTA package according to an embodiment includes a first device package and a fan-out RDL disposed over the first device package. The fan-out RDL extends past edges of the first device package. The first device package comprises a first die having a first redistribution layer (RDL) disposed on a first substrate, a second die having a second RDL disposed on a second substrate, an isolation material over the first die and extending along sidewalls of the second die, and a conductive via. The first RDL is bonded to the second RDL, and the first die and the second die comprise different lateral dimensions. At least a portion of the conductive via extends from a top surface of the isolation material to contact a first conductive element in the first RDL.
Thu, 25 Aug 2016 08:00:00 EDTA wire bonding method includes the following steps. First, a substrate including at least one metal finger is provided. Next, a first chip including at least one first boding pad is disposed on the substrate. Next, a metal ball bump is foamed on the corresponding metal finger. Next, a first wire is formed from the metal ball bump toward the corresponding first boding pad. Next, a first free air ball is formed on the first wire by electronic flame-off process. Then, the first free air ball connected to the first wire is pressed on the corresponding first boding pad, such that the first wire is located between the first free air ball and the corresponding first boding pad.
Thu, 25 Aug 2016 08:00:00 EDTA package structure is disclosed, which includes a substrate having a body, a plurality of conductive pads formed on the body and a surface passivation layer formed on the body and having a plurality of openings for exposing the conductive pads; a plurality of conductive vias formed in the openings of the surface passivation layer and electrically connected to the conductive pads; a plurality of circuits formed on the surface passivation layer and electrically connected to the conductive vias, wherein the circuits have, a plurality of electrical contacts; at least a pattern portion formed on the surface passivation layer and intersecting with the circuits; and a second passivation layer formed on the surface passivation layer, the circuits and the pattern portion d having a plurality of openings for exposing portions of the electrical contacts of the circuits, thereby strengthening the bonding between the circuits and the passivation layers.
Thu, 25 Aug 2016 08:00:00 EDTA manufacturing method for semiconductor devices includes the steps of forming an Ni/Au film that includes an Ni film and an Au film formed over the Ni film over a wiring that is coupled to each of a plurality of electrode pads formed over a principal surface of a semiconductor wafer and arranges each of the electrode pads at a different position, grinding a back surface of the semiconductor wafer, performing reduction treatment on a surface of the Ni/Au film, and forming a solder bump over the Ni/Au film. In the reduction treatment, respective processes of flux application, reflow soldering and cleaning are performed and the solder bump is bonded to the Ni/Au film after the reduction treatment has been completed. Thereby, bonding reliability in flip chip bonding of a semiconductor device is improved.
Thu, 25 Aug 2016 08:00:00 EDTTwo microelectronic components (110, 120), e.g. a die and an interposer, are bonded to each other. One of the components' contact pads (110C) include metal, and the other component has silicon (410) which reacts with the metal to form metal silicide (504). Then a hole (510) is made through one of the components to reach the metal silicide and possibly even the unreacted metal (110C) of the other component. The hole is filled with a conductor (130), possibly metal, to provide a conductive via that can be electrically coupled to contact pads (120C.B) attachable to other circuit elements or microelectronic components, e.g. to a printed circuit board.
Thu, 25 Aug 2016 08:00:00 EDTA device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer.
Thu, 25 Aug 2016 08:00:00 EDTPass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.