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ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

Thu, 06 Apr 2017 08:00:00 EDT

An organic light emitting display (OLED) device includes a substrate, a plurality of first electrodes, a plurality of light emitting layers, a second electrode, a power supply line, a third electrode, and an encapsulation member. The third electrode that is formed on the power supply line and the second electrode that is formed on the light emitting layers extend to a contact region that is in a peripheral region of the substrate. The third electrode and the second electrodes have an uneven pattern in the contact region.



COMPOSITION FOR FORMING ORGANIC SEMICONDUCTOR FILM, ORGANIC SEMICONDUCTOR FILM AND METHOD FOR MANUFACTURING SAME, ORGANIC SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING SAME, AND ORGANIC SEMICONDUCTOR COMPOUND

Thu, 06 Apr 2017 08:00:00 EDT

Objects of the present invention are to provide a composition for forming an organic semiconductor film that has excellent preservation stability and makes the obtained organic semiconductor element exhibit excellent driving stability in the atmosphere, to provide an organic semiconductor film using the composition for forming an organic semiconductor film, a method for manufacturing the organic semiconductor film, an organic semiconductor element, a method for manufacturing the organic semiconductor element, and to provide a novel organic semiconductor compound. A composition for forming an organic semiconductor film of the present invention contains a specific organic semiconductor having an alkoxyalkyl group as a component A and a solvent as a component B, in which a content of a non-halogen-based solvent is equal to or greater than 50% by mass with respect to a total content of the component B, and a content of the component A is equal to or greater than 0.7% by mass and less than 15% by mass.



METHOD FOR MANUFACTURING A DISPLAY UNIT

Thu, 06 Apr 2017 08:00:00 EDT

A method for manufacturing a display unit is provided, and the method includes forming a first insulating film, forming a plurality of first electrodes on the first insulating film, forming a second insulating film on the first electrodes, forming a plurality of openings corresponding to the first electrodes, forming a plurality of organic layers formed in a shape of a stripe having notch parts, forming a second electrode on the organic layer having the notch parts is formed, and forming a protective film on the second electrode.



DEVICE AND METHODS FOR MANUFACTURING AN ORGANIC LIGHT-EMITTING DISPLAY APPARATUS

Thu, 06 Apr 2017 08:00:00 EDT

A method of manufacturing an organic light-emitting display apparatus includes: arranging a mask on a substrate, the mask having an opening corresponding to a pattern of an organic emission layer; forming the organic emission layer by disposing an inkjet roller on the mask, and discharging inks from ink headers mounted in the inkjet roller through the opening of the mask, by rotating the inkjet roller; and curing the organic emission layer.



DOUBLE SPIN FILTER TUNNEL JUNCTION

Thu, 06 Apr 2017 08:00:00 EDT

A memory device that includes a first magnetic insulating tunnel barrier reference layer present on a first non-magnetic metal electrode, and a free magnetic metal layer present on the first magnetic insulating tunnel barrier reference layer. A second magnetic insulating tunnel barrier reference layer may be present on the free magnetic metal layer, and a second non-magnetic metal electrode may be present on the second magnetic insulating tunnel barrier. The first and second magnetic insulating tunnel barrier reference layers are arranged so that their magnetizations are aligned to be anti-parallel.



METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT

Thu, 06 Apr 2017 08:00:00 EDT

A method for manufacturing a semiconductor element includes providing a wafer having a sapphire substrate and a semiconductor stacked body disposed on the sapphire substrate, performing a first scanning of a portion of the sapphire substrate in which a laser beam is irradiated into an interior of the sapphire substrate, performing a second scanning of the portion of the sapphire substrate in which a laser beam is irradiated into the interior of the sapphire substrate, the second scanning occurring after the first scanning and before a void is produced in the interior of the sapphire substrate irradiated with the laser beam in the first scanning, and separating the wafer into a plurality of semiconductor elements.



LIGHT EMITTING DEVICE HAVING TRANSPARENT ELECTRODE AND METHOD OF MANUFACTURING LIGHT EMITTING DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

Provided are a light emitting device including a transparent electrode having high transmittance with respect to light in a UV wavelength range as well as in a visible wavelength range and good ohmic contact characteristic with respect to a semiconductor layer and and a method of manufacturing the light emitting device. A transparent electrode of a light emitting device is formed by using a resistance change material which has high transmittance with respect to light in a UV wavelength range and of which resistance state is to be changed from a high resistance state into a low resistance state due to conducting filaments, which current can flow through, formed in the material if a voltage exceeding a threshold voltage inherent in a material applied to the material, so that it is possible to obtain high transmittance with respect to light in a UV wavelength range.



METHOD, PROCESS AND FABRICATION TECHNOLOGY FOR OXIDE LAYERS

Thu, 06 Apr 2017 08:00:00 EDT

This disclosure relates to a Room Temperature Wet Chemical Growth (RTWCG) method and process of SiOX thin film coatings which can be grown on various substrates. The invention further relates to RTWCG method and process suited to grow thin films on the Si substrates used in the manufacture of silicon-based electronic and photonic (optoelectronic) device applications. The invention further relates to processes used to produce SiOX thin film layers for use as passivation layers, low reflectance layers, or high reflectance single layer coatings (SLARC) and selective emitters (SE).



Manufacturing Method of Non-Planar FET

Thu, 06 Apr 2017 08:00:00 EDT

The present invention provides a non-planar FET and a method of manufacturing the same. The non-planar FET includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.



METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

A semiconductor device includes a substrate, a semiconductor fin, a gate stack, and an epitaxy structure. The semiconductor fin is disposed in the substrate. A portion of the semiconductor fin is protruded from the substrate. The gate stack is disposed over the portion of the semiconductor fin protruded from the substrate. The epitaxy structure is disposed on the substrate and adjacent to the gate stack. The epitaxy structure has a top surface facing away the substrate, and the top surface has at least one curved portion having a radius of curvature ranging from about 5 nm to about 20 nm.



FABRICATION OF SHIELDED GATE TRENCH MOSFET WITH INCREASED SOURCE-METAL CONTACT

Thu, 06 Apr 2017 08:00:00 EDT

Forming a semiconductor device on a semiconductor substrate having a substrate top surface includes: forming a gate trench extending from the substrate top surface into the semiconductor substrate; forming a gate electrode in the gate trench; forming a curved sidewall portion along at least a portion of a sidewall of the gate trench; forming a body region adjacent to the gate trench; forming a source region embedded in the body region, including disposing source material in a region that is along at least a part of the curved sidewall portion; forming a gate top dielectric layer over the gate electrode and having a top side that is below at least a portion of the source region; and forming a metal layer over at least a portion of a gate trench opening and at least a portion of the source region.



METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT

Thu, 06 Apr 2017 08:00:00 EDT

Techniques related to a method for manufacturing an integrated circuit is disclosed. According to one embodiment, a method for manufacturing an integrated circuit on a wafer comprises a first device of the integrated circuit is formed on the wafer and a second device of the integrated circuit is formed on the wafer to make a projection area of the second device overlap with a projection area of the first device partially or completely. In one embodiment, two or more devices are formed in different layers of the integrated circuit, or formed at different depths in a same layer of the integrated circuit, so the two or more devices may share an area on the same wafer in a certain manner. Thereby, the area of the chip is saved and the chip cost of the integrated circuit is significantly reduced.



MECHANISMS FOR FORMING IMAGE SENSOR DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

A method for forming an image sensor device is provided. The method includes forming a photodetector in a semiconductor substrate and forming a shielding layer over the semiconductor substrate. The method also includes forming a dielectric layer over the shielding layer and partially removing the dielectric layer to form a recess. The method further includes partially removing the shielding layer through the recess. In addition, the method includes forming a filter in the recess after the shielding layer is partially removed.



METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY APPARATUS

Thu, 06 Apr 2017 08:00:00 EDT

An organic light emitting display includes a pixel circuit to supply current to an organic light emitting device. The pixel circuit includes a switching transistor and a driving transistor. The switching transistor includes a first insulating layer between a first gate electrode and an oxide semiconductor layer. The driving transistor includes a second gate electrode on an active layer. The first insulating layer is between the active layer and the second gate electrode.



METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

The present disclosure provides a method of manufacturing a three dimensional memory device to suppress warpage of conductive patterns. The method may include providing a multilayered structure in which different material layers are alternately stacked over a substrate, etching partially the material layers to form a multi-step structure, each step being formed of at least one pair of the material layers, forming vertical support layers, each support layer being disposed on a top face of each step, removing partially the material layers to form recesses, filling the recesses with a conductive material to form gate lines, the gate line defining an upper portion of the step, and forming vertical contact plugs respectively on the upper portion of the step.



NON-VOLATILE SPLIT GATE MEMORY CELLS WITH INTEGRATED HIGH K METAL GATE, AND METHOD OF MAKING SAME

Thu, 06 Apr 2017 08:00:00 EDT

A method of forming a pair of memory cells that includes forming a polysilicon layer over and insulated from a semiconductor substrate, forming a pair of conductive control gates over and insulated from the polysilicon layer, forming first and second insulation layers extending along inner and outer side surfaces of the control gates, removing portions of the polysilicon layer adjacent the outer side surfaces of the control gates, forming an HKMG layer on the structure and removing portions thereof between the control gates, removing a portion of the polysilicon layer adjacent the inner side surfaces of the control gates, forming a source region in the substrate adjacent the inner side surfaces of the control gates, forming a conductive erase gate over and insulated from the source region, forming conductive word line gates laterally adjacent to the control gates, and forming drain regions in the substrate adjacent the word line gates.



METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

Thu, 06 Apr 2017 08:00:00 EDT

Methods of manufacturing a semiconductor device are provided. Methods may include forming first to third regions having densities different from one another on a substrate, covering the first to third regions to form an upper interlayer insulating film including a low step portion and a high step portion higher than the low step portion, forming an organic film on the upper interlayer insulating film, removing a part of the organic film to expose an upper surface of the high step portion, removing the high step portion so that an upper surface of the high step portion is disposed on at least the same line as the organic film disposed on the upper surface of the lower step portion, removing the remaining part of the organic film to expose the upper surface of the upper interlayer insulating film and flattening the upper surface of the upper interlayer insulating film.



Offset-Printing Method for Three-Dimensional Package

Thu, 06 Apr 2017 08:00:00 EDT

The present invention discloses an offset-printing method for a three-dimensional 3D-oP (three-dimensional offset-printed memory)-based package. The mask-patterns for different 3D-op dice are merged onto a same data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different 3D-oP dice.



Offset-Printing Method for Three-Dimensional Printed Memory with Multiple Bits-Per-Cell

Thu, 06 Apr 2017 08:00:00 EDT

The present invention discloses an offset-printing method for a three-dimensional printed memory with multiple bits-per-cell. The mask-patterns for different bits-in-a-cell are merged onto a multi-region data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different bits-in-a-cell.



Semiconductor Structure and Manufacturing Method Thereof

Thu, 06 Apr 2017 08:00:00 EDT

A semiconductor structure includes a three dimensional stack including a first semiconductor die and a second semiconductor die. The second semiconductor die is connected with the first semiconductor die with a bump between the first semiconductor die and the second semiconductor die. The semiconductor structure includes a molding compound between the first semiconductor die and the second semiconductor die. A first portion of a metal structure over a surface of the three dimensional stack and contacting a backside of the second semiconductor die and a second portion of the metal structure over the surface of the three dimensional stack and configured for electrically connecting the three dimensional stack with an external electronic device.



DIE STACKING METHOD

Thu, 06 Apr 2017 08:00:00 EDT

A die stacking method is provided. The die stacking method includes executing a manufacturing recipe, and loading an interposer-die mapping file according to the manufacturing recipe. The interposer-die mapping file corresponds to an interposer wafer including interposer dies. The die stacking method also includes loading a combination setting data according to the interposer-die mapping file, and loading a top die number and a top-die ID code of a top-die mapping file according to the combination setting data and the interposer-die mapping file. The top-die ID code corresponds to a top wafer including top dies, and the top die number corresponds to one of the top dies. The die stacking method also includes disposing the one of the top dies of the top wafer on one of the interposer dies of the interposer wafer.



BATTERY PROTECTION PACKAGE AND PROCESS OF MAKING THE SAME

Thu, 06 Apr 2017 08:00:00 EDT

The present invention discloses small-size battery protection packages and provides a process of fabricating small-size battery protection packages. A battery protection package includes a first common-drain metal oxide semiconductor field effect transistor (MOSFET), a second common-drain MOSFET, a power control integrated circuit (IC), a plurality of solder balls, a plurality of conductive bumps, and a packaging layer. The power control IC is vertically stacked on top of the first and second common-drain MOSFETs. At least a majority portion of the power control IC and at least majority portions of the plurality of solder balls are embedded into the packaging layer. The process of fabricating battery protection packages includes steps of fabricating power control ICs; fabricating common-drain MOSFET wafer; integrating the power control ICs with the common-drain MOSFET wafer and connecting pinouts; forming a packaging layer; applying grinding processes; forming a metal layer; and singulating battery protection packages.



Chip-on-Substrate Packaging on Carrier

Thu, 06 Apr 2017 08:00:00 EDT

A method includes mounting a wafer-level package substrate over a carrier, and pre-cutting the wafer-level package substrate to form trenches extending from a top surface of the wafer-level package substrate into the wafer-level package substrate. A plurality of dies is bonded over the wafer-level package substrate. The plurality of dies is molded in a molding material to form a wafer-level package, with the wafer-level package including the wafer-level package substrate, the plurality of dies, and the molding material. The carrier is detached from the wafer-level package. The wafer-level package is sawed into a plurality of packages, with each of the plurality of packages including a portion of the wafer-level package substrate and one of the plurality of dies.



WAFER REINFORCEMENT TO REDUCE WAFER CURVATURE

Thu, 06 Apr 2017 08:00:00 EDT

A semiconductor structure includes filled dual reinforcing trenches that reduce curvature of the semiconductor structure by stiffening the semiconductor structure. The filled dual reinforcing trenches reduce curvature by acting against transverse loading, axial loading, and/or torsional loading of the semiconductor structure that would otherwise result in semiconductor structure curvature. The filled dual reinforcing trenches may be located in an array throughout the semiconductor structure, in particular locations within the semiconductor structure, or at the perimeter of the semiconductor structure.



METHOD OF MANUFACTURING ELEMENT CHIP AND METHOD OF MANUFACTURING ELECTRONIC COMPONENT-MOUNTED STRUCTURE

Thu, 06 Apr 2017 08:00:00 EDT

In a method of manufacturing an element chip for manufacturing a plurality of element chips by dividing a substrate, where the protruding portions, which are exposed element electrodes, are formed on element regions, protection films made of fluorocarbon film are formed on a second surface and side surfaces of the element chip, and a first surface in a gap by exposing the element chip to second plasma after the substrate is divided by etching. Next, the protection films formed on the second surface and the side surfaces of the element chip are removed while leaving at least a part of the protection film formed in the gap by exposing the element chip to third plasma. Therefore, creep-up of a conductive material in a mounting step is suppressed by the left protection film.



SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Thu, 06 Apr 2017 08:00:00 EDT

A method of manufacturing a semiconductor device includes providing a semiconductor substrate including a conductive pad disposed thereon; disposing a polymeric material over the semiconductor substrate and the conductive pad; patterning the polymeric material to form an opening exposing at least a portion of the conductive pad; disposing a conductive layer over the polymeric material and the portion of the conductive pad; and forming a conductor over the portion of the conductive pad and within the opening.



METHODS OF MANUFACTURING A PRINTED CIRCUIT MODULE HAVING A SEMICONDUCTOR DEVICE WITH A PROTECTIVE LAYER IN PLACE OF A LOW-RESISTIVITY HANDLE LAYER

Thu, 06 Apr 2017 08:00:00 EDT

A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned integrated passive die (IPD) attached to the printed circuit substrate. A protective layer is disposed over the thinned IPD to protect passive devices integrated within the thinned IPD, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 103 Ohm-cm.



FORMING A CMOS WITH DUAL STRAINED CHANNELS

Thu, 06 Apr 2017 08:00:00 EDT

The present invention relates generally to a semiconductor device, and more particularly, to a structure and method of forming a compressive strained layer and a tensile strained layer on the same wafer. A lower epitaxial layer may be formed adjacent to a tensile strained layer. An upper epitaxial layer may be formed over a portion of the lower epitaxial layer. Thermal oxidation may convert the upper epitaxial layer to an upper oxide layer, and thermal condensation may causes a portion of the lower epitaxial layer to become a compressive strained layer. The upper oxide layer and a remaining portion of the lower epitaxial layer may be removed, leaving the tensile strained layer and the compressive strained layer.



GATE STRUCTURES WITH VARIOUS WIDTHS AND METHOD FOR FORMING THE SAME

Thu, 06 Apr 2017 08:00:00 EDT

Embodiments of a semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a substrate and a first metal gate structure formed over the substrate. The first metal gate structure has a first width. The semiconductor device structure further includes a first contact formed adjacent to the first metal gate structure and a second metal gate structure formed over the substrate. The second metal gate structure has a second width smaller than the first width. The semiconductor device structure further includes an insulating layer formed over the second metal gate structure and a second contact self-aligned to the second metal gate structure.



Method for Producing a Number of Chip Assemblies and Method for Producing a Semiconductor Arrangement

Thu, 06 Apr 2017 08:00:00 EDT

Method for producing chip assemblies that include semiconductor chip arrangements, each semiconductor chip arrangement including a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.



OPTICAL DEVICE WAFER PROCESSING METHOD

Thu, 06 Apr 2017 08:00:00 EDT

An optical device wafer processing method includes a shield tunnel forming step of applying a pulsed laser beam having a transmission wavelength to a sapphire substrate along an area corresponding to each division line from the back side of the sapphire substrate in the condition where the focal point of the pulsed laser beam is set inside the sapphire substrate, thereby forming a plurality of shield tunnels arranged along the area corresponding to each division line, each shield tunnel being composed of a fine hole and an amorphous region formed around the fine hole for shielding the fine hole. The optical device wafer processing method further includes a dividing step of applying an external force to the optical device wafer after performing a light emitting layer forming step, thereby dividing the optical device wafer along the division lines to obtain the individual optical device chips.



METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE

Thu, 06 Apr 2017 08:00:00 EDT

A method of fabricating a semiconductor package is disclosed. The method includes forming a plurality of semiconductor chips and a mold layer covering the semiconductor chips on a substrate, forming outer terminals on a bottom surface of the substrate, coating a water-soluble material on the bottom surface of the substrate and the outer terminals to form a coating layer, cutting the substrate and the mold layer to separate the semiconductor chips from each other, and forming a shielding layer on the cutted mold layer.



METHOD OF OPTIMIZING WIRE RC FOR DEVICE PERFORMANCE AND RELIABILITY

Thu, 06 Apr 2017 08:00:00 EDT

A method of tailoring BEOL RC parametrics to improve chip performance. According to the method, an integrated circuit design on an integrated circuit chip is analyzed. The analysis comprises calculating Vmax for vias and metal lines in the integrated circuit design over a range of sizes for the vias and the metal lines. Predicted use voltage for applications on the integrated circuit chip is determined. The size or the location of at least one of the vias and the metal lines is tailored based on performance parameters of the integrated circuit chip.



SEMICONDUCTOR DEVICE AND FORMATION THEREOF

Thu, 06 Apr 2017 08:00:00 EDT

A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal plug is over a silicide layer, and the silicide layer is over a metal oxide layer. The metal oxide layer has an oxygen gradient, such that a percentage of oxygen increases from a top surface of the metal oxide layer to a bottom surface of the metal oxide layer. The metal oxide layer unpins the Fermi level of the interface between the metal plug and the substrate, which is exhibited by a lowered Schottky barrier height (SBH) and increased oxygen vacancy states between the V.B. and the C.B. of the metal oxide layer, which decreases the intrinsic resistivity between the metal plug and the substrate as compared to a semiconductor device that lacks such a metal oxide layer.



METHODS FOR DEPOSITING DIELECTRIC BARRIER LAYERS AND ALUMINUM CONTAINING ETCH STOP LAYERS

Thu, 06 Apr 2017 08:00:00 EDT

In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.



Methods of Forming an Integrated Circuit Chip Having Two Types of Memory Cells

Thu, 06 Apr 2017 08:00:00 EDT

An integrated circuit chip includes a first type memory cell and a second type memory cell. The first type memory cell includes a first reference line landing pad and a first word line landing pad. The first reference line landing pad of the first type memory cell and the first word line landing pad of the first type memory cell are aligned along a first direction. The second type memory cell includes a first reference line segment extending along the first direction and a first word line landing pad. The first word line landing pad of the second type memory cell and the first reference line segment of the second type memory cell are spaced apart along a second direction different from the first direction.



METHOD AND DEVICE FOR SURFACE TREATMENT OF SUBSTRATES

Thu, 06 Apr 2017 08:00:00 EDT

A method for surface treatment of an at least primarily crystalline substrate surface of a substrate such that by amorphization of the substrate surface, an amorphous layer is formed at the substrate surface with a thickness d>0 nm of the amorphous layer. This invention also relates to a corresponding device for surface treatment of substrates.



METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

A substrate processing apparatus includes a reception part configured to receive film thickness distribution data of a substrate on which a channel region, an insulating film on the channel region, and a first silicon-containing layer as a portion of a silicon-containing film on the insulating film are formed; a substrate mounting part configured to mount the substrate; and a gas supply part configured to supply a gas to form a second silicon-containing layer as a portion of the silicon-containing film on the first silicon-containing layer to have a film thickness distribution different from a film thickness distribution of the film thickness distribution data, thereby correcting a film thickness of the silicon-containing film.



PLANARIZING PROCESSING METHOD AND PLANARIZING PROCESSING DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

A planarization processing device for polishing a substrate, such as a semiconductor wafer, includes a drive motor that rotates the substrate about a rotational axis. A support plate holds a pad for polishing the substrate such that the surface of the pad faces the surface of the substrate. The surface of the pad contains a catalyst, e.g., composed of a transition metal compound. A liquid that supports a catalytic reaction for polishing the substrate is supplied between the surfaces of the substrate and the pad. A reciprocating drive device causes the support plate to undergo reciprocating motion in a direction parallel to the surface of the pad by at least an amount that makes possible planarization of the substrate based on the catalytic reaction.



Processed Substrate Surface For Epoxy Deposition And Method Thereof

Thu, 06 Apr 2017 08:00:00 EDT

The present invention provides a method for treating a substrate having a surface of deposition, the method comprises providing a hydrophilic coating over the surface of the substrate; and providing a hydrophobic coating on an area of deposition, wherein the area is a dedicated area over the surface of deposition. The dedicated area attributes a contrasting liquid attracting-repelling properties against a remaining area outside the area of deposition. The substrate treated with the above method is also provided.



BASE-ATTACHED ENCAPSULANT FOR SEMICONDUCTOR ENCAPSULATION, METHOD FOR MANUFACTURING BASE-ATTACHED ENCAPSULANT FOR SEMICONDUCTOR ENCAPSULATION, AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS

Thu, 06 Apr 2017 08:00:00 EDT

A base-attached encapsulant for semiconductor encapsulation, includes a base and encapsulating resin layer on one surface of the base, the base being composed of a fibrous base layer in which a thermosetting resin composition containing a thermosetting resin is impregnated into a fibrous base and cured, a cured material layer A composed of a cured material of the thermosetting resin composition formed on the fibrous base layer at the opposite side to the encapsulating resin layer, and a cured material layer B composed of a cured material of the thermosetting resin composition formed on the fibrous base layer at the encapsulating resin layer side. The thickness Ta of the cured material layer A is 0.5 μm or more. The ratio Ta/Tb of the thickness Ta of the cured material layer A and the thickness Tb of the cured material layer B is in a range of 0.1 to 10.



REMOVAL OF SURFACE PASSIVATION

Thu, 06 Apr 2017 08:00:00 EDT

Methods for removing a passivation film from a copper surface can include exposing the passivation film to a vapor phase organic reactant, for example at a temperature of 100° C. to 400° C. In some embodiments, the passivation film may have been formed by exposure of the copper surface to benzotriazole, such as can occur during a chemical mechanical planarization process. The methods can be performed as part of a process for integrated circuit fabrication. A second material can be selectively deposited on the cleaned copper surface relative to another surface of the substrate.



METHODS FOR ATOMIC LEVEL RESOLUTION AND PLASMA PROCESSING CONTROL

Thu, 06 Apr 2017 08:00:00 EDT

Methods and apparatus for processing substrates are provided. In some embodiments, methods of processing substrates includes: (a) providing a process gas comprising a polymer-forming gas and an etching gas between a first electrode and a second electrode within the processing volume, wherein the first electrode is opposite the second electrode; (b) applying a first voltage waveform from a first RF power source to the second electrode to form a plasma from the process gas, wherein the plasma has a first ion energy to deposit a polymer layer directly atop a dielectric layer of the substrate; and (c) adjusting the first voltage waveform to a second voltage waveform to increase an ion energy of the plasma from the first ion energy to a second ion energy, wherein the plasma at the second ion energy ceases to deposit the polymer layer and proceeds to etch the polymer layer and the dielectric layer.



ARTICLE AND PROCESS FOR SELECTIVE ETCHING

Thu, 06 Apr 2017 08:00:00 EDT

A process for etching includes disposing an activating catalyst on a substrate; providing a vapor composition that includes an etchant oxidizer, an activatable etchant, or a combination thereof; contacting the activating catalyst with the etchant oxidizer; contacting the substrate with the activatable etchant; performing an oxidation-reduction reaction between the substrate, the activatable etchant, and the etchant oxidizer in a presence of the activating catalyst and the vapor composition; forming an etchant product that includes a plurality of atoms from the substrate; and removing the etchant product from the substrate to etch the substrate.



METHOD OF MODIFYING EPITAXIAL GROWTH SHAPE ON SOURCE DRAIN AREA OF TRANSISTOR

Thu, 06 Apr 2017 08:00:00 EDT

Methods for forming semiconductor devices, such as FinFETs, are provided. An epitaxial film is formed over a semiconductor fin, and the epitaxial film includes a top surface having two facets. A cap layer is deposited on the top surface, and portions of the epitaxial film in a lateral direction are removed. Having a smaller lateral dimension prevents the epitaxial film from merging with an adjacent epitaxial film and creates a gap between the epitaxial film and the adjacent epitaxial film.



DEPOSITION OF SMOOTH METAL NITRIDE FILMS

Thu, 06 Apr 2017 08:00:00 EDT

In one aspect, methods of forming smooth ternary metal nitride films, such as TixWyNz films, are provided. In some embodiments, the films are formed by an ALD process comprising multiple super-cycles, each super-cycle comprising two deposition sub-cycles. In one sub-cycle a metal nitride, such as TiN is deposited, for example from TiCl4 and NH3, and in the other sub-cycle an elemental metal, such as W, is deposited, for example from WF6 and Si2H6. The ratio of the numbers of each sub-cycle carried out within each super-cycle can be selected to achieve a film of the desired composition and having desired properties.



METHODS OF FORMING METAL SILICIDES

Thu, 06 Apr 2017 08:00:00 EDT

A method of forming a metal silicide can include depositing an interface layer on exposed silicon regions of a substrate, where the interface layer includes a silicide forming metal and a non-silicide forming element. The method can include depositing a metal oxide layer over the interface layer, where the metal oxide layer includes a second silicide forming metal. The substrate can be subsequently heated to form the metal silicide beneath the interface layer, using silicon from the exposed silicon regions, the first silicide forming metal of the interface layer and the second silicide forming metal of the metal oxide layer.



AMOPHIZATION INDUCED METAL-SILICON CONTACT FORMATION

Thu, 06 Apr 2017 08:00:00 EDT

A method of forming a metal-silicon contact is provided. Embodiments include forming a metal layer over a substrate; forming an amorphous silicon (a-Si) capping layer over the metal layer; implanting ions to induce an athermal migration of the a-Si capping layer into the metal layer; and annealing the metal layer and the a-Si capping layer to form a metal silicide layer over the substrate.



METHOD AND APPARATUS FOR HEAT-TREATING HIGH DIELECTRIC CONSTANT FILM

Thu, 06 Apr 2017 08:00:00 EDT

A substrate in which a high-dielectric-constant gate insulator is formed on a silicon substrate with an interface layer film sandwiched in between is housed in a chamber. The method of the invention including: (a) housing the substrate in a chamber; (b) supplying ammonia to the chamber to foam an ammonia atmosphere; and (c) applying flash light to a surface of the substrate housed in the chamber to heat the high dielectric constant film, wherein the flash light applied in said step (c) has a spectral distribution that has a peak in a wavelength range of 200 to 300 nm.



Material Growth with Temperature Controlled Layer

Thu, 06 Apr 2017 08:00:00 EDT

A metal-organic chemical vapor deposition (MOCVD) growth with temperature controlled layer is described. A substrate or susceptor can have a temperature controlled layer formed thereon to adjust the temperature uniformity of a MOCVD growth process used to epitaxially grow semiconductor layers. In one embodiment, the substrate and/or the susceptor can be profiled with a shape that improves temperature uniformity during the MOCVD growth process. The profiled shape can be formed with material that provides a desired temperature distribution to the substrate that is in accordance with a predetermined temperature profile for the substrate for a particular MOCVD process.



METHOD FOR PROCESSING TARGET OBJECT

Thu, 06 Apr 2017 08:00:00 EDT

A method for processing a target object includes a formation step of forming a silicon oxide film in a processing chamber by repeatedly executing a sequence including a first step of supplying a first gas containing aminosilane-based gas, a second step of purging a space in the processing chamber after the first step, a third step of generating a plasma of a second gas containing oxygen gas after the second step, and a fourth step of purging the space after the third step. The method further includes a preparation step executed before the target object is accommodated in the processing chamber and a processing step of performing an etching process on the target object. The preparation step is performed before the processing step. The formation step is performed in the preparation step and the processing step. In the first step, a plasma of the first gas is not generated.



HYBRID PEROVSKITE FILMS

Thu, 06 Apr 2017 08:00:00 EDT

Methods for humidity-driven crystallization of hybrid perovskite films as well as the resulting hybrid perovskite films are provided. Hybrid perovskite films can be made by sequentially depositing respective layers of inorganic and organic hybrid perovskite precursors onto a substrate to form a hybrid perovskite film precursor. The hybrid perovskite film precursor can then be exposed to a humidified atmosphere so as to convert the inorganic and organic hybrid perovskite precursors to the hybrid perovskite. The processing desirably results in a void-free hybrid perovskite film. Humidity exposure processing methods can be the enabling step in the formation of large grain size (above 1 micrometer) for building vertical bulk-heterojunction structures through the infiltration of different media in vertical grain-boundaries.



RESIST UNDERLAYER FILM-FORMING COMPOSITION CONTAINING NOVOLAC RESIN TO WHICH AROMATIC VINYL COMPOUND IS ADDED

Thu, 06 Apr 2017 08:00:00 EDT

A resist underlayer film-forming composition has high solubility in a solvent used at a lithography process for exhibiting good coating film forming properties and able to decrease a sublime generated during formation of a film. A resist underlayer film-forming composition having a novolac resin having a structure group (C) obtained by a reaction of an aromatic ring structure of an aromatic ring-containing compound (A) with a vinyl group of an aromatic vinyl compound (B). The aromatic vinyl compound (B) is represented by Formula (1), and is specifically styrene, 2-vinylnaphthalene, 4-tert-butylstyrene, or 4-tert-butoxystyrene. The structure group (C) is represented by Formula (2). The aromatic ring-containing compound (A) is an aromatic amine compound or a phenolic hydroxy group-containing compound. The novolac resin is a resin produced by a reaction of the aromatic amine compound or the phenolic hydroxy group-containing compound with aldehyde or ketone.



MANUFACTURE METHOD OF BLACK MATRIX

Thu, 06 Apr 2017 08:00:00 EDT

The present invention provides a manufacture method of a black matrix. The COA technology is utilized to manufacture the organic photoresist blocks with a larger thickness on the alignment marks. Then, the black matrix thin film covers on the organic photoresist blocks to tremendously increase the level differences of the positions of the alignment marks and adjacent areas. Thus, the contour recognition apparatus is employed to accurately recognize positions of the alignment marks. The issue that the alignment marks are difficult to be recognized after the black matrix thin film is coated in the BOA process can be solved.



THIN FILM TRANSISTOR SUBSTRATE, DISPLAY DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE

Thu, 06 Apr 2017 08:00:00 EDT

A thin film transistor substrate, a display device including the same, and a method of manufacturing a thin film transistor substrate. The thin film transistor substrate includes: a base plate including a first area and a second area; a nano uneven pattern formed on one side of the base plate in the first area; a wire grid pattern formed on the ne side of the base plate in the second area; a gate electrode disposed on and overlapping the wire grid pattern; and one of a source electrode and a drain electrode disposed on the gate electrode and overlapping the wire grid pattern.



SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE

Thu, 06 Apr 2017 08:00:00 EDT

A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes a processed semiconductor substrate. The processed semiconductor substrate includes active electronic components. The semiconductor structure also includes a dielectric layer that covers, at least partially, the processed semiconductor substrate. An interface layer that is suitable for growing optically active material on the interface layer is bonded to the dielectric layer. An optical gain layer and the processed semiconductor substrate are connected through the dielectric layer by electric and/or optical contacts.



DYNAMIC CURRENT DISTRIBUTION CONTROL APPARATUS AND METHOD FOR WAFER ELECTROPLATING

Thu, 06 Apr 2017 08:00:00 EDT

Methods, systems, and apparatus for plating a metal onto a work piece are described. In one aspect, an apparatus includes a plating chamber, a substrate holder, an anode chamber housing an anode, an ionically resistive ionically permeable element positioned between a substrate and the anode chamber during electroplating, an auxiliary cathode located between the anode and the ionically resistive ionically permeable element, and an insulating shield with an opening in its central region. The insulating shield may be movable with respect to the ionically resistive ionically permeable element to vary a distance between the shield and the ionically resistive ionically permeable element during electroplating.



DYNAMIC PRECURSOR DOSING FOR ATOMIC LAYER DEPOSITION

Thu, 06 Apr 2017 08:00:00 EDT

Methods and apparatuses for controlling precursor flow in a semiconductor processing tool are disclosed. A method may include flowing gas through a gas line, opening an ampoule valve(s), before a dose step, to start a flow of precursor from the ampoule to a process chamber through the gas line, closing the ampoule valve(s) to stop the precursor from flowing out of the ampoule, opening a process chamber valve, at the beginning of the dose step, to allow the flow of precursor to enter the process chamber, and closing the process chamber valve, at the end of the dose step, to stop the flow of precursor from entering the process chamber. A controller may include at least one memory and at least one processor and the at least one memory may store instructions for controlling the at least one processor to control precursor flow in a semiconductor processing tool.



Rotating Disk Reactor With Ferrofluid Seal For Chemical Vapor Deposition

Thu, 06 Apr 2017 08:00:00 EDT

A rotating disk reactor for chemical vapor deposition includes a vacuum chamber and a ferrofluid feedthrough comprising an upper and a lower ferrofluid seal that passes a motor shaft into the vacuum chamber. A motor is coupled to the motor shaft and is positioned in an atmospheric region between the upper and the lower ferrofluid seal. A turntable is positioned in the vacuum chamber and is coupled to the motor shall so that the motor rotates the turntable at a desired rotation rate. A dielectric support is coupled to the turntable so that the turntable rotates the dielectric support when driven by the shaft. A substrate carrier is positioned on the dielectric support in the vacuum chamber for chemical vapor deposition processing. A heater is positioned proximate to the substrate carrier that controls the temperature of the substrate carrier to a desired temperature for chemical vapor deposition.



POLISHING COMPOSITION, POLISHING METHOD, AND METHOD FOR PRODUCING POLISHING COMPOSITION

Thu, 06 Apr 2017 08:00:00 EDT

A polishing composition includes crystalline metal oxide particles as abrasive grains, wherein the full width at half maximum of a peak portion having the maximum diffracted intensity in an X-ray powder diffraction pattern of the metal oxide particles is less than 1°. Thus, a polishing composition and a polishing method have high polishing speed and suppress defect generation such as a scratch and dishing, which causes to degrade reliability of a semiconductor apparatus in a polishing process of a semiconductor substrate, particularly in a chemical mechanical polishing process of a semiconductor substrate with a metal layer having tungsten, etc.; and a method produces the polishing composition.