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ORGANIC LIGHT EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

Thu, 23 Feb 2017 08:00:00 EST

Disclosed is an organic light emitting display apparatus in which an anode electrode, an organic emission layer, a cathode electrode, and an auxiliary electrode connected to the cathode electrode and disposed on the same layer as that of the anode electrode are disposed in an active area of the substrate, a signal pad and a pad electrode connected to the signal pad and covering a top of the signal pad are disposed in a pad area of the substrate, and a top of the pad electrode has lower oxidation rate than the top of the signal pad.



METHOD OF MANUFACTURING AN IMAGE SENSOR DEVICE

Thu, 23 Feb 2017 08:00:00 EST

A method of manufacturing an image sensor device includes providing a metalized thin film transistor layer on a glass substrate; forming an inter-layer dielectric layer on the metalized thin film transistor layer: forming a via through the inter-layer dielectric layer; forming a metal layer the inter-layer dielectric and within the inter-layer dielectric layer via for contacting the metalized thin film transistor layer; forming a bank layer on the metal layer and the inter-layer dielectric layer: forming a via through the bank layer; forming an electron transport layer on the bank layer and within the bank layer via for contacting an upper surface of the metal layer; forming a bulk heterojunction layer on the electron transport layer; forming a hole transport layer on the bulk heterojunction layer; and forming a top contact layer on the hole transport layer.



Techniques For Edge Management Of Printed Layers In A Flat Panel Display

Thu, 23 Feb 2017 08:00:00 EST

An ink jet process is used to deposit a material layer to a desired thickness. Layout data is converted to per-cell grayscale values, each representing ink volume to be locally delivered. The grayscale values are used to generate a halftone pattern to deliver variable ink volume (and thickness) to the substrate. The halftoning provides for a relatively continuous layer (e.g., without unintended gaps or holes) while providing for variable volume and, thus, contributes to variable ink/material buildup to achieve desired thickness. The ink is jetted as liquid or aerosol that suspends material used to form the material layer, for example, an organic material used to form an encapsulation layer for a flat panel device. The deposited layer is then cured or otherwise finished to complete the process.



SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Thu, 23 Feb 2017 08:00:00 EST

Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a selection element, a lower electrode pattern provided on the selection element to include a horizontal portion and a vertical portion; and a phase-changeable pattern on the lower electrode pattern. The vertical portion may extend from the horizontal portion toward the phase-changeable pattern and have a top surface, whose area is smaller than that of a bottom surface of the phase-changeable pattern.



EMBEDDED MASK PATTERNING PROCESS FOR FABRICATING MAGNETIC MEDIA AND OTHER STRUCTURES

Thu, 23 Feb 2017 08:00:00 EST

In some examples, a method including depositing a functional layer over a substrate; depositing a granular layer over the functional layer, the granular layer including a first material defining a plurality of grains separated by a second material defining grain boundaries of the plurality of grains; removing the second material from the granular layer such that the plurality of grains of the granular layer define a hard mask layer on the functional layer; and removing, via reactive ion etching with a carrier gas, portions of the functional layer not masked by the hard mask layer, wherein the carrier gas comprises a gas with an atomic number less than an atomic number of argon.



Magnetoresistive Random Access Memory Device and Method of Manufacturing the Same

Thu, 23 Feb 2017 08:00:00 EST

In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening.



METHOD OF MANUFACTURING LIGHT EMITTING DEVICE

Thu, 23 Feb 2017 08:00:00 EST

A method of manufacturing a light emitting device includes: providing on a mounting substrate a soluble member which is soluble in a solvent and which has a lower surface, an upper surface opposite to the lower surface in a height direction, and an outer side surface provided between the lower surface and the upper surface, the lower surface contacting the mounting substrate; providing a light blocking member made of resin to cover the outer side surface of the soluble member so that an inner side wall of the light blocking member contacts the outer side surface of the soluble member; removing the soluble member using the solvent to provide a recess surrounded by the inner side wall of the light blocking member; and mounting a light emitting element in the recess.



ADDITIONAL TEMPERATURE TREATMENT STEP FOR THIN-FILM SOLAR CELLS

Thu, 23 Feb 2017 08:00:00 EST

The present invention refers to a method for producing CdTe thin-film solar cells, respectively a semi-finished CdTe thin-film solar cell, where in an additional temperature step is carried out after applying the CdTe layer on to a substrate. In particular, the temperature step is performed after activating the CdTe layer using a suitable activation agent and removing the residual activation agent from the CdTe layer. The temperature treatment is performed under vacuum or in a heating chamber filled with either air or inert gas, during which treatment the substrate is exposed to a temperature between 180° C. and 380° C. for a time between 5 minutes and 60 minutes. Due to the inventive additional temperature step, the number and extension of crystal defects in the CdTe layer is reduced and the electric efficiency of the solar cell is further improved.



METHOD FOR PRODUCING DIFFERENTLY DOPED SEMICONDUCTORS

Thu, 23 Feb 2017 08:00:00 EST

The present invention relates to a liquid-phase method for doping a semiconductor substrate, characterized in that a first composition containing at least one first dopant is applied to one or more regions of the surface of the semiconductor substrate, in order to create one or more region(s) of the surface of the semiconductor substrate coated with the first composition; a second composition containing at least one second dopant is applied to one or more regions of the surface of the semiconductor substrate, in order to create one or more region(s) of the surface of the semiconductor substrate coated with the second composition, where the one or more region(s) coated with the first composition and the one or more region(s) coated with the second composition are different and do not overlap significantly and where the first dopant is an n-type dopant and the second dopant is a p-type dopant or vice versa; the regions of the surface of the semiconductor substrate coated with the first composition and with the second composition are each fully or partly activated; optionally, the unactivated regions of the surface of the semiconductor substrate coated with the first composition and with the second composition are each oxidized; and the semiconductor substrate is heated to a temperature at which the dopants diffuse out of the coating into the semiconductor substrate. The invention further relates to the semiconductor obtainable by the method and to the use thereof, especially in the production of solar cells.



Method For Producing a Solar Cell, in Particular a Silicon Thin-Film Solar Cell

Thu, 23 Feb 2017 08:00:00 EST

A method for producing a solar cell, in particular a silicon thin-film solar cell, wherein a TCO layer (3) is applied to a glass substrate (1) and at least one silicon layer (4, 5) is applied to the TCO layer (3). Before the TCO layer (3) is applied, electron radiation is applied to the glass substrate (1), such that a light-scattering layer (2) of the glass substrate (1) is produced, to which light-scattering layer the TCO layer (3) is applied. Alternatively or additionally, a first silicon layer (4) may be applied to the TCO layer (3), a laser radiation or electron radiation may be applied to the first silicon layer (4), and a second silicon layer (5) may be applied to the irradiated first silicon layer (4).



METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Thu, 23 Feb 2017 08:00:00 EST

An object of an embodiment of the present invention is to provide a semiconductor device including a normally-off oxide semiconductor element whose characteristic variation is small in the long term. A cation containing one or more elements selected from oxygen and halogen is added to an oxide semiconductor layer, thereby suppressing elimination of oxygen, reducing hydrogen, or suppressing movement of hydrogen. Accordingly, carriers in the oxide semiconductor can be reduced and the number of the carriers can be kept constant in the long term. As a result, the semiconductor device including the normally-off oxide semiconductor element whose characteristic variation is small in the long term can be provided.



MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Thu, 23 Feb 2017 08:00:00 EST

A method for manufacturing a semiconductor device has a first step including a step of forming an oxide semiconductor film, a second step including a step of forming a gate insulating film over the oxide semiconductor film and a step of forming a gate electrode over the gate insulating film, a third step including a step of forming a nitride insulating film over the oxide semiconductor film and the gate electrode, a fourth step including a step of forming an oxide insulating film over the nitride insulating film, a fifth step including a step of forming an opening in the nitride insulating film and the oxide insulating film, and a sixth step including a step of forming source and drain electrodes over the oxide insulating film so as to cover the opening. In the third step, the nitride insulating film is formed through at least two steps: plasma treatment and deposition treatment. The two steps are each performed at a temperature higher than or equal to 150° C. and lower than 300° C.



LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Thu, 23 Feb 2017 08:00:00 EST

A lateral double diffused metal oxide semiconductor device, includes: a P-type substrate, an epitaxial layer, a P-type high voltage well, a P-type body region, an N-type well, an isolation oxide region, a drift oxide region, a gate, an N-type contact region, a P-type contact region, a top source, a bottom source, and an N-type drain. The P-type body region is between and connects the P-type high voltage well and the surface of the epitaxial layer. The P-type body region includes a peak concentration region, which is beneath and indirect contact the surface of the epitaxial layer, wherein the peak concentration region has a highest P-type impurity concentration in the P-type body region. The P-type impurity concentration of the P-type body region is higher than a predetermined threshold to suppress a parasitic bipolar transistor such that it does not turn ON.



FINFET PCM ACCESS TRANSISTOR HAVING GATE-WRAPPED SOURCE AND DRAIN REGIONS

Thu, 23 Feb 2017 08:00:00 EST

Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET) device. The method includes forming at least one source region having multiple sides, forming at least one drain region having multiple sides, forming at least one channel region having multiple sides, forming at least one gate region around the multiple sides of the at least one channel region and forming the at least one gate region around the multiple sides of the at least one drain region.



FORMING A GATE CONTACT IN THE ACTIVE AREA

Thu, 23 Feb 2017 08:00:00 EST

A method of making a semiconductor device includes patterning a fin in a substrate; forming a gate between source/drain regions over the substrate, the gate having a dielectric spacer along a sidewall; removing a portion of the dielectric spacer and filling with a metal oxide to form a spacer having a first spacer portion and a second spacer portion; forming a source/drain contact over at least one of the source/drain regions; recessing the source/drain contact and forming a via contact over the source/drain contact; and forming a gate contact over the gate, the gate contact having a first gate contact portion contacting the gate and a second gate contact portion positioned over the first gate contact portion; wherein the first spacer portion isolates the first gate contact portion from the source/drain contact, and the second spacer portion isolates the second gate contact portion from the source/drain contact.



STRAINED FINFET DEVICE FABRICATION

Thu, 23 Feb 2017 08:00:00 EST

A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.



METHOD FOR MANUFACTURING A FINFET DEVICE

Thu, 23 Feb 2017 08:00:00 EST

A method for manufacturing a FinFET device, including providing a substrate; implementing a source/drain doping on the substrate; etching the doped substrate to form a source region and a drain region; forming a fin channel between the source region and the drain region; and forming a gate on the Fin channel. The fin and the gate are formed after the source/drain doping is implemented on the substrate, so that the source/drain doping is done as a doping for a planar device, which ensures the quality of the source/drain coping and improves the property of the FinFET device.



SEMICONDUCTOR DEVICE WITH ENHANCED 3D RESURF

Thu, 23 Feb 2017 08:00:00 EST

A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and spaced from one another along a first lateral dimension, and a drift region in the semiconductor substrate and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions. The drift region has a notched dopant profile in a second lateral dimension along an interface between the drift region and the drain region.



METHODS OF FORMING SEMICONDUCTOR DEVICES

Thu, 23 Feb 2017 08:00:00 EST

Methods of forming semiconductor devices are provided. A method of forming a semiconductor device includes forming first and second dielectric layers in first and second trenches. The method includes forming first and second conductive layers on the first and second dielectric layers, respectively. The method includes forming first and second protective layers on the first and second conductive layers, respectively. The method includes performing an annealing process while the first and second protective layers are on the first and second conductive layers. The method includes removing the first and second protective layers. The method includes removing the first conductive layer, after performing the annealing process. Moreover, the method includes forming first and second gate metals in the first and second trenches, respectively, after removing the first conductive layer.



MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE

Thu, 23 Feb 2017 08:00:00 EST

Provided is a method for manufacturing a semiconductor device that improves the reliability of the semiconductor device. An opening is formed in an insulating film formed over a semiconductor substrate. At that time, a mask layer for formation of the opening is formed over the insulating film. The insulating film is dry etched and then wet etched. The dry etching step is finished before the semiconductor substrate is exposed at the bottom of the opening, and the wet etching step is finished after the semiconductor substrate is exposed at the bottom of the opening.



VERTICAL TRANSFER GATE STRUCTURE FOR A BACK-SIDE ILLUMINATION (BSI) COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) IMAGE SENSOR USING GLOBAL SHUTTER CAPTURE

Thu, 23 Feb 2017 08:00:00 EST

A method for manufacturing a back-side illumination (BSI) complementary metal-oxide-semiconductor (CMOS) image sensor with a vertical transfer gate structure for improved quantum efficiency (QE) and global shutter efficiency (GSE) is provided. A sacrificial dielectric layer is formed over a semiconductor region. A first etch is performed into the sacrificial dielectric layer to form an opening exposing a photodetector in the semiconductor region. A semiconductor column is formed in the opening. A floating diffusion region (FDR) is formed over the semiconductor column and the sacrificial dielectric layer. A second etch is performed into the sacrificial dielectric layer to remove the sacrificial dielectric layer, and to form a lateral recess between the FDR and the photodetector. A gate is formed filling the lateral recess and laterally spaced from the semiconductor column by a gate dielectric layer. The BSI CMOS image sensor resulting from the method is also provided.



PREPARATION METHODS FOR THIN-FILM LAYER PATTERN, THIN-FILM TRANSISTOR AND ARRAY SUBSTRATE

Thu, 23 Feb 2017 08:00:00 EST

Preparation methods for a thin-film layer pattern, thin-film transistor and array substrate. The preparation method for a thin-film layer pattern includes: providing a mask plate, the mask plate including a mask plate body and a hollowed portion arranged on same; placing the mask plate onto a substrate, and allowing a projection of the hollowed portion on the substrate to be overlapped with a projection of a thin-film layer pattern to be formed on the substrate; forming a thin film on the substrate on which the mask plate (10) is placed, wherein a first thin-film portion formed at the hollowed portion is disconnected from a second thin-film portion formed on the mask plate body; and stripping the mask plate, and reserving the first thin-film portion to form the thin-film layer pattern.



STRAIN RELEASE IN PFET REGIONS

Thu, 23 Feb 2017 08:00:00 EST

A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric layer disposed on a substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer, forming a plurality of fins on the SSOI structure, forming a gate structure over a portion of at least one fin in a nFET region, forming a gate structure over a portion of at least one fin in a pFET region, removing the gate structure over the portion of the at least one fin in the pFET region, removing the silicon germanium layer exposed by the removing, and forming a new gate structure over the portion of the at least one fin in the pFET region, such that the new gate structure surrounds the portion on all four sides.



THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME

Thu, 23 Feb 2017 08:00:00 EST

A thin film transistor array panel is provided as follows. A gate electrode is disposed on a substrate. A semiconductor layer is disposed on the gate electrode. A gate insulating layer is disposed between the gate electrode and the semiconductor layer. A source electrode is disposed on a first side of the semiconductor layer, having a first lateral surface. A drain electrode is disposed on a second side of the semiconductor layer, having a second lateral surface. The first and second lateral surfaces define a spacing which overlaps the gate electrode. A metal suicide layer is disposed on the first and second lateral surfaces. A passivation layer is disposed on the metal silicide layer, the source electrode and the drain electrode. The passivation layer is not in contact with the first and second lateral surfaces.



U-SHAPED VERTICAL THIN-CHANNEL MEMORY

Thu, 23 Feb 2017 08:00:00 EST

A memory device, which can be configured as a 3D NAND flash memory, includes a plurality of stacks of conductive strips, including even stacks and odd stacks having sidewalls. Some of the conductive strips in the stacks are configured as word lines. Data storage structures are disposed on the sidewalls of the even and odd stacks. Active pillars between corresponding even and odd stacks of conductive strips include even and odd semiconductor films connected at the bottom of the trench between the stacks, and have outside surfaces and inside surfaces. The outside surfaces contact the data storage structures on the sidewalls of the corresponding even and odd stacks forming a 3D array of memory cells; the inside surfaces are separated by an insulating structure that can include a gap. The semiconductor films can be thin-films having a U-shaped current path.



METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Thu, 23 Feb 2017 08:00:00 EST

A performance of a semiconductor device is improved. A film, which is made of silicon, is formed in a resistance element formation region on a semiconductor substrate, and an impurity, which is at least one type of elements selected from a group including a group 14 element and a group 18 element, is ion-implanted into the film, and a film portion which is formed of the film of a portion into which the impurity is ion-implanted is formed. Next, an insulating film with a charge storage portion therein is formed in a memory formation region on the semiconductor substrate, and a conductive film is formed on the insulating film.



METHOD OF FABRICATING SEMICONDUCTOR DEVICE

Thu, 23 Feb 2017 08:00:00 EST

A method of fabricating a semiconductor device includes forming first cell patterns on a substrate, forming a first layer relative to the first cell patterns, and forming a second cell pattern and a peripheral pattern on the first layer. The second cell pattern includes first holes in a cell region and the peripheral pattern is located in a peripheral region. The method also includes filling the first holes, removing the second cell pattern to expose pillars, and forming second holes. Each of the second holes corresponds to adjacent cell spacers of the pillars. The method also includes removing the pillars to form third holes corresponding to respective ones of the cell spacers, and etching the substrate using the cell spacers, the first cell patterns, and the peripheral pattern as etch masks to form a trench.



OPTIMIZING POWER DISTRIBUTION FROM A POWER SOURCE THROUGH A C4 SOLDER BALL GRID INTERCONNECTED THROUGH SILICON VIAS IN INTERMEDIATE INTEGRATED CIRCUIT CHIP CONNECTED TO CIRCUITRY IN AN UPPER INTERGRATED CIRCUIT CHIP THROUGH A GRID OF MICRO uC4 SOLDER BALLS

Thu, 23 Feb 2017 08:00:00 EST

In an integrated chip stack arrangement, wherein power is provided to an upper integrated chip, including a processor core with a grid arrangement of cells connected to a power supply in a substrate by a conventional C4 solder ball array on the substrate connected through TSVs in an intermediate integrated circuit chip, it has been recognized that for maximum current efficiency and minimum electro migration the vias should not be directly coincident with the micro C4 solder balls connecting the upper chip with the intermediate chip.



METHOD FOR MANUFACTURING STRETCHABLE WIRE AND METHOD FOR MANUFACTURING STRETCHABLE INTEGRATED CIRCUIT

Thu, 23 Feb 2017 08:00:00 EST

Provided is a method for manufacturing a stretchable wire, the method including removing a portion of a photoresist layer on a substrate to form a photoresist pattern comprising at least one pattern slit, applying a liquid-phase conductive material on the photoresist pattern to form a liquid-phase conductive structure in the pattern slit, forming a stretchable first insulating layer on the liquid-phase conductive structure, after removing the photoresist pattern, and separating the liquid-phase conductive structure and the first insulating layer from the substrate.



DEVICE AND METHOD FOR PERMANENT BONDING

Thu, 23 Feb 2017 08:00:00 EST

A method and corresponding device for permanent bonding of a first layer of a first substrate to a second layer of a second substrate on a bond interface, characterized in that a dislocation density of a dislocation of the first and/or second layer is increased at least in the region of the bond interface before and/or during the boding.



ELECTROSTATIC DISCHARGE PROTECTION APPARATUS AND PROCESS

Thu, 23 Feb 2017 08:00:00 EST

In a process, at least one circuit element is formed in a substrate. A conductive layer is formed over the substrate and in electrical contact with the at least one circuit element. Electrostatic charges are discharged from the substrate via the conductive layer.



Protrusion Bump Pads for Bond-on-Trace Processing

Thu, 23 Feb 2017 08:00:00 EST

An embodiment apparatus includes a dielectric layer in a die, a conductive trace in the dielectric layer, and a protrusion bump pad on the conductive trace. The protrusion bump pad at least partially extends over the dielectric layer, and the protrusion bump pad includes a lengthwise axis and a widthwise axis. A ratio of a first dimension of the lengthwise axis to a second dimension of the widthwise axis is about 0.8 to about 1.2



THREE DIMENSIONAL INTEGRATED CIRCUIT STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Thu, 23 Feb 2017 08:00:00 EST

Provided is a three dimensional integrated circuit structure including a first die, a through substrate via and a connector. The first die is bonded to a second die with a first dielectric layer of the first die and a second dielectric layer of the second die, wherein a first passivation layer is between the first dielectric layer and a first substrate of the first die, and a first test pad is embedded in the first passivation layer. The through substrate via penetrates through the first die and is electrically connected to the second die. The connector is electrically connected to the first die and the second die through the through substrate via.



HYBRID CORRECTIVE PROCESSING SYSTEM AND METHOD

Thu, 23 Feb 2017 08:00:00 EST

A system and method for performing corrective processing of a workpiece is described. The system and method includes receiving a first set of parametric data from a first source that diagnostically relates to at least a first portion of a microelectronic workpiece, and receiving a second set of parametric data from a second source different than the first source that diagnostically relates to at least a second portion of the microelectronic workpiece. Thereafter, a corrective process is generated, and a target region of the microelectronic workpiece is processed by applying the corrective process to the target region using a combination of the first set of parametric data and the second set of parametric data.



Method And Apparatus For Analysis Of Processing Of A Semiconductor Wafer

Thu, 23 Feb 2017 08:00:00 EST

An apparatus and a method for analysis of processing of a semiconductor wafer is disclosed which comprises gathering a plurality of items of processing data, applying at least one process model to the at least some of the plurality of items of processing data to derive at least one set of process results, comparing at least some of the derived sets of process results or at least some of the plurality of items of processing data with a process window, and outputting a set of comparison results based on the comparison of the derived sets of process results or the plurality of items of processing data with the process window.



Single-Wafer Real-Time Etch Rate and Uniformity Predictor For Plasma Etch Processes

Thu, 23 Feb 2017 08:00:00 EST

The present disclosure relates to semiconductor manufacturing, in particular to a real-time method for qualifying the etch rate for plasma etch processes. A method for testing a semiconductor plasma etch chamber may include: depositing a film on a substrate of a wafer, the wafer including a center region and an edge region; depositing photoresist on top of the film in a pattern that isolates the center region from the edge region of the wafer; and performing an etch process on the wafer that includes at least three process steps. The three process steps may include: etching the film in any areas without photoresist covering the areas until a first clear endpoint signal is achieved; performing an in-situ ash to remove any photoresist; and etching the film in any areas exposed by the removal of the photoresist until a second clear endpoint is achieved. The method may further include determining whether both endpoints are achieved within respective previously set tolerances, and, if both endpoints are achieved within the previously set tolerance, qualifying the plasma etch chamber as verified.



FINFET DEVICES HAVING GATE DIELECTRIC STRUCTURES WITH DIFFERENT THICKNESSES ON SAME SEMICONDUCTOR STRUCTURE

Thu, 23 Feb 2017 08:00:00 EST

FinFET devices are formed on the same semiconductor structure wherein at least one finFET device has a gate dielectric structure that is different in thickness relative to a gate dielectric structure of at least one other finFET device. The finFET devices are formed as part of the same fabrication process.



SEMICONDUCTOR STRUCTURES HAVING INCREASED CHANNEL STRAIN USING FIN RELEASE IN GATE REGIONS

Thu, 23 Feb 2017 08:00:00 EST

A method of introducing strain in a channel region of a FinFET device includes forming a fin structure on a substrate, the fin structure having a lower portion comprising a sacrificial layer and an upper portion comprising a strained semiconductor layer; and removing a portion of the sacrificial layer corresponding to a channel region of the FinFET device so as to release the upper portion of the fin structure from the substrate in the channel region.



STRAINED FINFET DEVICE FABRICATION

Thu, 23 Feb 2017 08:00:00 EST

A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.



FORMING CMOSFET STRUCTURES WITH DIFFERENT CONTACT LINERS

Thu, 23 Feb 2017 08:00:00 EST

A method of making a semiconductor device includes forming a first trench contact over a first source/drain region of a first transistor; forming a second trench contact over a second source/drain region of a second transistor; depositing a first liner material within the first trench contact; and depositing a second liner material within the second trench contact; wherein the first liner material and the second liner material include different materials.



METHODS FOR FORMING FIN STRUCTURES

Thu, 23 Feb 2017 08:00:00 EST

A method includes providing a substrate having a first and a second plurality of fins with a first at least one dielectric material disposed thereon, removing upper portions of the first dielectric material to expose upper portions of the first and the second plurality of fins, removing the first dielectric material from the lower portions of the second plurality of fins to expose lower portions of the second plurality of fins, depositing a second at least one dielectric material on at least the upper and the lower exposed portions of the second plurality of fins and on the upper exposed portions of first plurality of fins, removing the second dielectric material to expose upper portions of the first and the second plurality of fins, and wherein the first dielectric material is different from the second dielectric material. The resulting structure may be operable for use as nFETs and pFETs.



METHODS FOR PRODUCING SEMICONDUCTOR DEVICES

Thu, 23 Feb 2017 08:00:00 EST

A method for producing a semiconductor device in accordance with various embodiments may include providing a semiconductor workpiece attached to a first carrier; dicing the semiconductor workpiece and the carrier so as to form at least one individual semiconductor chip; mounting the at least one semiconductor chip with a side facing away from the carrier, to an additional carrier.



WAFER STRUCTURE AND PROCESSING METHOD THEREOF

Thu, 23 Feb 2017 08:00:00 EST

A wafer structure and a processing method of a wafer structure are disclosed here. The wafer structure, which is used for forming a plurality of dies, comprising: a semiconductor substrate having a first surface and a second surface opposite to the first one; at least one first functional layer and at least one second functional layer at the first surface of the semiconductor substrate, wherein the at least one second functional layer is located in a scribe lane of the wafer; and a plurality of scribing marks in the scribe lane, for singulating adjacent ones of the plurality of dies during a laser cutting process, wherein the plurality of dies each include the at least one first functional layer and a portion of the semiconductor substrate. The wafer structure can provide a functional layer in the scribe lane, while it facilitates to singulate the adjacent ones of the plurality of dies.



WAFER PROCESSING METHOD

Thu, 23 Feb 2017 08:00:00 EST

A wafer formed from an SiC substrate having a first surface and a second surface is divided into individual device chips. A division start point formed by a cutting blade has a depth corresponding to the finished thickness of each device chip along division lines formed on the first surface. A separation start point is formed by a laser beam having a focal point set inside the SiC substrate at a predetermined depth from the second surface, and the laser beam is applied to the second surface while relatively moving the focal point and the SiC substrate to thereby form a modified layer parallel to the first surface and cracks extending from the modified layer along a c-plane. An external force is applied to the wafer, thereby separating the wafer into a first wafer having the first surface and a second wafer having the second surface.



WAFER PROCESSING METHOD

Thu, 23 Feb 2017 08:00:00 EST

A wafer processing method of processing a wafer with a plurality of devices disposed in areas demarcated by projected division lines and formed on a face side thereof includes a protective member placing step of placing a protective member for protecting the face side of the wafer on the face side of the wafer which is divided into individual device chips, a resin laying step of laying a die-bonding resin on the reverse sides of the individual device chips by applying a die-bonding liquid resin on the reverse side of the wafer and hardening the applied die-bonding liquid resin, and a separation step of separating the device chips with the die-bonding liquid resin laid on the reverse sides thereof from the wafer.



WAFER PROCESSING METHOD

Thu, 23 Feb 2017 08:00:00 EST

A wafer formed from an SiC substrate having a first surface and a second surface is divided into individual device chips. A division start point formed by a laser has a depth corresponding to the finished thickness of each device chip along each division line formed on the first surface. The focal point of the laser beam is set inside the SiC substrate at a predetermined depth from the second surface, and the laser beam is applied to the second surface while relatively moving the focal point and the SiC substrate to thereby form a modified layer parallel to the first surface and cracks extending from the modified layer along a c-plane, thus forming a separation start point. An external force is applied to the wafer, thereby separating the wafer into a first wafer having the first surface and a second wafer having the second surface.



METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE

Thu, 23 Feb 2017 08:00:00 EST

A method for fabricating a semiconductor device is disclosed. The method includes forming a first interlayer insulating layer including a first trench that is defined by a first gate spacer and a second trench that is defined by a second gate spacer on a substrate, forming a first gate electrode that fills a part of the first trench and a second gate electrode that fills a part of the second trench, forming a first capping pattern that fills the remainder of the first trench on the first gate electrode, forming a second capping pattern that fills the remainder of the second trench on the second gate electrode, forming a second interlayer insulating layer that covers the first gate spacer and the second gate spacer on the first interlayer insulating layer, forming a third interlayer insulating layer on the second interlayer insulating layer and forming a contact hole that penetrates the third interlayer insulating layer and the second interlayer insulating layer between the first gate electrode and the second gate electrode.



SEMICONDUCTOR SUBSTRATE POLISHING METHODS AND SLURRIES AND METHODS FOR MANUFACTURING SILICON ON INSULATOR STRUCTURES

Thu, 23 Feb 2017 08:00:00 EST

Polishing slurries for polishing semiconductor substrates are disclosed. The polishing slurry may include first and second sets of colloidal silica particles with the second set having a silica content greater than the first set.



SEMICONDUCTOR DEVICES HAVING FIN FIELD EFFECT TRANSISTORS WITH A SINGLE LINER PATTERN IN A FIRST REGION AND A DUAL LINER PATTERN IN A SECOND REGION AND METHODS FOR MANUFACTURING THE SAME

Thu, 23 Feb 2017 08:00:00 EST

A method for manufacturing a semiconductor device includes forming a first active pattern in a first region of a substrate and a second active pattern in a second region of the substrate, wherein the first and second active patterns project from the substrate, forming a second liner pattern on the substrate and the second active pattern in the second region, wherein the second liner pattern has a second polarity, forming a first liner pattern on the substrate and the first active pattern in the first region, wherein the first liner pattern has a first polarity different from the second polarity, forming an isolation pattern on the first liner pattern in the first region and the second liner pattern in the second region, and exposing the first active pattern and the second active pattern by recessing the isolation pattern.



WAFER PROCESSING BONDING ARRANGEMENT, WAFER LAMINATE, AND THIN WAFER MANUFACTURING METHOD

Thu, 23 Feb 2017 08:00:00 EST

A bonding arrangement comprising a silicone-base adhesive composition is suited for temporarily bonding a wafer to a support for wafer processing. The bonding arrangement includes a first temporary bond layer of non-silicone thermoplastic resin, and a second temporary bond layer of thermosetting silicone polymer and/or a third temporary bond layer of thermosetting siloxane-modified polymer. The second and/or third bond layer contains an antistatic agent.