Thu, 27 Oct 2016 08:00:00 EDTA system and method for providing laser diodes emitting multiple wavelengths is described. Multiple wavelengths and/or colors of laser output are obtained by having multiple laser devices, each emitting a different wavelength, packaged onto the same substrate. In other embodiments, multiple laser devices having different wavelengths are formed from the same substrate.
Thu, 27 Oct 2016 08:00:00 EDTA method of cutting a substrate includes: forming a first protective layer on a first surface of the substrate; forming a removal area where a portion of the first protective layer is removed by irradiating the first protective layer at the portion of the first protective layer with a first laser beam; and forming a cutting area by removing a portion of the substrate by irradiating the substrate with a second laser beam at the removal area, after irradiating the first protective layer with the first laser beam.
Thu, 27 Oct 2016 08:00:00 EDTA mask frame assembly including a frame and a mask having a first surface that contacts the frame. The mask includes an active area and pattern holes formed in the active area, the pattern holes being configured to allow a deposition material to pass through the mask. The mask also includes a rib portion disposed outside the active area and configured to block the deposition material from passing through the mask and a non-magnetic reinforcing member disposed on a part of the rib portion.
Thu, 27 Oct 2016 08:00:00 EDTThe present invention provides a method for manufacturing a flexible display device, which includes the following steps: (1) providing a flexible substrate and a number of clamps; (2) securing edges of the flexible substrate with the number of clamps; and (3) subjecting the flexible substrate to operations of exposure, development, etching, thin film deposition, annealing, and film formation, wherein in each of the operations, the clamps are adjusted in order to adjust flatness and amount of contraction of the flexible substrate and also, the clamps are adjusted to adjust angle of the flexible substrate. The present invention uses the clamps to securely clamp edges of the flexible substrate so that adjustment of the clamps may be conducted in case that deformation and deflection of the flexible substrate occurs in order to reduce the deformation and deflection of the flexible substrate and achieve precise control of accuracy of the manufacturing process thereby preventing the deformation and deflection from affecting the accuracy of the manufacturing process. In different operations, the flexible substrate can be adjusted to be horizontal, inclined, or vertical and the clamps may apply different amounts of forces to control the accuracy and reduce deformation of the substrate. No operations of laminating and peeling are necessary.
Thu, 27 Oct 2016 08:00:00 EDTProvided are an organic transistor having high carrier mobility that contains a compound represented by the following formula in a semiconductor active layer (each of X1 to X4 represents NR100, an O atom, or a S atom; NR100 represents a hydrogen atom, an alkyl group, an alkenyl group, an alkynyl group, an acyl group, an aryl group, or a heteroaryl group; each of R1 to R6 represents a hydrogen atom or a substituent; at least one of R1, R2, R3, R4, R5, or R6 is a substituent represented by -L-R; L is a divalent linking group having a specific structure; and R is an alkyl group having 5 to 19 carbon atoms); a compound; an organic semiconductor material for a non-light-emitting organic semiconductor device; a material for an organic transistor; a coating solution for a non-light-emitting organic semiconductor device; an organic semiconductor film for a non-light-emitting organic semiconductor device; and a method for manufacturing an organic semiconductor film for a non-light-emitting organic semiconductor device.
Thu, 27 Oct 2016 08:00:00 EDTA method is disclosed for producing an organic component including a substrate and at least one layer produced by a sintering process. An organic component produced by such method is also disclosed.
Thu, 27 Oct 2016 08:00:00 EDTA method of manufacturing an organic light-emitting device including a plurality of pixels using an organic solution spray apparatus, where each of the pixels comprises a plurality of sub-pixels having different colors, includes: preparing a substrate on which a plurality of sub-pixel regions is defined; generating a potential difference between a nozzle of the organic solution spray apparatus and the sub-pixel regions; spraying an organic solution from the nozzle of the organic solution spray apparatus to the sub-pixel regions; and forming an organic material layer by selectively depositing the organic solution to the sub-pixel regions using the potential difference between the nozzle and the sub-pixel regions.
Thu, 27 Oct 2016 08:00:00 EDTMethods of fabricating a device having laterally patterned first and second sub-devices, such as subpixels of an OLED, are provided. Exemplary methods may include depositing via organic vapor jet printing (OVJP) a first organic layer of the first sub-device and a first organic layer of the second sub-device. The first organic layer of the first sub-device and the first organic layer of the second sub-device are both the same type of layer, but have different thicknesses. The type of layer is selected from an ETL, an HTL, an HIL, a space and a capping layer.
Thu, 27 Oct 2016 08:00:00 EDTThere is provided an electroactive system for forming an electroactive layer. The system includes: (a) a first electroactive material; (b) a facilitation additive; and (c) a first liquid medium. The facilitation additive is present during baking in an amount sufficient to enable the electroactive layer made therefrom to effectively resist mixing with a second liquid medium applied thereover after the electroactive system is deposited and baked at a temperature less than 350° C. for a predetermined time.
Thu, 27 Oct 2016 08:00:00 EDTIn forming a top electrode for a magnetoresistive device, photoresist used in patterning the electrode is stripped using a non-reactive stripping process. Such a non-reactive stripping process uses water vapor or some other non-oxidizing gas that also passivates exposed portions the magnetoresistive device. In such magnetoresistive devices, a non-reactive spacer layer is included that helps prevent diffusion between layers in the magnetoresistive device, where the non-reactive nature of the spacer layer prevents sidewall roughness that can interfere with accurate formation of the lower portions of the magnetoresistive device.
Thu, 27 Oct 2016 08:00:00 EDTThis disclosure provides systems, methods, and apparatus related to thermoelectric materials. In one aspect, a thermoelectric material is provided. The thermoelectric material is then irradiated with charged particles to generated native defects in the thermoelectric material. The charged particles have energies of 100 keV or greater. The irradiation of the thermoelectric material may improve its thermoelectric properties.
Thu, 27 Oct 2016 08:00:00 EDTProvided is a CIGSSe thin film for a solar cell, a method for preparing the same, and a solar cell using the same. More particularly, the CIGSSe thin film for a solar cell shows a decrease in peak intensity of sulfur from the surface of the thin film to the local minimum value point of sulfur content in the depth direction, after the analysis based on the Auger electron spectroscopy, and thus controls the band-gap in the thin film. Therefore, the solar cell including the CIGSSe thin film shows an excellent effect in improving photoelectric conversion efficiency.
Thu, 27 Oct 2016 08:00:00 EDTMethods and systems for forming a layer from a fluid mixture on a web are provided. The system includes a fluid delivery apparatus for delivering the fluid mixture onto the web. The fluid delivery apparatus includes a cascade device and a chemical dispenser device. The system also includes a fluid stirring apparatus comprising at least one fan positioned over the web and configured to generate a flow pattern that stirs the fluid mixture on the web while the layer is being formed, without the at least one fan contacting the fluid mixture. The system further includes a fluid removal apparatus having a rinsing device and a suction device. The rinsing device is configured to dispense a rinsing fluid onto the web. The suction device is configured to remove by suction the rinsing fluid and a remaining portion of the fluid mixture remaining on the web after formation of the layer.
Thu, 27 Oct 2016 08:00:00 EDTA method for preparing a mesoscopic solar cell based on perovskite light absorption materials, the method including 1) preparing a hole blocking layer on a conductive substrate; 2) preparing and sintering a mesoporous nanocrystalline layer, an insulation separating layer, and a hole collecting layer on the hole blocking layer in order; and 3) drop-coating a precursor solution on the hole collecting layer, and allowing the precursor solution to penetrate pores of the mesoporous nanocrystalline layer via the hole collecting layer from top to bottom, and drying a resulting product to obtain a mesoscopic solar cell.
Thu, 27 Oct 2016 08:00:00 EDTDisclosed is a thin film solar cell including a substrate, a first electrode, a light absorbing layer, a buffer layer, a window layer, and a second electrode, wherein a compound layer of MxSy or MxSey (here, M is metal, and x and y each are a natural number) is present in an interface between the first electrode and the light absorbing layer, the thickness of the compound layer of MxSy or MxSey being 150 nm or less.
Thu, 27 Oct 2016 08:00:00 EDTThe present invention relates to a conductive paste and a method for producing solar cell by using the same. The conductive paste comprises at least silver powders and a composite glass frit comprising a first type of glass frit containing lead oxides and silicon oxides and a second type of glass frit containing tellurium oxides and zinc oxides wherein the first type of glass frit and the second type of glass frit are in a weight ratio of 93:7 to 44:56.
Thu, 27 Oct 2016 08:00:00 EDTA method of texturizing a silicon substrate comprising a) contacting the substrate with an etching solution comprising glycolic acid, b) etching a surface of the substrate thereby forming disruptions in said surface of the substrate, and c) removing the etching solution to yield a texturized substrate, said texturized substrate having a plurality of disruptions in at least one surface with a surface density of disruptions of a minimum of 60 disruptions in a 400 micron square area.
Thu, 27 Oct 2016 08:00:00 EDTDisclosed is a method of manufacturing an a-IGZO TFT-based transient semiconductor. The method includes (a) stacking a thermal oxide layer on a silicon substrate and depositing a nickel thin layer; (b) forming a PECVD layer on the nickel thin layer; (c) patterning the PECVD layer after setting a gate area and depositing a metallic layer; (d) lifting off the metallic layer to form a gage metallic thin layer and depositing a gage insulating layer on the gate metallic thin layer; (e) depositing an a-IGZO layer on the gate insulating layer; (f) etching an active area and the gate insulating layer; (g) forming a source electrode and a drain electrode and attaching a thermal release tape on the source electrode and the drain electrode; (h) delaminating the nickel thin layer; (i) performing transcription on a polyvinyl alcohol thin layer after etching the nickel thin layer; and (j) detaching the tape.
Thu, 27 Oct 2016 08:00:00 EDTA method for fabricating a semiconductor device includes: forming a metal pattern including nickel on a semiconductor layer, the metal pattern having upper and side surfaces; forming a mask pattern having an opening in which upper and side surfaces of the metal pattern therein being exposed; forming a barrier layer on the metal pattern exposed in the opening by a plating method; and forming a conducting layer on the barrier layer exposed in the opening.
Thu, 27 Oct 2016 08:00:00 EDTA highly reliable semiconductor device the yield of which can be prevented from decreasing due to electrostatic discharge damage is provided. A semiconductor device is provided which includes a gate electrode layer, a first gate insulating layer over the gate electrode layer, a second gate insulating layer being over the first gate insulating layer and having a smaller thickness than the first gate insulating layer, an oxide semiconductor layer over the second gate insulating layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The first gate insulating layer contains nitrogen and has a spin density of 1×1017 spins/cm3 or less corresponding to a signal that appears at a g-factor of 2.003 in electron spin resonance spectroscopy. The second gate insulating layer contains nitrogen and has a lower hydrogen concentration than the first gate insulating layer.
Thu, 27 Oct 2016 08:00:00 EDTA method of forming an asymmetrical three dimensional semiconductor device. The method may include providing a fin structure extending perpendicularly from a substrate plane and having a fin axis parallel to the substrate plane, wherein a portion of the fin structure is covered by a gate structure defining a channel region, and wherein the fin structure comprises a first end surface not covered by the gate structure and second end surface not covered by the gate structure. The method may further include directing ions in a fin treatment to the fin structure, wherein the fin treatment comprises a first treatment of the first end surface and a second treatment of the second end surface different from the first treatment.
Thu, 27 Oct 2016 08:00:00 EDTA method for forming a three dimensional device. The method may include directing ions to an end surface of an extension region of a fin structure, the fin structure extending perpendicularly from a substrate plane and having a fin axis parallel to the substrate plane, wherein the ions have trajectories extending in a plane perpendicular to the substrate plane and parallel to the fin axis, wherein a portion of the fin structure is covered by a gate structure defining a channel region, and wherein the end surface is not covered by the gate structure.
Thu, 27 Oct 2016 08:00:00 EDTAn e-Fuse structure is provided on a surface of an insulator layer of a semiconductor-on-insulator substrate (SOI). The e-Fuse structure includes a first metal semiconductor alloy structure of a first thickness, a second metal semiconductor alloy structure of the first thickness, and a metal semiconductor alloy fuse link is located laterally between and connected to the first and second metal semiconductor alloy structures. The metal semiconductor alloy fuse link has a second thickness that is less than the first thickness.
Thu, 27 Oct 2016 08:00:00 EDTA method of manufacturing a display panel having a plurality of lightly doped drain thin film transistors arranged as a matrix includes forming a semiconductor pattern with a predetermined shape on a substrate; forming a dielectric layer covering the semiconductor pattern on the substrate; forming a metal layer on the dielectric layer; forming a photoresist patterns smaller than the semiconductor pattern on the metal layer above the semiconductor pattern; etching the metal layer to form a gate electrode smaller than the photoresist pattern; doping high concentration ions by using the photoresist pattern as a mask to form a pair of highly doped regions on the semiconductor pattern not covered by the photoresist pattern; removing the photoresist pattern; and doping low concentration ions by using the gate electrode as a mask to form a pair of lightly doped regions between the highly doped regions and a part of the semiconductor pattern.
Thu, 27 Oct 2016 08:00:00 EDTWhen p-type impurities are implanted into a SiC substrate using a laser, controlling the concentration is difficult. A p-type impurity region is formed by a laser in a region where the control of the concentration in the SiC substrate is not necessary almost at all. A SiC semiconductor device having withstanding high voltage is manufactured at a lower temperature process compared to ion implantation process. A method of manufacturing a silicon carbide semiconductor device includes forming, on one main surface of a first conductivity-type silicon carbide substrate, a first conductivity-type drift layer having a lower concentration than that of the silicon carbide substrate; forming, on a front surface side of the drift layer, a second conductivity-type electric field control region by a laser doping technology; forming a Schottky electrode in contact with the drift layer; and forming, on the other main surface of the silicon carbide substrate, a cathode electrode.
Thu, 27 Oct 2016 08:00:00 EDTA stratified gate dielectric stack includes a first high dielectric constant (high-k) gate dielectric comprising a first high-k dielectric material, a band-gap-disrupting dielectric comprising a dielectric material having a different band gap than the first high-k dielectric material, and a second high-k gate dielectric comprising a second high-k dielectric material. The band-gap-disrupting dielectric includes at least one contiguous atomic layer of the dielectric material. Thus, the stratified gate dielectric stack includes a first atomic interface between the first high-k gate dielectric and the band-gap-disrupting dielectric, and a second atomic interface between the second high-k gate dielectric and the band-gap-disrupting dielectric that is spaced from the first atomic interface by at least one continuous atomic layer of the dielectric material of the band-gap-disrupting dielectric. The insertion of the band-gap disrupting dielectric results in lower gate leakage without resulting in any substantial changes in the threshold voltage characteristics and effective oxide thickness.
Thu, 27 Oct 2016 08:00:00 EDTA SOI substrate is covered by a semiconductor material pattern which includes a dividing pattern made from electrically insulating material. The dividing pattern is coated by one or more semiconductor materials. The semiconductor material pattern is covered by a gate electrode which is facing the dividing pattern. The semiconductor material pattern and the gate pattern are covered by a cap layer. The substrate is eliminated to access the source/drain regions. Two delineation patterns are formed to cover the source region and drain region and to leave the dividing pattern free. A second cap layer is deposited and access vias are formed to access the source/drain regions by elimination of the delineation patterns.
Thu, 27 Oct 2016 08:00:00 EDTA method for manufacturing a vertical super junction drift layer of a power semiconductor device. The method includes: a): adopting P+ single crystal silicon to prepare a P+ substrate; b): finishing top processes of the devices on the P+ substrate, forming at least P type region, manufacturing active area and metallizing the top surface of the P+ substrate; c): thinning the back surface of the P+ single crystal silicon; d): selectively implanting H+ ions at the back surface repeatedly and then annealing to form N pillars in the P type region; and e): metallizing the back surface.
Thu, 27 Oct 2016 08:00:00 EDTTo form a dielectric layer, an organometallic precursor is adsorbed on a substrate loaded into a process chamber. The organometallic precursor includes a central metal and ligands bound to the central metal. An inactive oxidant is provided onto the substrate. The inactive oxidant is reactive with the organometallic precursor. An active oxidant is also provided onto the substrate. The active oxidant has a higher reactivity than that of the inactive oxidant.
Thu, 27 Oct 2016 08:00:00 EDTA circuit board in which damage to an electrode is reduced or a light-emitting device in which damage to an electrode is reduced is manufactured. A method for manufacturing the circuit board or the light-emitting device includes the following steps: preparing a processing member including a circuit and a terminal electrode over a first substrate, a separation layer over the terminal electrode, a bonding layer over the separation layer, and a second substrate over the bonding layer; forming a groove in the processing member using a blade capable of cutting processing by being rotated; and removing part of the separation layer, part of the bonding layer, and part of the second substrate to expose part of the terminal electrode.
Thu, 27 Oct 2016 08:00:00 EDTA method of manufacturing a photoelectric conversion device includes forming a wiring structure above a semiconductor substrate including a photoelectric converter, forming, by a plasma CVD method, a first insulating film which contains hydrogen, above an uppermost wiring layer in the wiring structure, performing, after formation of the first insulating film, first annealing in a hydrogen containing atmosphere on a structure including the semiconductor substrate, the wiring structure, and the first insulating film, forming a second insulating film above the first insulating film after the first annealing, and performing, after formation of the second insulating film, second annealing in the hydrogen containing atmosphere on a structure including the semiconductor substrate, the wiring structure, the first insulating film, and the second insulating film.
Thu, 27 Oct 2016 08:00:00 EDTTo provide a semiconductor device having mix-loaded therein a nonvolatile memory cell and a field effect transistor at a reduced cost. A method of manufacturing a semiconductor device includes pattering a conductor film by using an additional mask that covers a gate electrode formation region of a memory formation region and exposes a main circuit formation region (field effect transistor formation region) and thereby forming a gate electrode of a nonvolatile memory cell in the memory formation region and then forming an n−type semiconductor region of the nonvolatile memory cell in a semiconductor substrate by ion implantation using the above-mentioned additional mask without changing it to another one.
Thu, 27 Oct 2016 08:00:00 EDTA method of making a memory device comprising a base; a capacitor comprising a ferroelectric layer and at least two electrically conductive layers, the ferroelectric layer being located between the at least two electrically conductive layers; each of the at least two conductive layers being operatively connected to a current source; a cantilever attached to the base at first end and movable at a second end, the ferroelectric capacitor being mounted to the cantilever such that the second end of the cantilever moves a predetermined displacement upon application of a current to the ferroelectric layer which induces deformation of the ferroelectric layer thereby causing displacement of the cantilever which is operatively associated with a contact so that an electrical connection is enabled with the contact upon the predetermined displacement of the cantilever. The presence or absence of a connection forms two states of a memory cell.
Thu, 27 Oct 2016 08:00:00 EDTA semiconductor device having a plurality of fins including at least one first fin and at least one second fin formed on a semiconductor substrate is provided. Each of the first fin and second fin has a first portion and a second portion. A gate electrode structure overlies the first portion of the plurality of fins. The gate electrode structure includes a gate electrode, and a gate dielectric layer between the gate electrode and the plurality of fins, A first electrode overlies the second portion of the plurality of fins and the first electrode is in electrical contact with the second portion of the plurality of fins. The gate electrode structure is in direct physical contact with the first portion of the first fin and the gate electrode structure is spaced apart from the first portion of the second fin.
Thu, 27 Oct 2016 08:00:00 EDTElectrostatic discharge (ESD) devices and methods of manufacture are provided. The method includes forming a plurality of fin structures and a mesa structure from semiconductor material. The method further includes forming an epitaxial material with doped regions on the mesa structure and forming gate material over at least the plurality of fin structures. The method further includes planarizing at least the gate material such that the gate material and the epitaxial material are of a same height. The method further includes forming contacts in electrical connection with respective ones of the doped regions of the epitaxial material.
Thu, 27 Oct 2016 08:00:00 EDTA link device with a large density routing is attached to a package in order to provide a high-density interconnect pathway to interconnect semiconductor devices. In an embodiment the package is an integrated fan out package. The link device may be bonded on either side of the package, and the package may optionally comprise through package vias. The link device may also be an integrated passive device that includes resistors, inductor, and capacitor components.
Thu, 27 Oct 2016 08:00:00 EDTA method of manufacturing a semiconductor structure includes providing a first wafer including a surface, removing some portions of the first wafer over the surface to form a plurality of recesses extended over at least a portion of the surface of the first wafer, providing a second wafer, and disposing the second wafer over the surface of the first wafer.
Thu, 27 Oct 2016 08:00:00 EDTA connective structure for bonding semiconductor devices and methods for forming the same are provided. The bonding structure includes an alpad structure, i.e., a thick aluminum-containing connective pad, and a substructure beneath the aluminum-containing pad that includes at least a pre-metal layer and a barrier layer. The pre-metal layer is a dense material layer and includes a density greater than the barrier layer and is a low surface roughness film. The high density pre-metal layer prevents plasma damage from producing charges in underlying dielectric materials or destroying subjacent semiconductor devices.
Thu, 27 Oct 2016 08:00:00 EDTA semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.
Thu, 27 Oct 2016 08:00:00 EDTThe present disclosure provides a manufacturing method of a semiconductor packaging, including forming a redistribution layer (RDL) on a carrier, defining an active portion and a dummy portion of the RDL, and placing a semiconductor die over the dummy portion of the RDL. The present disclosure also provides a manufacturing method of a package-on-package (PoP) semiconductor structure, including forming a first redistribution layer (RDL) on a polymer-based layer of a carrier, defining an active portion and a dummy portion of the first RDL, placing a semiconductor die over the dummy portion of the first RDL, a back side of the semiconductor die facing the first RDL, forming a second RDL over a front side of the semiconductor die, the front side having at least one contact pad, and attaching a semiconductor package at the back side of the semiconductor die.
Thu, 27 Oct 2016 08:00:00 EDTA film-forming resin composition for use in encapsulating large-diameter thin-film wafers includes (A) a silicone resin having a weight-average molecular weight of 3,000 to 500,000 and containing repeating units of formula (1) wherein R1 to R4 are monovalent hydrocarbon groups, but R3 and R4 are not both methyl, m and n are integers of 0 to 300, R5 to R8 are divalent hydrocarbon groups, a and b are positive numbers such that a+b=1, and X is a specific divalent organic moiety; (B) a phenolic compound of formula (7) wherein Y is a carbon atom or a tetravalent hydrocarbon group of 2 to 20 carbon atoms, and R13 to R16 are monovalent hydrocarbon groups or hydrogen atoms; and (C) a filler.
Thu, 27 Oct 2016 08:00:00 EDTMethods for plasma etching are disclosed. In one embodiment, a method of etching a plurality of features on a wafer includes positioning a wafer on a feature plate within a chamber of a plasma etcher, providing a plasma source gas within the chamber, providing an anode above the feature plate and a cathode below the feature plate, connecting a portion of the cathode to the feature plate, generating plasma ions using a radio frequency power source and the plasma source gas, directing the plasma ions toward the wafer using an electric field, and providing an electrode shield around the cathode. The electrode shield is configured to protect the cathode from ions directed toward the cathode including the portion of the cathode connected to the feature plate.
Thu, 27 Oct 2016 08:00:00 EDTA silicon single crystal wafer is provided. The silicon single crystal wafer includes an IDP which is divided into an NiG region and an NIDP region, wherein the IDP region is a region where a Cu based defect is not detected, the NiG region is a region where an Ni based defect is detected and the NIPD region is a region where an Ni based defect is not detected.
Thu, 27 Oct 2016 08:00:00 EDTA composition for removing photoresist, including an alkyl ammonium fluoride salt in an amount ranging from about 0.5 weight percent to about 10 weight percent, based on a total weight of the composition; an organic sulfonic acid in an amount ranging from about 1 weight percent to about 20 weight percent, based on the total weight of the composition; and a lactone-based solvent in an amount ranging from about 70 weight percent to about 98.5 weight percent, based on the total weight of the composition.
Thu, 27 Oct 2016 08:00:00 EDTProvided are a semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a first active fin and a second active fin which protrude from a substrate and extend along a first direction, a first gate structure which is on the first active fin to extend along a second direction intersecting the first direction, a second gate structure which is located adjacent to the first gate structure in the second direction and is on the second active fin to extend along the second direction, and a dummy structure which is in a space between the first gate structure and the second gate structure.
Thu, 27 Oct 2016 08:00:00 EDTA method of forming a semiconductor device is provided including providing a semiconductor-on-insulator (SOI) wafer comprising a first semiconductor layer comprising a first material component and formed on a buried oxide (BOX) layer, and forming a channel region of a P-channel transistor device, including forming a second semiconductor layer only over a first portion of the first semiconductor layer, wherein the second semiconductor layer comprises the first material component and a second material component different from the first material component, forming an opening in the first semiconductor layer outside the first portion and subsequently performing a thermal anneal to push the second material component from the second semiconductor layer into the first semiconductor layer.
Thu, 27 Oct 2016 08:00:00 EDTObject is to provide a semiconductor device having improved reliability or performance. A high-breakdown-voltage n type transistor has source and drain regions having first, second, and third semiconductor regions, which are formed by ion implantation of a first impurity from the outside of a high-breakdown-voltage gate electrode, a second impurity from the outside of the high-breakdown-voltage gate electrode and a first sidewall insulating film, and a third impurity from the outside of the high-breakdown-voltage gate electrode and the first and second sidewall insulating films, respectively. The first and second impurities are implanted from a direction tilted by 45° relative to the main surface of the semiconductor substrate and the third impurity from a direction perpendicular thereto. The impurity concentration of the first semiconductor region is lower than that of the second one and the ion implantation energy of the first impurity is greater than that of the second impurity.
Thu, 27 Oct 2016 08:00:00 EDTVarious embodiments provide a method of detaching semiconductor material from a carrier, wherein the method comprises providing a carrier having attached thereto a layer of semiconductor material, wherein the layer comprises an edge portion; and guiding an air stream onto the edge portion of the layer of semiconductor material.
Thu, 27 Oct 2016 08:00:00 EDTDisclosed herein is a wafer processing method for dividing a wafer into a plurality of individual devices along a plurality of crossing division lines. The wafer is composed of a substrate and a functional layer formed on the front side of the substrate. The division lines are formed on the front side of the functional layer. A laser beam having a transmission wavelength to the substrate is applied to the wafer from the back side thereof to detect the height of an interface between the functional layer and the substrate in an area corresponding to each division line. The depth of cut by a cutting blade for cutting the substrate is next set according to the height detected above. The back side of the substrate is next cut by the cutting blade according to the depth of cut set above to thereby form a cut groove having a depth not reaching the functional layer with a remaining part of the substrate left between the bottom of the cut groove and the functional layer along each division line, the remaining part having a uniform thickness. Thereafter, the remaining part and the functional layer are cut along each division line to thereby divide the wafer.
Thu, 27 Oct 2016 08:00:00 EDTA method is described of radiatively cutting a wafer, the method comprising the steps of low power cutting of two trenches followed by high power cutting of a fissure. A single pulsed radiation beam is split into a first pulsed radiation beam for cutting at least one of the trenches and a second pulsed radiation beam for cutting the fissure. When cutting a fissure on the wafer in a cutting direction along a cutting street, the first and second radiation beams are directed simultaneously with the first radiation beam leading and the second radiation beam trailing. For cutting a fissure in the opposite cutting direction, a third pulsed radiation beam for trenching is split from said single pulsed radiation beam.