Thu, 25 Aug 2016 08:00:00 EDTEmbodiments describe techniques for utilizing fractional-N phase locked loops (PLL). Some embodiments describe a factional-divider based fractional-N PLL for a spread spectrum clock (SSC) generator that utilizes phase average techniques to suppress phase interpolator nonlinearity. Some embodiments describe a fractional-N PLL based on fractional dividers with hybrid finite impulse response (FIR) filtering. Some embodiments describe a small size and low power divider for a hybrid FIR fractional-N PLL.
Thu, 25 Aug 2016 08:00:00 EDTA level shifter circuit a first transistor connected between a power source terminal of the level shifter circuit and an output terminal of the level shifter circuit, the first transistor being configured to transmit, in response to a first signal and a second signal, a power source voltage applied from the power source terminal to the output terminal, the first signal being received from an input terminal of the level shifter circuit through a first gate of the first transistor, the second signal being received through a second gate of the first transistor, and a second transistor connected between a ground terminal of the level shifter circuit and the output terminal, the second transistor being configured to transmit a ground voltage from the ground terminal to the output terminal in response to a gate signal received through a gate of the second transistor.
Thu, 25 Aug 2016 08:00:00 EDTLevel shifters, memory systems, and level shifting methods are described. According to one arrangement, a level shifter includes an input configured to receive an input signal in a first voltage domain, an output configured to output an output signal from the level shifter in a second voltage domain different than the first voltage domain, a plurality of pull-down devices, and wherein one of the pull-down devices is coupled with the input and the output, a plurality of cross-coupled devices coupled with the pull-down devices and configured to provide transitions in the output signal as a result of transitions in the input signal, a plurality of current limiting devices coupled with the cross-coupled devices and configured to limit a flow of current from a source to the cross-coupled devices, and a plurality of dynamic devices configured to selectively provide charging current from the source to the cross-coupled devices.
Thu, 25 Aug 2016 08:00:00 EDTA feedthrough signal transmission apparatus, fabricated on a single silicon, includes a plurality of feedthrough signal transmission circuits and a permanently on control cell that is coupled to the feedthrough signal transmission circuits, where each feedthrough signal transmission circuit of the feedthrough signal transmission circuits may include at least one sub-circuit that is kept in a power on state when the sub-circuit performs feedthrough signal transmission. For example, and the sub-circuit may include a permanently on-for-feedthrough repeater (e.g. a repeater that is kept in the power on state when the repeater performs feedthrough signal transmission). In addition, the permanently on control cell may be configured to maintain the power on state of the sub-circuit when the sub-circuit performs feedthrough signal transmission. For example, sub-circuits of the feedthrough signal transmission circuits are located at grid-based locations, respectively.
Thu, 25 Aug 2016 08:00:00 EDTIn an embodiment, a switching circuit includes a high voltage depletion mode transistor having a first leakage current and operatively connected in a cascode arrangement to a low voltage enhancement mode transistor having a second leakage current. The second leakage current is larger than the first leakage current.
Thu, 25 Aug 2016 08:00:00 EDTThe present technology relates to a driving circuit and a driving method, in which power loss at the time of switching an FET (Field Effect Transistor) can be reduced with a simple circuit configuration. A coil constitutes a resonance circuit together with an input capacitance at a gate of the FET. A switch (regeneration switch) turns on or off current flowing in the coil. A DC power source is a power source to replenish the resonance circuit with electric charge and is connected to the gate of the FET. A switch (replenish switch) turns on or off connection between the DC power source and the gate of the FET. The present technology is applicable to, for example, a power source that outputs AC voltage and current by switching operation.
Thu, 25 Aug 2016 08:00:00 EDTThe present invention relates to an insulated gate bipolar transistor (IGBT) driver module for driving at least one gate of at least one IGBT device, and method therefor. The IGBT driver module comprises at least one series capacitance operably coupled between a driver component of the IGBT driver module and the at least one gate of the at least one IGBT device. The IGBT driver module further comprises at least one series capacitance charge adjustment component controllable to determine a gate voltage error (ΔGerr) at the at least one gate of the at least one IGBT device and dynamically adjust a charge of the at least one series capacitance based at least partly on the determined gate voltage error (ΔGerr).
Thu, 25 Aug 2016 08:00:00 EDTTo reduce power consumption, a semiconductor device includes a power source circuit for generating a power source potential, and a power supply control switch for controlling supply of the power source potential from the power source circuit to a back gate of a transistor, and the power supply control switch includes a control transistor for controlling conduction between the power source circuit and the back gate of the transistor by being turned on or off in accordance with a pulse signal that is input into a control terminal of the control transistor. The power source potential is intermittently supplied from the power source circuit to the back gate of the transistor, using the power supply control switch.
Thu, 25 Aug 2016 08:00:00 EDTA back-power prevention circuit is provided that protects a buffer transistor from back-power during a back-power condition by charging a signal lead coupled to a gate of the buffer transistor to a pad voltage and by charging a body of the buffer transistor to the pad voltage.
Thu, 25 Aug 2016 08:00:00 EDTA gate drive circuit comprising multistage gate drive on array (GOA) drive units is provided. Each stage of GOA drive unit comprises a pull-up control part, a pull-up part, a key pull-down part, and a pull-down holding part. The pull-down holding part comprises a bridging module, a first and a second pull-down holding modules. When the bridging module is in a shutoff state, the first and the second pull-down holding modules work alternately, whereby a potential at the gate signal output end and/or a potential at the control end of the pull-up part are/is kept at a potential of the direct current power source according to a pull-down holding control signal.
Thu, 25 Aug 2016 08:00:00 EDTA sensing circuit configured to activate a controller is disclosed. The circuit comprises a first transistor configured to output an activation signal to the controller and a plurality of switches in connection with a base of the transistor. Each of the switches is connected to an identifying resistor. A first output node and a second output node are in communication with the base of the transistor and each of the switches. The first output node and the second output node are separated across an additional identifying resistor. The first output node and the second output node are configured to output a characteristic voltage corresponding a ratio of each of the identifying resistors in response to an input received by one or more of the plurality of switches.
Thu, 25 Aug 2016 08:00:00 EDTA level-shift circuit, receiving a supply voltage and a input signal, includes a pre-stage voltage conversion circuit and a post-stage voltage conversion circuit. The pre-stage voltage conversion circuit includes a first voltage protection module generating an inner conversion voltage and a first voltage conversion module converting the input signal into a pre-stage output signal according to the inner conversion voltage. The post-stage voltage conversion circuit includes a second voltage protection module generating a first inverse output signal, a first output signal, a second inverse output signal, and a second output signal. The transistors of the pre-stage voltage conversion circuit and the post-stage voltage conversion circuit have a punch-through voltage. The level-shift makes the stress of the transistors less than the punch-through voltage when the supply voltage is greater than the punch-through voltage, and remains the driving capability when being less than the punch-through voltage.
Thu, 25 Aug 2016 08:00:00 EDTSystems and methods for powering up circuits are described herein. In one embodiment, a method for power up comprises comparing a voltage of a first supply rail with a voltage of a second supply rail, and determining whether the voltage of the first supply rail is within a predetermined amount of the voltage of the second supply rail for at least a predetermined period of time based on the comparison. The method also comprises initiating switching of a plurality of switches coupled between the first and second supply rails upon a determination that the voltage of the first supply rail is within the predetermined amount of the voltage of the second supply rail for at least the predetermined period of time.
Thu, 25 Aug 2016 08:00:00 EDTA drive device that drives a semiconductor switching device includes a capacitor and an output selection unit that selects whether or not to supply charge of the capacitor to a conduction control terminal of the semiconductor switching device, in which the output selection unit includes a first switching device and a second switching device, the charge of the capacitor is supplied to the conduction control terminal of the semiconductor switching device by the first switching device going to a conducting state, the charge is extracted from the conduction control terminal of the semiconductor switching device by the second switching device going to the conducting state, and a gate width of the second switching device is smaller than the gate width of the first switching device.
Thu, 25 Aug 2016 08:00:00 EDTA circuit includes a first power node, an output node, a driver transistor coupled between the first power node and the output node, and a contending circuit. The driver transistor is configured to be turned on responsive to an edge of a first type of an input signal and to be turned off responsive to an edge of a second type of the input signal. The driver transistor has a source, a drain, and a gate, and the source of the driver transistor is coupled with the first power node. The contending circuit includes a control circuit configured to generate a control signal based on a signal at a gate of the driver transistor; and a contending transistor between the drain of the driver transistor and a second voltage. The contending transistor has a gate configured to receive the control signal.
Thu, 25 Aug 2016 08:00:00 EDTA latch circuit includes a first input node, a second input node, a first output node, a second output node, a first switching device coupled between the first output node and the second output node, and a first amplification circuit coupled with the first input node, the second input node, the first output node, and the second output node. The first switching device is configured to be turned on in response to a first state of a clock signal and to be turned off in response to a second state of the clock signal. The first amplification circuit is configured to cause a voltage difference across the first switching device based on voltage levels of the first input node and the second input node in response to the first state of the clock signal.
Thu, 25 Aug 2016 08:00:00 EDTA circuit to a extend signal comparison voltage range includes a latching circuit and a comparator responsive to common-mode input signals. The comparator is coupled to the latching circuit and to a dynamic node. The circuit also includes a clocked boost circuit coupled to the dynamic node. The clocked boost circuit is configured to extend a supply voltage range of the comparator via biasing the dynamic node. A method to extend a signal comparison voltage range includes selectively shifting a voltage level of one of a ground reference of a dynamic circuit or a supply reference of the dynamic circuit in response to a clock signal.
Thu, 25 Aug 2016 08:00:00 EDTA semiconductor device according to an embodiment includes a differential circuit including a first current-path receiving a first voltage and a second current-path receiving a second voltage. A first mirror circuit can cause a current obtained by multiplying a current flowing through the first current-path by a first mirror ratio to flow through a third current-path. A second mirror circuit can cause a current obtained by multiplying a current flowing through the second current-path by a second mirror ratio to flow through a fourth current-path. A third mirror circuit can cause a current obtained by multiplying a current flowing through the third current-path by a third mirror ratio to flow through the fourth current-path. A first circuit changes any one of the first to third mirror ratios according to a logic level of data output from an output part that is connected to the fourth current-path.
Thu, 25 Aug 2016 08:00:00 EDTIn one form, a flip-flop comprises a master latch, a slave latch, and a multiplexer. The master latch has an input for receiving a data input signal, and an output, and operates in transparent and latching modes during respective first and second phases of a clock signal. The slave latch has an input coupled to the output of the master latch, and an output, and operates in the transparent and latching modes during the second and first phases of the clock signal, respectively. The multiplexer has a first input coupled to the output of the slave latch, a second input coupled to the output of the master latch, and an output for providing a data output signal, and provides the first input to the output during the first phase of the clock signal, and the second input to the output during the second phase of the clock signal.
Thu, 25 Aug 2016 08:00:00 EDTAccording to one embodiment, a level shift circuit includes first through fourth transistors, a control circuit, and first and second generating circuits. The control circuit outputs a first voltage obtained by level-shifting an input voltage to a first terminal. The first transistor supplies a first electric current to the control circuit for outputting the first voltage to the first terminal. The second transistor increases the first electric current. The first generating circuit generates a first pulse signal for controlling the second transistor. The third transistor supplies a second electric current to the first terminal for generating a second voltage corresponding to a first supply of a low-potential side. The fourth transistor increases the second electric current. The second generating circuit generates a second pulse signal for controlling the fourth transistor.
Thu, 25 Aug 2016 08:00:00 EDTA power transfer electrical system includes an electrical signal source that generates a current at an output. An electrical load is electrically connected to the output of the electrical signal source. An output of a controllable voltage source is also electrically connected to the electrical load. The controllable voltage source generates a voltage that is proportional to the current generated by the electrical signal source. An input of a controller is electrically connected to the output of the electrical signal source and an output of the controller is electrically connected to a control input of the controllable voltage source. The controller generates a signal that controls the voltage generated by the controllable voltage source so that a desirable amount of power is transferred from the electrical signal source to the controllable voltage source.
Thu, 25 Aug 2016 08:00:00 EDTA gate-drive-on-array circuit for use with oxide semiconductor thin-film transistors of the present invention uses two constant-voltage negative potential sources (VSS1, VSS2) that are reduced step by step and low potentials of a high-frequency clock signal (CK(n)) and a low-frequency clock signal (LC1, LC2) to ensure an up-pull circuit portion (200) is maintained in a well closed condition during a non-operating period without being affected by the high-frequency clock signal (CK(n)) so as to ensure the circuit operates normally. Further, the first down-pull circuit portion (400) is re-designed to prevent influence thereof imposed on the outputs of the first node (Q(N)) and the output terminal (G(N)) so as to ensure the first node (Q(N)) and the output terminal (G(N)) can supply the outputs normally without generating signal distortion.
Thu, 25 Aug 2016 08:00:00 EDTProvided herein are apparatus and methods for radio frequency (RF) switching. In certain configurations, an RF switching circuit includes two or more FETs electrically connected in series between an input terminal and an output terminal, with the two or more FETs in the series connected via one or more intermediate nodes. The RF switching circuit receives a first switch control signal that can be used to control the DC bias voltages of the gates of the two or more FETs, and a second switch control signal that can be used to control the DC bias voltages of the one or more intermediate nodes.
Thu, 25 Aug 2016 08:00:00 EDTAn injection locked frequency divider is disclosed. The injection-locked frequency divider includes a sub-harmonic injection-locked oscillator, a reference clock divider, a counter, and a variable load resistor control unit. The sub-harmonic injection-locked oscillator has variable load resistors that are adjusted in response to a resistance adjustment signal, and, when oscillation frequency determined based on the magnitudes of the variable load resistors is a sub-harmonic of an injection signal, outputs signals having the oscillation frequency as divided output signals. The reference clock divider generates a count-enable signal from a reference clock signal according to a reference division ratio. The counter generates divided output count signals based on the divided output signals in response to the count-enable signal. The variable load resistor control unit compares target count values, determined based on the target frequencies of the divided output signals, with the divided output count signals, and outputs the resistance adjustment signal.
Thu, 25 Aug 2016 08:00:00 EDTA power-supply control device that includes a transistor that is interposed between a power source and a load; a control circuit to which a voltage from the power source is applied, the voltage being applied across a high-voltage side input terminal and a low-voltage side input terminal of the control circuit, and that is configured to turn the transistor on or off based on an operating signal for the load that is applied from an external device, and controlling supply of power to the load; a voltage detector that is configured to detect a value of the voltage applied to the control circuit by the power source, and is configured to determine whether or not the applied voltage value detected is lower than a predetermined voltage value; and a negative voltage output circuit.
Thu, 25 Aug 2016 08:00:00 EDTAn integrated circuit comprises a transistor body control circuit for controlling a body of a bidirectional power transistor. The transistor body control circuit comprises switches connected between a body terminal and a first current terminal, with a control terminal for controlling the current flowing through the switch. The control terminal of the switch is connected to alternating current, AC capacitive voltage divider. The AC capacitive voltage dividers are connected to the control terminals and arranged to control the switches to switch the voltage of the body terminal as a function of the voltage between the first current terminal and the second current terminal. The integrated circuit further comprises a bi-directional power transistor connected to the transistor body control circuit.
Thu, 25 Aug 2016 08:00:00 EDTA gate drive circuit is disclosed. The gate drive circuit comprises multi-stage of GOA drive unit, and each stage of GOA drive unit comprises a signal afferent unit, used for outputting a pull-down control signal; an output unit, used for outputting a first gate signal and a second gate signal; a pull-up control unit, used for outputting a pull-up control signal; and a pull-up sustaining unit, used for pulling up an electric potential of the control end of the output unit to an electric potential of the direct-current power supply according to the pull-up control signal, so that the first gate signal and the second gate signal are maintained in a high-level state.
Thu, 25 Aug 2016 08:00:00 EDTA current control system is disclosed. The current control system may include a controller configured to provide a control signal, an A/D converter dedicated to the controller, a driver configured to supply a current based on the control signal and a sensor configured to provide a digital signal representative of the current to the controller. The digital signal may bypass the dedicated A/D converter. A method for controlling current is likewise disclosed. A circuit for controlling current through an inductive load is likewise disclosed.
Thu, 25 Aug 2016 08:00:00 EDTProvided is a liquid discharging apparatus which includes a modulation circuit which generates a modulation signal which is obtained by pulse-modulating a source signal, a transistor which generates an amplified modulation signal by amplifying the modulation signal, a low pass filter which includes an inductor and a capacitor and generates a drive signal by smoothening the amplified modulation signal, a piezoelectric element which is displaced by receiving the drive signal, a cavity of which the internal volume changes in accordance with the displacement of the piezoelectric element, a nozzle through which liquid in the cavity is discharged in accordance with change in the internal volume of the cavity, and a circuit substrate on which the modulation circuit, the transistor, and the low pass filter are mounted, in which the capacitor is a leadless type capacitor.
Thu, 18 Aug 2016 08:00:00 EDTA variable phase generator is disclosed that includes a delay line with an input, and output, and a delay lone control signal input. A signal on the delay line output has a phase offset relative to the delay line input signal such that the phase offset is controlled by a digital offset signal. A phase detector process the input signal and the output signal to generate a phase detector output signal. A charge pump, responsive to the phase detector output signal, generates a charge pump output. A digital to analog converter receives and converts the digital offset signal to an analog offset signal. A control node is connected to the delay line control input, the charge pump, and the digital to analog converter, and is configured to receive and combine the charge pump output and the analog offset signal to create the delay line control signal.
Thu, 18 Aug 2016 08:00:00 EDTA drive unit includes a reverse conducting transistor including a transistor and a first diode being connected in inverse-parallel to the transistor, the transistor and the first diode being provided on a common semiconductor substrate; a second diode including a cathode being connected to a collector of the transistor the second diode being provided on the semiconductor substrate; and a detection portion configured to detect a voltage between the collector and an emitter of the transistor via an anode of the second diode.
Thu, 18 Aug 2016 08:00:00 EDTAn apparatus, comprising a clock adapted to provide a clock signal alternating with a cycle between a first level and a second level if a timing violation is not detected; a first latch adapted to be clocked such that it passes a first signal when the clock signal is at the first level; a second combinational logic adapted to output a second signal based on the first signal passed through the first latch; a second latch adapted to be clocked such that it passes the second signal when the clock signal is at the second level; a detecting means adapted to detect the timing violation of at least one of the first signal and of the second signal; a time stretching means adapted to stretch, if the timing violation is detected, the clock such that the clock alternates between the first level and the second level with a delay.
Thu, 18 Aug 2016 08:00:00 EDTA liquid discharge apparatus includes: an modulation circuit that generates a modulated signal by pulse-modulating a source signal through self-oscillation; a transistor that amplifies the modulated signal to generate an amplified modulated signal; a low-pass filter that includes an inductor and a capacitor and smoothes the amplified modulated signal to generate a drive signal; a feedback circuit that allows the drive signal to return to the modulation circuit; a piezoelectric element that is displaced by application of the drive signal thereto; a cavity that is filled with a liquid inside and has an internal volume which changes when the piezoelectric element is displaced; and a nozzle that is provided to discharge the liquid inside the cavity in response to the change of the internal volume of the cavity. In this configuration, a self-resonant frequency of the capacitor is higher than a frequency of the self-oscillation.
Thu, 18 Aug 2016 08:00:00 EDTA capacitive load driving circuit for repeating between charging and discharging for a capacitive load includes a charge supply source, a first signal path through which a first voltage is applied by the charge supply source, a second signal path through which a second voltage higher than the first voltage is applied by the charge supply source, and a connection path selector configured to electrically connect the capacitive load and the charge supply source via at least one of the first signal path and the second signal path, in accordance with a control signal. The charge supply source is arranged and configured to supply voltage to the connection path selection section.
Thu, 18 Aug 2016 08:00:00 EDTA single-pole multi-throw switch includes a set of selection switches. The set of selection switches includes a set of primary switches, a first set and a second set of secondary switches. The primary set of switches includes a plurality of primary transistors coupled in series for transmitting radio frequency signals. The first set of secondary switches is coupled to the primary set of switches and includes a plurality of first secondary transistors coupled in series for transmitting the radio frequency signals when the primary transistors and the first secondary transistors are turned on. The second set of secondary switches is coupled to the primary set of switches and includes a plurality of second secondary transistors coupled in series for transmitting the radio frequency signals when the primary transistors and the second secondary transistors are turned on.
Thu, 18 Aug 2016 08:00:00 EDTA transmission circuit includes a driver circuit that includes: a first transistor to regulate output impedance, and a switching circuit that is connected to the first transistor and switches an output polarity for differential output; and a bias circuit that includes: a first replica circuit including a second transistor corresponding to the first transistor, the bias circuit generating a gate voltage so as to make a current-voltage characteristic of the first transistor correspond to a first output impedance value, and supply the gate voltage to a gate of the first transistor.
Thu, 18 Aug 2016 08:00:00 EDTThere is described a driver circuit for a single wire protocol slave unit, the driver circuit comprising (a) at least one current mirror comprising a first transistor (MP1, MN3) and a second transistor (MP2, MN4), wherein the gate of both transistors is connected to a bias node (PBIAS, S2BIAS), and wherein the second transistor is adapted to conduct a mirror current (I2, IOUT) equal to a current (I1, I2) conducted by the first transistor multiplied by a predetermined factor, (b) a bias transistor (MP3, MN5) for selectively connecting and disconnecting the bias node to and from a predetermined potential (VDD, GND) in response to a control signal (ABUF, AN), and (c) a current boosting element for providing a boost current (I1P, I2P) to the bias node for a predetermined period of time when the control signal causes the bias transistor to disconnect the bias node from the predetermined potential. There is also described a universal integrated circuit card device comprising a driver circuit.
Thu, 18 Aug 2016 08:00:00 EDTMethods, systems, circuits, and devices for power-packet-switching power converters using bidirectional bipolar transistors (B-TRANs) for switching. Four-terminal three-layer B-TRANs provide substantially identical operation in either direction with forward voltages of less than a diode drop. B-TRANs are fully symmetric merged double-base bidirectional bipolar opposite-faced devices which operate under conditions of high non-equilibrium carrier concentration, and which can have surprising synergies when used as bidirectional switches for power-packet-switching power converters. B-TRANs are driven into a state of high carrier concentration, making the on-state voltage drop very low.
Thu, 18 Aug 2016 08:00:00 EDTA bipolar transistor switches for radio frequency signals are disclosed. In an embodiment a device includes a first radio frequency (RF) terminal, a second RF terminal, and a bipolar transistor, wherein an emitter terminal of the bipolar transistor is coupled to the first RF terminal, and wherein a collector terminal of the bipolar transistor is coupled to the second RF terminal. The device further includes a base current supply circuit configured to selectively supply a base current to a base terminal of the bipolar transistor.
Thu, 18 Aug 2016 08:00:00 EDTA control circuit for turning on a power semiconductor switch comprises an input which is configured to receive a signal that characterizes the switch-on behavior of the power semiconductor switch, a variable current source which is configured to supply a current with a variable level to a control input of the power semiconductor switch in order to switch on the power semiconductor switch, wherein the control circuit is configured to control the variable current source in a closed control loop in response to the signal that characterizes the switch-on behavior of the power semiconductor switch.
Thu, 18 Aug 2016 08:00:00 EDTA leakage current-based delay circuit is provided, wherein the delay circuit may include a first transistor circuit and a second transistor circuit, each transistor circuit may include a p-type transistor, an n-type transistor, an n-node between a drain node of the p-type transistor and a gate node of the n-type transistor, and a p-node between a gate node of the p-type transistor and a drain node of the n-type transistor. The p-node of the second transistor circuit may be charged based on a power source voltage through the first transistor circuit during a first time interval of an input signal, and the n-node of the second transistor circuit may be discharged based on a ground voltage through the first transistor circuit during the first time interval.
Thu, 18 Aug 2016 08:00:00 EDTA voltage supply circuit for an electronic circuit includes a switch configured to selectively connect a supply input of the electronic circuit with a main supply voltage source. An auxiliary voltage supply unit has an auxiliary voltage output coupled to the supply input of the electronic circuit. The auxiliary voltage supply unit is configured to at least temporarily output an auxiliary voltage to the supply input. The auxiliary voltage has a voltage level lower than a voltage level of a main supply voltage supplied by the main supply voltage source.
Thu, 18 Aug 2016 08:00:00 EDTA driver circuit 101 is connected to a control terminal of a semiconductor switching element 1. The driver circuit 101 includes an input circuit 3 connected to an input terminal 50, and an output control circuit 4 connected to the input circuit 3. A pulse signal output from the output control circuit 4 is input to a dead time adjustment circuit 13. The dead time adjustment circuit 13 includes a delay circuit which can delay the rising edge and the falling edge of the pulse signal output from the output control circuit 4 on the basis of signals from temperature analog output circuits 11 and 12. An output from the dead time adjustment circuit 13 is input to the drive circuit 5. The drive circuit 5 outputs a drive signal to an output terminal 51 of the driver circuit 101.
Thu, 18 Aug 2016 08:00:00 EDTThis application relates to an active diode circuit for letting current pass in one direction and blocking current in the opposite direction. The active diode circuit comprises a transistor, a control voltage generation circuit for generating a control voltage that is supplied to a control terminal of the transistor, and a sensing circuit for detecting a quantity indicative of a current flowing through the transistor. The control voltage generation circuit generates the control voltage in dependence on the detected quantity. The application further relates to a method of controlling a transistor to function as an active diode so that current may pass in one direction and is blocked in the opposite direction.
Thu, 18 Aug 2016 08:00:00 EDTAn example of the invention provides a digital delay unit that is made up of a plurality of NAND gates. The digital delay unit includes a first delay path and a second delay path. The first delay path is coupled between a first input terminal and an output terminal to provide a basic time delay which is caused by one NAND gate. The second delay path is coupled between a second input terminal and the output terminal to provide at least three basic time delays.
Thu, 18 Aug 2016 08:00:00 EDTEmbodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a data path to pass a data signal and a clock path to pass a clock signal. A jitter equalizer may be coupled with the data path and/or clock path to provide a programmable delay to the data signal and/or clock signal, respectively. The delay may be determined by a training process in which a supply voltage may be modulated by a modulation frequency. The delay may be dependent on a value of the supply voltage, such as a voltage level and/or jitter frequency component of the supply voltage. A phase error detector is also described that may be used with the communication circuit and/or other embodiments.
Thu, 18 Aug 2016 08:00:00 EDTA comparison circuit is provided which is capable of removing the influence of an offset voltage of a comparator in the comparison circuit and obtaining a highly accurate comparison/determination result even at a high temperature. The comparison circuit includes a comparator having a first input terminal inputted with a first input voltage through a first capacitor, a second input terminal inputted with a second input voltage through a second capacitor, and an output terminal; a first switch which has one end connected to the first input terminal and is turned on in a sample phase to set a voltage of the first input terminal as a voltage of the output terminal; a second switch which has one end connected to the second input terminal and is turned on in the sample phase to set a voltage of the second input terminal as a reference voltage; and a third switch which is turned on in a comparison phase to equalize voltages of the other end of the first switch and the other end of the second switch.
Thu, 18 Aug 2016 08:00:00 EDTA frequency multiplier includes an input terminal, an output terminal, a first transistor having a first gate to which a radiofrequency signal is input from the input terminal, a first drain from which an output signal is issued to the output terminal, and a first source, a second transistor having a second gate, a second source to which the radiofrequency signal is input from the input terminal, and a second drain from which an output signal is issued to the output terminal, and a stabilizing resistor which is a resistor connected to the second gate, wherein no resistor exists on the path for the radiofrequency signal, and wherein the stabilizing resistor suppresses a reflex gain produced by the second transistor.
Thu, 18 Aug 2016 08:00:00 EDTA Schmitt trigger circuit includes a first inverter, second inverter, first feedback unit, and second feedback unit. The first inverter includes a PMOS transistor unit and an NMOS transistor unit which generate an internal signal by inverting an input signal based on a first feedback signal and provide the internal signal to a first node. A second inverter generates an output signal by inverting the first signal. A first feedback unit generates a first feedback signal providing a first hysteresis character to a first unit among the PMOS transistor unit and NMOS transistor unit based on a first signal of the first node. A second feedback unit generates a second feedback signal providing a second hysteresis character to a second unit among the PMOS transistor unit and NMOS transistor unit based on the output signal. The second feedback unit provides the second feedback signal to the first node.
Thu, 18 Aug 2016 08:00:00 EDTIn a semiconductor device, a charge pump operates in accordance with a clock signal and thereby generates a boosted voltage of a polarity which is the same as or reverse to the polarity of an input voltage. An oscillation circuit generates and outputs a clock signal. The oscillation circuit cyclically fluctuates a frequency of the clock signal within a predetermined fluctuation range. Thereby, EMI noise generated corresponding to the frequency of the clock signal for driving the charge pump is reduced.