Thu, 27 Oct 2016 08:00:00 EDTA resonator is supplied with voltage from a constant-voltage source, and the constant-voltage source outputs output voltage adjusted by a voltage adjustment signal to the resonator. The resonator outputs a clock signal having a frequency varied by varying capacitance in accordance with a received control signal and a frequency adjustment signal, and a frequency of the clock signal is varied by voltage output from the constant-voltage source.
Thu, 27 Oct 2016 08:00:00 EDTA phase locked loop circuit including: a loop filter having a high cutoff characteristic and a low cutoff characteristic that are switchable, and a switching circuit configured to: detect a timing when an irregular gap of no signal, included in a input signal, does not occur, and switch, in the detected timing, a cut off characteristic of the loop filter from the high cutoff characteristic during entrainment of phase locking of a output signal with the input signal to the low cut off characteristic after the phase locking.
Thu, 27 Oct 2016 08:00:00 EDTA phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code.
Thu, 27 Oct 2016 08:00:00 EDTA regenerative frequency divider comprising an in-phase mixer circuit and a phase-shifted mixer circuit. At least one switching device of the in-phase mixer circuit is of a smaller scale than a corresponding switching device of the transconductance component of the in-phase mixer circuit. In some examples, at least one switching device within an input switching stage of the regenerative frequency divider forming part of the phase-shifted mixer circuit is of a smaller scale than a respective corresponding switching device within the input switching stage forming part of the in-phase mixer circuit. In some further examples, all switching devices within the phase-shifted mixer circuit are of a small scale than respective corresponding switching devices within the in-phase mixer circuit.
Thu, 27 Oct 2016 08:00:00 EDTA method of dividing a clock signal by an input signal of N bits with M most significant bits is described herein. The method includes dividing the clock signal by the most significant bits of the input signal 2N-M−1 times out of 2N-M divisions of the clock signal, using a divider. The clock signal is divided by a sum of the most significant bits and the least significant bits one time out of 2N-M divisions of the clock signal, using the divider. The clock signal is also divided by 2N-M, 2N-M times, using the divider.
Thu, 27 Oct 2016 08:00:00 EDTA Low-Voltage Differential Signaling (differential signaling) driver circuit (10) comprising enable circuitry for enabling and disabling the differential signaling driver circuit (10) in accordance with an control signal is described. The differential signaling driver circuit (10) comprises: a differential output (12, 13) connected or connectable to a differential signaling receiver circuit via a differential transmission line; current control circuitry (14) for driving a signal current through the differential output (12, 13) in accordance with a driver signal; feedback circuitry (16) for driving the current control circuitry (14) to counteract a difference between a common mode voltage of the differential output (12, 13) and a reference voltage from a reference voltage provider; and the enable circuitry (18). The feedback circuitry (16) comprises a common mode node (20) for providing the common mode voltage (Vcm), a reference input (22) connected or connectable to the reference voltage provider, and a feedback input (24). The enable circuitry (18) is arranged to connect the feedback input (24) to the common mode node (20) when the differential signaling driver circuit (10) is in an enabled state and to the reference voltage provider when the differential signaling driver circuit (10) is in a disabled state. A method of enabling (5.1) and disabling (5.2) a Low-Voltage Differential Signaling (differential signaling) driver circuit (10) is also proposed.
Thu, 27 Oct 2016 08:00:00 EDTProvided are semiconductor circuits. A semiconductor circuit includes: a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.
Thu, 27 Oct 2016 08:00:00 EDTThe operating device for an electrical apparatus or a system, in particular for a vehicle component, is provided with at least one elastically mounted operating element (12), a counter-element (14), relative to which the at least one operating element (12) is movable when actuated, thereby varying the distance, namely as seen in the movement direction, and at least one capacitor (38) which comprises a first carrier body (20) with a first capacitor electrode (34) and an elastically bendable second carrier body (22), designed as a bending bar, having a first end (26) and a second end (32) opposite said first end and having a second capacitor electrode (36) opposite the first capacitor electrode (34). Connected to the first and second capacitor electrode (34, 36) is an evaluation unit (42) for determining the capacitance and/or a change in the capacitance of the at least one capacitor (38) upon actuation of the at least one operating element (12).
Thu, 27 Oct 2016 08:00:00 EDTAn integrated circuit die includes a plurality of transistors formed in a semiconductor substrate, the body regions of the transistors on a doped well region of the semiconductor substrate. A body bias voltage generator generates a positive body bias voltage, and a negative body bias voltage in the ground body bias voltage. A multiplexer selectively outputs one of the positive, negative, or ground body bias voltage to the doped well region of the semiconductor substrate based on the temperature of the semiconductor substrate.
Thu, 27 Oct 2016 08:00:00 EDTA coil-driving IC having a first output terminal configured connected to a first terminal of a coil and a second output terminal configured connected to a second terminal of the coil is disclosed. The coil-driving IC comprises a first switch connected to the first output terminal; a second switch connected to the second output terminal; a current driving part comprising a first current terminal connected to the first output terminal via the first switch and a second current terminal connected to the second output terminal via the second switch; and a gate driving part controlling the first switch and the second switch so that, when the coil is driven by a current provided from the first current terminal or the second current terminal, the first switch and the second switch are in an ON state, otherwise, the first switch and the second switch are in an OFF state.
Thu, 27 Oct 2016 08:00:00 EDTThe present invention comprises a method and apparatus for controlling an IGBT device. The method comprises, upon receipt of a first and at least one further IGBT control signals, the first IGBT control signal indicating a required change in operating state of the IGBT device, controlling an IGBT driver module for the IGBT device to change an operating state of the IGBT device by applying a first logical state modulation at an input of an IGBT coupling channel, and applying at least one further modulation to the logical state at the input of the IGBT coupling channel in accordance with the at least one further IGBT control signal within a time period from the first logical state modulation, the time period being less than a state change reaction period Δt for the at least one IGBT device.
Thu, 27 Oct 2016 08:00:00 EDTIn the case of reducing an effect of variations in current characteristics of transistors by inputting a signal current to a transistor in a pixel, a potential of a wiring is detected by using a precharge circuit. In the case where there is a difference between a predetermined potential and the potential of the wiring, a charge is supplied to the wiring to perform a precharge by charging rapidly. When the potential of the wiring reaches the predetermined potential, the supply of charge is stopped and a signal current only is supplied. Thus, a precharge is performed only in a period until the potential of the wiring reaches the predetermined potential, therefore, a precharge can be performed for an optimal period.
Thu, 27 Oct 2016 08:00:00 EDTSystems, circuits, and methods for operating an Insulated-Gate Bipolar Transistor (IGBT) are provided. A switching circuit is described that includes a first current path and a second current path. The first current path carries current away from the gate of the IGBT during a first phase of switching and the second current path carries current away from the gate of the IGBT during a second phase of switching.
Thu, 27 Oct 2016 08:00:00 EDTThe present disclosure is applicable to electronic fields, and provides a voltage comparator. The voltage comparator includes a first branch, a second branch and a third branch. The first branch and the second branch both have self-biasing capabilities, and require no dedicated bias circuit. Under the same power voltage, the static power consumption of the voltage comparator is relatively low; fewer the power consuming branches exist in the circuit, and the reliability is high under low power consumption.
Thu, 27 Oct 2016 08:00:00 EDTSystems and methods for generating a spurious signal cancellation signal, the system comprising two direct digital synthesizers (DDS). The first DDS provides phase tracking to correct for rounding errors. The second DDS outputs a frequency that is exactly equal to N/M*CLK, where N and M are values selected to set the output frequency equal to the frequency of a spurious signal to be cancelled, and CLK is a clock frequency used to clock the first and second DDS circuits.
Thu, 27 Oct 2016 08:00:00 EDTMethods and apparatuses for measuring a phase noise level in an input signal are disclosed. An input signal can be delayed to generate a delayed version of the input signal. Next, a phase difference can be detected between the input signal and the delayed version of the input signal. A phase noise level in the input signal can then be determined based on the detected phase difference. The measured phase noise level can then be used to suppress phase noise in the input signal.
Thu, 27 Oct 2016 08:00:00 EDTA noise filter circuit includes a first control circuit, a second control circuit, and a central processing unit (CPU). The first control circuit includes a first control terminal and a first output terminal. The second control circuit includes a second control terminal and a second output terminal. The CPU includes a clock signal input terminal electrically coupled to the second output terminal. The first control terminal receives a first voltage signal, the first output terminal being electrically coupled to the second control terminal, and the second control terminal receives a second voltage signal at a first voltage level. The first control circuit detects clock signals received by the CPU, the first control terminal receives a first voltage signal at a first voltage level when there are noise signals in the clock signals. The second output terminal is grounded to filter out the noise signals in the clock signals.
Thu, 27 Oct 2016 08:00:00 EDTA charge pump circuit generates a charge pump voltage that powers a bias circuit. The bias circuit generates a reference current and generates switch currents from the reference current. Gate-source voltages are generated from the switch currents and applied to switching components of switch circuits to connect two nodes. The gate-source voltages can be generated in the bias circuit and provided to the switch circuits. The gate-source voltages can also be generated in the switch circuits.
Thu, 27 Oct 2016 08:00:00 EDTA semiconductor substrate includes: a first conduction type first semiconductor region exposed at a first surface; a second conduction type main base region exposed at the first surface at a position adjacent to the first semiconductor region; and a second conduction type surface layer base region which is exposed at the first surface at a position adjacent to the main base region and has a smaller thickness than that of the main base region. A gate electrode is disposed across upper portions of the first semiconductor region, the main base region, and the surface layer base region.
Thu, 27 Oct 2016 08:00:00 EDTAn integrated circuit, a method of forming an integrated circuit, and a semiconductor are disclosed for preventing unauthorized use in radiation-hard applications. In one embodiment, the integrated circuit comprises a silicon-on-insulator (SOI) structure, a radiation insensitive sub-circuit, and a radiation sensitive sub-circuit. The SOI structure comprises a silicon substrate, a buried oxide layer, and an active silicon layer. The radiation insensitive sub-circuit is formed on the active layer, and includes a partially depleted transistor. The radiation sensitive sub-circuit is formed on the active layer, and includes a fully depleted transistor, to prevent operation of the radiation sensitive sub-circuit under specified radiation conditions. Each of the partially depleted transistor and the fully depleted transistor includes a channel region formed in the active silicon layer, and the channel regions of the partially depleted transistor and the fully depleted transistor have substantially the same thickness but different doping concentrations.
Thu, 27 Oct 2016 08:00:00 EDTA two-to-one multiplexor comprises a first data input configured to hold data provided from a first preceding asynchronous pipeline stage and a second data input configured to hold data provided from a second preceding asynchronous pipeline stage, a 4-phase bundled data protocol facilitating communication between the first and the second data inputs and the first and second preceding asynchronous pipeline stage, an arbitration unit connected to the first data input and the second data input, and configured to select which of the data from the first and the second data inputs is released, a request release unit, and a reset unit wherein the arbitration unit, the request release unit, and the reset unit implement and complete a second 4-phase bundled data protocol facilitating communication with a succeeding asynchronous pipeline stage for transmission of the data chosen by the arbitration unit thereby providing asynchronous multiplexing of the data.
Thu, 27 Oct 2016 08:00:00 EDTAn integrated electronic device includes an electronic component and a temperature transducer. The temperature transducer is electrically arranged between a control terminal and a conduction terminal of the electronic component and includes a first diode. The first diode has a bulk resistance of at least 1Ω.
Thu, 27 Oct 2016 08:00:00 EDTEmbodiments contained in the disclosure provide a method and apparatus for device specific thermal mitigation. The thermal and power behavior of the device, is characterized. A thermal threshold is then determined for the device. The thermal data and thermal ramp factor for each device are determined and stored in a cross-reference matrix. A correlation factor is determined for temperature and frequency. These correlation factors determine a device mitigation temperature. The device mitigation temperature may be stored in a fuse table on the device, with a fuse blown on the device to permanently store the device mitigation temperature. The apparatus includes: an electronic device, a memory within the electronic device, and a set of fuses within the electronic device. The device also includes means for determining if a static or dynamic frequency is high, and means for mitigating a voltage and frequency used by the device, based on that determination.
Thu, 20 Oct 2016 08:00:00 EDTA phase locked loop frequency calibration circuit and a method are provided. The circuit includes a timer, a counter, a control module, a frequency divider and a voltage controlled oscillator; output of voltage controlled oscillator is connected with first input of frequency divider, output of frequency divider is connected with first input of counter, second input of frequency divider, first input of timer and second input of counter are respectively connected with first output of control module, third input of counter is connected with output of timer, output of counter is connected with first input of control module, a reference clock signal is respectively sent to second input of timer and second input of control module, the number of clocks used by frequency divider to perform frequency division on output clock signal of voltage controlled oscillator is sent to third input of control module.
Thu, 20 Oct 2016 08:00:00 EDTA phase-locked loop (PLL) circuit is disclosed. The PLL circuit includes a detecting circuit configured to detect a phase difference between a digitally controlled oscillator (DCO) clock signal and a reference clock signal, and generate a difference signal based on the detected phase difference; a digitized difference generator, coupled to the detecting circuit, configured to generate a control code based upon the difference signal; and a DCO configured to generate the DCO output signal responsive to the control code of the digitized difference generator; wherein the detecting circuit, the digitized difference generator and the DCO form a closed loop and reduce the phase difference between the DCO output signal and the reference clock signal. An associated method and a circuit are also disclosed.
Thu, 20 Oct 2016 08:00:00 EDTDescribed is a phase-locked loop with lower power charge pump. The phase-locked loop comprises: a phase frequency detector to compare a reference clock and a feedback clock and generate a pulse based on the comparison, a charge pump to provide a charge signal corresponding to the pulse, a bias generator to provide biasing for the charge pump, wherein the bias generator is operable to receive a bias enable signal from the phase frequency detector and the bias generator is disabled when the bias enable signal is not asserted, a loop filter coupled to the output of the charge pump to provide a control signal responsive to the charge signal, and a voltage-controlled oscillator (VCO), wherein the oscillating frequency of the VCO is controlled by the control signal.
Thu, 20 Oct 2016 08:00:00 EDTFrequency divider techniques are disclosed which can be used to address two problems: when an incorrect division occurs if the modulus control changes before the divide cycle is complete, and when an incorrect division occurs due to a boundary crossing (e.g., power-of-2 boundary crossing in a fractional-N PLL application). In one embodiment, a frequency divider is provided comprising a plurality of flip-flops operatively coupled to carry out division of an input frequency, and configured to generate a modulus output and receive a divided clock signal of a previous cell. An additional flip-flop is selectively clocked off one of the modulus output or the divided clock of the previous stage, depending at least in part on a Skip control signal applied to a data input of the additional flip-flop, and is further configured to selectively reset the plurality of flip-flops to a state that will result in a correct divide ratio.
Thu, 20 Oct 2016 08:00:00 EDTA semiconductor integrated circuit device, including a semiconductor layer of a first conductivity type, a first well region of a second conductivity type, a second well region of the second conductivity type, and a third well region of the first conductivity type. The device further includes an isolation region electrically isolating a predetermined region in the first well region, a first high-concentration region of the second conductivity type, disposed outside the isolation region and inside one of the first well region and the second well region, and a second high-concentration region of the second conductivity type, disposed inside the isolation region and inside one of the first well region and the second well region. The first and second high-concentration regions each have an impurity concentration that is higher than that of the first well region.
Thu, 20 Oct 2016 08:00:00 EDTA semiconductor apparatus may include an internal voltage level controller configured to output either a normal trimming code or a test voltage code as a voltage control code in response to a test mode signal, a specific operation start signal, and a specific operation end signal. The semiconductor apparatus may include an internal voltage generator configured to generate an internal voltage and control a voltage level of the internal voltage in response to the voltage control code.
Thu, 20 Oct 2016 08:00:00 EDTThe present disclosure relates to a gate driver for driving an inverter. In one embodiment, a gate driver includes an IC module configured to generate the switching signal by using a PWM signal input from the outside, and a power supply managing part configured to apply an IC module driving voltage for drive of the IC module by using a switching element and a driver driving voltage for drive of the gate driver if the driver driving voltage is equal to or larger than a first reference voltage, and is further configured to stop the application of the IC module driving voltage if the driver driving voltage is equal to or lower than a second reference voltage.
Thu, 20 Oct 2016 08:00:00 EDTA switching circuit includes a normally-on switch, a normally-off switch, a current compensating unit and a current sharing unit. Each of the normally-on switch and the normally-off switch include a first terminal, a second terminal and a control terminal respectively. The first terminal of the normally-off switch is connected to the second terminal of the normally-on switch. The second terminal of the normally-off switch is connected to the control terminal of the normally-on switch. The current compensating unit is connected to the normally-on switch and configured to generate a compensating current when a leakage current of the normally-on switch is smaller than the leakage current of the normally-off switch. The current sharing unit is connected to the normally-off switch and configured to share the leakage current of the normally-on switch when the leakage current of the normally-on switch is larger than the leakage current of the normally-off switch.
Thu, 20 Oct 2016 08:00:00 EDTAn integrated circuit embedded in a plug of a universal serial bus (USB) 3.1 type-C cable assembly is disclosed. The integrated circuit includes a first pin connected to an operation transmission line through which an operation voltage is transmitted, a second pin connected to a configuration channel (CC) line, a first resistor connected to the first pin, a ground line, and a switching circuit configured to connect the first resistor and the ground line using a channel voltage supplied to the second pin when the operation voltage is not applied, and disconnect the first resistor from the ground line based on the operation voltage.
Thu, 20 Oct 2016 08:00:00 EDTThe present invention relates to a control system and control method for controlling a switching device (1) integrated in an electronic converter, the object of which is to extend the working voltage range of the switching devices and thus increase the power of the electronic DC/AC converter which prepares the energy produced by a energy generating system and injects it into the electrical grid. It basically comprises a voltage source (3), a capacitance (7), a first gate resistor (21) and a second gate resistor (22), a first circuit formed by a series resistor (6) with a first diode (5), a second circuit formed by a second diode (4) and a connecting element (8) controlled by a control unit (12) that controls the opening and closing thereof. Another object of the present invention is a switching cell for an electronic converter comprising said control system.
Thu, 20 Oct 2016 08:00:00 EDTA drive control device for two semiconductor elements having a transistor structure and a diode structure with a common energization electrode includes: a current detection device outputting a current detection signal of the semiconductor elements; and a first control device outputting a gate drive signal from when a first time period has elapsed from a starting time to when a second time period has elapsed from the starting time, at which an off-command signal is input after it is determined that a current flows through the semiconductor elements in a forward direction of the diode structure during a time period for which an on-command signal is input to the semiconductor elements. The first and the second time periods are preliminary set not to generate an arm short-circuit between two semiconductor elements.
Thu, 20 Oct 2016 08:00:00 EDTThe power circuit includes: a main substrate; a first electrode pattern disposed on the main substrate and connected to a positive-side power terminal P; a second electrode pattern disposed on a main substrate and connected to a negative-side power terminal N; a third electrode pattern disposed on the main substrate and connected to an output terminal O; a first MISFET Q1 of which a first drain is disposed on the first electrode pattern; a second MISFET Q4 of which a second drain is disposed on the third electrode pattern; a first control circuit (DG1) connected between a first gate G1 and a first source S1 of the first MISFET, and configured to control a current path conducted from the first source towards the first gate. There can be provided the power circuit capable of reducing the misoperation and the parasitic oscillation and capable of realizing the high speed switching performance.
Thu, 20 Oct 2016 08:00:00 EDTThe signal multiplexer 1 inputs two selection signals CLK, CLK that sequentially reach significant levels, inputs two input signals IN, IN, and outputs, from an output terminal 14, a signal OUT that depends on an m-th input signal IN of the two input signals when an m-th selection signal CLK of the two selection signals is at the significant level. The signal multiplexer 1 includes a resistance unit 20 and two drive units 301, 302. Each of the drive units 30m includes a driving switch 31m, a selecting switch 32m, and a potential stabilizing switch 33m. When one of the selecting switch 32m and the potential stabilizing switch 33m in each of the drive units 30m is in a closed state, the other is in an open state.
Thu, 20 Oct 2016 08:00:00 EDTEmbodiments are provided for biasing circuits with compensation of process variation without band-gap referenced current or voltage. In an embodiment, a circuit for biasing a field-effect transistor (FET) passive mixer comprises a series of diode-connected FETs, and a series of first resistors connected to a voltage source and the series of diode-connected FETs. Additionally, one or more second resistors are connected to the series of diode-connected FETs and to ground. In an embodiment method, the total number of the diode-connected FETs and the total number of the resistors, including the first and second series of resistors, are selected. The total number of the second resistors is then determined according to a defined relation between the selected total number of diode-connected FETs and the total number of resistors.
Thu, 20 Oct 2016 08:00:00 EDTA circuit includes a time delta detector configured to receive an input clock signal and a reference clock signal and generate a delta pulse signal and a reference pulse signal. A comparison circuit is configured to receive the delta pulse signal and the reference pulse signal. The comparison circuit generates an output indicative of a bit of a time difference between the input clock signal and the reference clock signal. A control circuit is configured to receive the output from the comparison circuit. The control circuit maintains a count of the time difference between the input clock signal and the reference clock signal.
Thu, 20 Oct 2016 08:00:00 EDTCircuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.
Thu, 20 Oct 2016 08:00:00 EDTIn a signal potential converter, a capacitor receives an input signal CIN at one terminal thereof and has the other terminal thereof connected to a terminal node. A clamp circuit defines a potential (signal IN) at the terminal node within the range of a first potential to a second potential. The clamp circuit includes a level adjuster circuit configured to adjust at least one of the first and second potentials according to a supply voltage of a circuit that drives the input signal CIN.
Thu, 20 Oct 2016 08:00:00 EDTFrequency detector and oscillator circuits are disclosed. Example frequency detector and oscillator circuits disclosed herein include a current approximation circuit coupled to an external clock operating at a target frequency. In some examples, the current approximation circuit is configured to determine a magnitude of a first current to charge a capacitor to reach a reference voltage during a first set of clock cycles generated by the external clock. In some examples, the current approximation circuit is further configured to generate an output current based on the magnitude of the first current and to use the output current to produce a comparator output. In some examples, the frequency detector and oscillator circuits further include a latching circuit coupled to receive the comparator output from the current approximation circuit. In some such examples, the latching circuit is configured to generate oscillating signals at the target frequency based on the comparator output.
Thu, 20 Oct 2016 08:00:00 EDTA level shifter for level-shifting a digital input signal referenced to an input ground potential to a digital output signal referenced to an output ground potential, comprising: a capacitor; a driver circuit, including an input node coupled to the digital input signal, and an output node coupled to a first terminal of the capacitor; a receiver circuit, including a first input node coupled to a second terminal of the capacitor, and an output node coupled to the digital output signal; and a latching feedback circuit, including a first input node coupled to the output node of the receiver circuit, and an output node coupled to the second terminal of the capacitor to latch a toggled signal. An optional resistor can be inserted to increase the output resistance of the latching feedback circuit to be substantially larger than the output resistance of the driver circuit.
Thu, 20 Oct 2016 08:00:00 EDTVarious implementations described herein are directed to an integrated circuit for power-on-reset detection. The integrated circuit may include a first stage configured to receive an input voltage signal and provide a triggering signal during ramp of the input voltage signal. The integrated circuit may include a second stage configured to receive the triggering signal from the first stage and provide an output voltage signal during ramp of the input voltage signal via gate leakage through at least one transistor.
Thu, 20 Oct 2016 08:00:00 EDTA clock generation circuit operates in a STANDBY mode as well as conventional OFF and ON modes. In STANDBY mode, a small pre-bias current is applied to amplifiers in the clock generation circuit, which bias voltages on internal nodes to very near their operating voltage values. This reduces transient perturbations on signals as the clock generation circuit is returned to ON mode. The smaller transients settle faster, and allow the clock generation circuit to achieve very fast startup times from STANDBY to ON. The very fast startup times allow the clock generation circuit to be placed in STANDBY mode more often, such as when a system must monitor and rapidly respond to activity on an external bus or interface (such as an RF modem).
Thu, 20 Oct 2016 08:00:00 EDTProvided is a current-to-voltage conversion circuit, including: an input/output node configured to input a current signal including a direct current component and an alternating current component, and to output a voltage based on the current signal; an amplification unit configured to input the voltage of the input/output node; an extraction unit configured to output a voltage based on a direct current component of a voltage output from the amplification unit; a first current supply unit configured to supply a current based on the voltage output from the extraction unit to the input/output node; and a second current supply unit configured to supply a current based on the alternating current component of the current signal to the input/output node. The current supplied by the second current supply unit corresponds to a difference between a current of the current signal and the current supplied by the first current supply unit.
Thu, 20 Oct 2016 08:00:00 EDTA voltage regulator includes: a drive voltage generating part for generating a drive voltage and then apply the drive voltage to a drive line; an output transistor for outputting a voltage corresponding to a voltage value of the drive line as the internal source voltage; and a compulsory drive circuit including a capacitor element configured to receive the source voltage at one end, a first switching element for receiving a ground voltage and applying the ground voltage to the other end of the capacitor element by being set in an ON state over a period in which the selected operational mode is the standby mode, and a second switching element that connects the other end of the capacitor element to the drive line only for a predetermined period in an ON state when the operational mode transitions from the standby mode to the active mode.
Thu, 20 Oct 2016 08:00:00 EDTA method of operating a charge pump where successive values of a charge pump output voltage are measured and compared is presented. The result of the comparison is used to adjust one or more parameters of the charge pump operation A charge pump's maximum efficiency is tracked by storing and comparing successive output voltage values, with sample and hold circuitry.
Thu, 20 Oct 2016 08:00:00 EDTIn one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.
Thu, 20 Oct 2016 08:00:00 EDTThere is provided a stage circuit capable of minimizing a mounting area. The stage circuit includes: an output unit configured to supply a voltage of a first node, an i-th (i is a natural number) carry signal, and to supply an i-th scan signal in response to the voltage of the first node, a voltage of a second node, and a first clock signal, a controller configured to control the voltage of the second node in response to the first clock signal; a pull-up unit configured to control the voltage of the first node in response to a carry signal of a previous stage and a voltage of a first node of the previous stage, and a pull-down unit configured to control the voltage of the first node in response to the voltage of the second node and a carry signal of a next stage.
Thu, 20 Oct 2016 08:00:00 EDTAn electronic device and an integrated circuit thereof are provided. The integrated circuit includes a voltage generator and a current generator with a negative temperature coefficient. The voltage generator generates a reference voltage proportional to an absolute temperature based on a predetermined value. The current generator with the negative temperature coefficient receives the reference voltage and generates a reference current based on the reference voltage.