Thu, 03 Nov 2016 08:00:00 EDTA digitally controlled oscillator (DCO) modulation apparatus and method provides a wideband phase-modulated signal output. An exemplary modulator circuit uses an oscillator in a phase-locked loop. The circuit receives a wrapped-phase input signal, unwraps the wrapped-phase input signal to generate an unwrapped-phase signal, and differentiates the unwrapped-phase signal. The wrapped-phase input signal and the differentiated unwrapped-phase signal are both injected into a feedback loop of the modulator circuit. The feedback loop may include a multi-modulus frequency divider with a frequency divisor that is temporarily incremented or decremented to cancel out abrupt phase jumps associated with the wrapped-phase to unwrapped-phase conversion.
Thu, 03 Nov 2016 08:00:00 EDTAccording to one aspect, the invention relates to a proximity detector (10) of a motor vehicle device (Eq), the proximity detector (10) comprising:—a detection antenna (1) generating a detection signal when a user (U) is in the proximity of said device (Eq);—a printed circuit (2) processing the detection signal in order to command an action of said device (Eq);—and a conducting rod (3) for electrical connection of the detection antenna (1) to the printed circuit (2).
Thu, 03 Nov 2016 08:00:00 EDTA half-bridge circuit can include a high-side HEMT, a high-side switch transistor, a low-side HEMT, and a low-side switch transistor. The die substrates of the HEMTs can be coupled to the sources of their corresponding switch transistors. In another aspect, a packaged electronic device for a half-bridge circuit can have a design that can use shorter connectors that help to reduce parasitic inductance and resistance. In a further aspect, a packaged electronic device for a half-bridge circuit can include more than one connection along the bottom of the package allows less lead connections along the periphery of the packaged electronic device and can allow for a smaller package.
Thu, 03 Nov 2016 08:00:00 EDTA device to drive a plurality of power switches in a power converter with an input voltage port having an input voltage comprises a drive resonant tank, a switch network, a control block configured to control the turn-on and turn-off of drive switches, and an output port. The drive resonant tank comprises a resonant inductor, and a resonant capacitor which comprises an input capacitance of a power switch. The switch network has a plurality of drive switches, which are controlled such that the drive resonant tank goes through a resonant state and a pseudo clamp state consecutively during a switching period. A gate drive voltage of a power switch fluctuates slightly during the pseudo clamp state. The output port has two terminals coupled to a gate and a source of a power switch respectively.
Thu, 03 Nov 2016 08:00:00 EDTThis circuit constant variable circuit changes the circuit constant of a passive element for which the impedance fluctuates according to the frequency of an AC current. The circuit constant variable circuit is equipped with a first bidirectional switch (Q1) connected in series, a series circuit (20) including a passive element (C1), and a second bidirectional switch (Q2) connected in parallel to the series circuit (20).
Thu, 03 Nov 2016 08:00:00 EDTA comparator system may include a comparator circuit and input circuitry coupled to a communication line. The circuitry may include resistors that are used to generate input voltages supplied to input terminals of the comparator. Resistor-dependent currents generated from a resistor-dependent current source may be supplied to the resistors of the input circuitry. The resistors of the input circuitry and resistors of the resistor-dependent current source may be of the same type and/or configured on the same chip to increase stability in the presence of various process-voltage-temperature (PVT) conditions. The comparator system may be implemented as a squelch detector or other signal detection system, such that an output generated by the comparator based on the input voltages may indicate presence or absence of a signal.
Thu, 03 Nov 2016 08:00:00 EDTMethods and apparatus including a latency control circuit are described. An example apparatus includes a delay line circuit configured to delay a clock signal, and a latch control circuit configured to receive the clock signal and the delayed clock signal. The latch control circuit is configured to provide first control signals based on a count associated with the first clock signal. The latch control circuit is further configured to provide second control signals based on the count associated with the first clock signal. The second clock signals are delayed relative to the first clock signals by an amount substantially equal to a delay between the clock signal and the delayed clock signal. The example apparatus further includes a latch circuit configured to latch an input signal responsive to the first control signals. The latch circuit is further configured to provide the latched signal to an output responsive to the second control signals.
Thu, 03 Nov 2016 08:00:00 EDTIn accordance with an embodiment, an automatic zeroing circuit is provided that includes an automatic zeroing circuit, comprising a first voltage adjustment circuit coupled for receiving an induced voltage and a second voltage adjustment circuit coupled for receiving a common voltage. A comparator having an inverting input terminal coupled to the first voltage adjustment circuit and a noninverting input terminal coupled to the second voltage adjustment circuit. In accordance with another embodiment, a method for automatically zeroing a detection circuit includes receiving a first back electromotive force at a first voltage level and shifting the first back electromotive force from the first voltage level to a second voltage level. A comparator circuit is calibrated and the first back electromotive force is detected.
Thu, 03 Nov 2016 08:00:00 EDTDescribed is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node. Described is a flip-flop which comprises: a first latch including: a first AOI logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply, the first latch having an output node; and a second latch having an input node coupled to the output node of the first latch, the second latch having an output node to provide an output of the flip-flop.
Thu, 03 Nov 2016 08:00:00 EDTAn example embodiment includes a fiber optic integrated circuit (IC). The fiber optic IC includes an integrated power supply. The integrated power supply includes a filter, an active switch, and a pulse width modulator (“PWM”). The filter is configured to convert a signal to an output signal of the integrated power supply. The active switch is configured to control introduction of the signal to the filter. The PWM is configured to generate a PWM output signal that triggers the active switch.
Thu, 03 Nov 2016 08:00:00 EDTA circuit for generating a voltage waveform at an output node. The circuit includes a voltage rail connected to the output node via a voltage rail switch; an anchor node connected to the output node via an inductor and a bidirectional switch, wherein the bidirectional switch includes two or more transistors connected in series; and a control unit configured to change the voltage at the output node by controlling the voltage rail switch and the bidirectional switch so that, if a load capacitance is connected to the output node, a resonant circuit is established between the inductor and the load capacitance. The circuit may be included in an apparatus for use in processing charged particles, e.g. for use in performing mass spectrometry or ion mobility spectrometry.
Thu, 03 Nov 2016 08:00:00 EDTA frequency selective circuit includes a first transistor, an impedance element, a first capacitive element, a second capacitive element, a second capacitive and a second transistor. The first transistor includes a first terminal, a second terminal and a control terminal. The impedance element is coupled between the first terminal and the control terminal of the first transistor. The first capacitive element is coupled to the first terminal of the first transistor. The second capacitive element is coupled to the control terminal of the first transistor. The second transistor includes a first terminal, a second terminal and a control terminal, wherein the control terminal of the second transistor is coupled to the control terminal of the first transistor.
Thu, 03 Nov 2016 08:00:00 EDTA bipolar output charge pump circuit having a network of switching paths for selectively connecting an input node and a reference node for connection to an input voltage, a first pair of output nodes and a second pair of output nodes, and two pairs of flying capacitor nodes, and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors connected to the two pairs of flying capacitor nodes, to provide a first bipolar output voltage at the first pair of output nodes and a second bipolar output voltage at the second pair of bipolar output nodes.
Thu, 03 Nov 2016 08:00:00 EDTCompact component arrangements that can be incorporated into integrated circuits are disclosed. In each of these compact component arrangements, a pitch parameter of a first set of components is used to define a pitch parameter of a second set of components that is to be interconnected with the first set of components. In some example embodiments, the first set of components is a set of optical devices and the second set of components is a set of interface circuits (for example, transmitter circuits or receiver circuits). In other example embodiments, the first set of components is the set of interface circuits and the second set of components is a set of synchronizing circuits each of which can be used for example, to retime an electrical signal that is provided to a respective one of the set of interface circuits.
Thu, 03 Nov 2016 08:00:00 EDTTo provide a semiconductor device having a high aperture ratio and including a capacitor with a high charge capacitance. To provide a semiconductor device with a narrow bezel. A transistor over a substrate; a first conductive film over a surface over which a gate electrode of the transistor is provided; a second conductive film over a surface over which a pair of electrodes of the transistor is provided; and a first light-transmitting conductive film electrically connected to the first conductive film and the second conductive film are included. The second conductive film overlaps the first conductive film with a gate insulating film of the transistor laid between the second conductive film and the first conductive film.
Thu, 03 Nov 2016 08:00:00 EDTA semiconductor integrated circuit device having a bulk bias control function is provided. The semiconductor integrated circuit device may be configured to output the first external voltage as a bulk voltage of a transistor in a power-up period, and to output a second external voltage having a higher level than the first external voltage as the bulk voltage of the transistor in a power-down mode.
Thu, 03 Nov 2016 08:00:00 EDTA circuit includes a bias circuit for a biased transistor. The bias circuit includes a master-slave source follower circuit, a reference transistor, and a bias circuit voltage output coupled to the biased transistor and configured to provide a bias voltage. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor. A signal ground circuit may be coupled between the biased transistor and one or more components of the bias circuit that do not generate significant return currents to a power supply ground. A method includes generating a current in a reference transistor according to a first voltage generated using a master source follower circuit, generating a second voltage substantially identical to the first voltage using a slave source follower circuit, and providing the second voltage to a biased transistor. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor.