Thu, 23 Feb 2017 08:00:00 ESTA power switch circuit includes an oscillation circuit that generates a clock signal based on a supplied first voltage. A boosting circuit receiving the clock signal and boosting the first voltage based on the clock signal to output a boosted first voltage as a second voltage is provided. A detection circuit that detects a difference in voltage levels between an input voltage and the first voltage and outputs a voltage selection signal based on the detected difference is provided. A voltage selection circuit that selects one of the first voltage and the second voltage based on the voltage selection signal and outputs the selected voltage is provided. A switching element switching according to a control voltage based on an enable signal and the selected voltage is also provided.
Thu, 23 Feb 2017 08:00:00 ESTA cooperative control method for a plurality of power semiconductor elements connected in parallel. The cooperative control method includes (1) connecting, in a daisy chain configuration, a plurality of current balance control circuits each for driving a corresponding power semiconductor element, and (2) responsive to an input to cause the power semiconductor elements to simultaneously perform switching operations, comparing current information of each power semiconductor element with that of an adjacent power semiconductor element, and delaying, using the current balance control circuits, turn-on time or turn-off time of each power semiconductor element, upon determining that the turn-on time or the turn-off time is earlier than turn-on time or turn-off time obtained from the current information of the adjacent power semiconductor element.
Thu, 23 Feb 2017 08:00:00 ESTDisclosed is a method and a drive circuit. The method includes measuring a frequency of an input signal received by a drive circuit and driving a transistor device by the drive circuit based on the input signal such that a switching speed of the transistor is dependent on the measured frequency. The drive circuit is configured to receive an input signal, to measure a frequency of the input signal, and to drive a transistor device based on the input signal such that a switching speed of the transistor is dependent on the measured frequency.
Thu, 23 Feb 2017 08:00:00 ESTA semiconductor system may include a first semiconductor device configured to output a command and receive data. The semiconductor system may include a second semiconductor device configured to generate a period signal, the period signals periodically toggled in response to the command, output the data in response to the period signal, and discharge the charges of an internal node if the period signal is not toggled during a predetermined section.
Thu, 23 Feb 2017 08:00:00 ESTA signal frequency conversion circuit is configured to reduce power consumption and resource costs of the signal frequency conversion circuit. Embodiments of the present disclosure include a primary-stage frequency conversion module and at least one subsequent-stage frequency conversion module that is in series connection, where the primary-stage frequency conversion module includes a first filter and a numerically controlled oscillator NCO, and an output of the first filter is connected to an input of the NCO; each subsequent-stage frequency conversion module includes a second filter and a subsequent-stage frequency conversion unit, and an output of the second filter is connected to an input of the subsequent-stage frequency conversion unit; and an output of the NCO is connected to an input of a second filter in a first subsequent-stage frequency conversion module in the at least one subsequent-stage frequency conversion module in series connection.
Thu, 23 Feb 2017 08:00:00 ESTA high-side circuit, adapted for a switched-mode converter, includes a level shifter, a high-side driver, a high-side transistor, a capacitor, and an active diode. The level shifter receives a first signal to generate a set signal. The high-side driver is supplied by a bootstrap voltage of a bootstrap node and a floating reference voltage of a floating reference node, which controls the high-side transistor to provide an input voltage to the floating reference node according to the set signal. The capacitor is coupled between the bootstrap node and the floating reference node. The active diode provides a supply voltage to the bootstrap node. When the bootstrap voltage exceeds the supply voltage, the active diode isolates the supply voltage from the bootstrap node according to a control voltage. The active diode includes a first-type well coupled to the bootstrap node, where the high-side driver is disposed.
Thu, 23 Feb 2017 08:00:00 ESTA semiconductor apparatus including a multichip package is disclosed. The semiconductor apparatus includes a slave chip having a slave region and a master region. The slave region is configured to have a first threshold voltage smaller than an operation voltage and the master region is configured to have a second threshold voltage greater than the operation voltage.
Thu, 23 Feb 2017 08:00:00 ESTA sensor system or a sensor bus comprises a plurality of sensors coupled together by a bus to a controller for sensing physical parameters and responding to changes of the physical parameters. The bus comprises a two wire bus, with a first wire and a second wire, configured to communicate supply signals to the plurality of sensors and data communication signals generated by current modulate signals from the plurality of sensors or the controller. The plurality of sensors and the controller comprise variable current sources. The variable current sources of the sensors generate data communication signals in a first frequency range, while the variable currents sources of the controller and sensors regulate the supply signals from the bus in a different frequency range. A termination network having termination, dividers at both ends of the bus, match the load impedances and the line impedances of the bus within the first frequency range, which is about five to ten times larger than the second frequency range.
Thu, 16 Feb 2017 08:00:00 ESTA phase look loop (PLL) device has a dynamic lock range that is based on a temperature measured during a calibration process. The PLL device includes a calibration circuit configured to receive a temperature reading corresponding to a junction temperature of the PLL device during the calibration process. Based on this temperature reading, the calibration circuit initiates a preset procedure that presets a control voltage of a voltage control oscillator in the PLL device. The preset procedure implements a calibration function defined by a slope with a numerator component and a denominator component. The numerator component corresponds to a range of the control voltage, whereas the denominator component corresponds to a range of ambient temperatures within which the PLL device operates.
Thu, 16 Feb 2017 08:00:00 ESTA phase locked loop circuit includes a voltage controlled oscillator, VCO, configured to receive an oscillator tuning voltage; a phase detector configured to receive an input signal and a reference signal and generate a phase difference pulse signal that is varied in accordance with the oscillator tuning voltage; a loop filter having an input and an output; and a level shifter circuit coupled to an output of the phase detector and the loop filter input and configured to apply a level shift to the phase difference pulse signal such that the level shift is configured to compensate VCO gain and the loop filter averages the phase difference pulse signal to output an averaged signal to the VCO.
Thu, 16 Feb 2017 08:00:00 ESTMethods and systems for a sampled loop filter in a phase locked loop (PLL) may comprise a phase locked loop (PLL) comprising a phase frequency detector, a sampled loop filter comprising a plurality of capacitors and at least one switch, a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter, and a frequency divider. The PLL generates at least one clock signal, and the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero. The frequency divider may be a fractional-N divider. A second switch in said sampled loop filter may have switching times that are non-overlapping with switching times of the at least one switch. Capacitors may be coupled to ground from each terminal of the second switch.
Thu, 16 Feb 2017 08:00:00 ESTA modular capacitive sensing switch provides a separate circuit module attachable to a variety of electrode modules, the latter having different configurations. Embodiments providing adhesive mounting and network connections allow simple configuration of a wide variety of capacitive touch panel systems.
Thu, 16 Feb 2017 08:00:00 ESTAn apparatus having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to translate an input signal in a first voltage domain to generate a complementary pair of first signals in a second voltage domain. The second circuit may be configured to logically switch the first signals to generate a complementary pair of second signals in the second voltage domain. The first signals may be logically switched such that both of the second signals are inactive before one of the second signals transitions from inactive to active. The third circuit may be configured to amplify the second signals to generate a complementary pair of output signals in the second voltage domain. Each of the output signals generally has a current capacity to drive one or more of a plurality of diodes in a diode switch circuit.
Thu, 16 Feb 2017 08:00:00 ESTA pulse-transformer-based isolated gate driver circuit uses a small count of high-temperature-qualified components to drive a power semiconductor switch with asymmetrical voltage biases. A differential driver generates a pulse signal from a pulse-width-modulated signal, which is passed to a charge and lock circuit through a transformer. The charge and lock circuit includes an activation path and a deactivation path, which are selectively open to current flow based on positive or negative voltage pulses in the pulse signal, to selectively turn the main semiconductor switch on or off. The charge and lock circuit can lock voltage across the main semiconductor switch to keep the main semiconductor switch in an “on” or and “off” state.
Thu, 16 Feb 2017 08:00:00 ESTA buffer circuit includes first and second current generators, a comparator, a differential driver, and an inverter. The first current generator outputs a first current corresponding to a reference voltage. The second current generator generates a limit current corresponding to an input limit voltage, and outputs a second current having a size equal to about half of the limit current. The sizes of the first current and the limit current are controlled by the feedback voltage. The comparator generates the feedback voltage by comparing the first and second currents. The differential driver generates an internal current, and controls the internal current based on the feedback voltage. The magnitudes of an upper limit value and a lower limit value of the internal current are substantially equal to each other with respect to a reference value. The inverter generates an output current by inverting the internal current based on supply voltage.
Thu, 16 Feb 2017 08:00:00 ESTA power switching cell with normally on field-effect transistors comprises a current switch receiving the control input signal over an activation input and a power transistor for switching a high voltage VDD applied to its drain, to its source that is connected to the output port of the cell. The control of the gate of the power transistor whose source is floating, according to the input signal, is provided by a self-biasing circuit connected between its gate and source. The current switch is connected between the self-biasing circuit and a zero or negative reference voltage. The self-biasing circuit comprises a transistor whose source or drain is connected to the gate or source of the power transistor. The gate of this transistor is biased by a resistor connected between its gate and source, and between the current switch and the source. The transistors are HEMT transistors using GaN or AsGa technology.
Thu, 16 Feb 2017 08:00:00 ESTIn a semiconductor module, second semiconductor chips (e.g., diodes) are disposed closer to a laminated substrate than first semiconductor chips (MOSFETs). When a control signal supplied to gate electrodes of the first semiconductor chips (MOSFETs) is off, an electric current produced by a voltage from source terminals to a drain board mainly flows through the second semiconductor chips.
Thu, 16 Feb 2017 08:00:00 ESTA symmetrically-bidirectional bipolar transistor circuit where the two base contact regions are clamped, through a low-voltage diode and a resistive element, to avoid bringing either emitter junction to forward bias. This avoids bipolar gain in the off state, and thereby avoids reduction of the withstand voltage due to bipolar gain.
Thu, 16 Feb 2017 08:00:00 ESTAn electronic circuit includes a first level shift circuit, a second level shift circuit, an internal circuit, a high voltage circuit, first and second transistors, and first and second protective circuits. The first and second protective circuits perform control the first and second transistors so as to make them non-conductive when at least one of a plurality of types of power supply voltages becomes equal to or less than a predetermined value.
Thu, 16 Feb 2017 08:00:00 ESTA technique of reducing leakage energy associated with a post-silicon target circuit is generally described herein. One example method includes purposefully aging a plurality of gates in the target circuit based on a targeted metric including a timing constraint associated with the target circuit.
Thu, 16 Feb 2017 08:00:00 ESTSubject matter disclosed herein may relate to programmable current for correlated electron switches.
Thu, 16 Feb 2017 08:00:00 ESTIn some examples, a circuit is described. The circuit may be included in a digital phase-locked loop (PLL) and may include a first delay cell, a second delay cell, and a delay controller. The first delay cell may include a first inverter circuit that includes first and second transistors and may be configured to receive and to delay a first signal. The delay of the first inverter circuit may be based on first and second voltages respectively provided to the first and second transistors. The second delay cell may include a second inverter circuit that includes third and fourth transistors and may be configured to receive and to delay a second signal. The delay of the second inverter circuit may be based on third and fourth voltages respectively provided to the third and fourth transistors. The delay controller may be configured to provide the first, second, third, and fourth voltages.
Thu, 16 Feb 2017 08:00:00 ESTA semiconductor device includes a first circuit block that is connected between a first power supply voltage line and a first reference voltage line, a second circuit block that is connected between a second power supply voltage line and a second reference voltage line and transmits and receives signals with the first circuit block, a first clamp circuit that clamps a potential difference between the second power supply voltage line and the first reference voltage line, a resistor circuit that is connected between the second power supply voltage line and the second circuit block and includes a resistance value that is greater than an impedance of the first clamp circuit, and a second clamp circuit that clamps a potential difference between a line connected between the resistor circuit and the second circuit block and the first reference voltage line.
Thu, 16 Feb 2017 08:00:00 ESTA system and method sequentially measure the amplitude and phase of an output signal of a device under test in each of two or more frequency ranges which together span the output signal spectrum, using a local oscillator (LO) signal whose frequency and phase change for each measurement. The measured phase of the output signal is adjusted for at least one of the frequency ranges to account for the change of phase in the LO signal from measurement of one frequency range to another frequency range, including applying to the measured phase a phase offset determined by measuring the phases of two pilot tones in the two or more frequency ranges, using the LO signal. The phase-adjusted measurements of the output signal in the two or more frequency ranges are stitched together to determine the amplitude and phase of the output signal across the output spectrum.
Thu, 16 Feb 2017 08:00:00 ESTA pulse generator and a method of fabricating a pulse generator are described. The pulse generator includes an input node to receive an input voltage, a first capacitor, and a second capacitor. The first capacitor is positioned between the input node and the second capacitor. An output node outputs an output voltage with a pulse shape, and the pulse generator also includes at least one switch between the input node and the second capacitor. The at least one switch controls the pulse shape of the output voltage.
Thu, 16 Feb 2017 08:00:00 ESTA particular apparatus includes a magnetic tunnel junction (MTJ) device and a transistor. The MTJ device and the transistor are included in a comparator that has a hysteresis property associated with multiple transition points that correspond to magnetic switching points of the MTJ device.
Thu, 16 Feb 2017 08:00:00 ESTIn one embodiment, a semiconductor device may include forming a first inverter and a second inverter to selectively receive separate inputs of a differential input signal and directly connecting each of the first and second inverters to receive power directly from a voltage input and a voltage return. The first inverter may be configured to include a first control switch that is configured to selectively couple together an upper transistor and a lower transistor of the first inverter. The second inverter may be configured to include a second control switch that is configured to selectively couple together an upper transistor and a lower transistor of the second inverter.
Thu, 16 Feb 2017 08:00:00 ESTA cascode voltage generating circuit and method are provided. The circuit includes four switching elements. In a high voltage operation mode, the first and second switching elements, respectively, couple a first intermediate voltage input node to a first intermediate voltage output node, and a second intermediate voltage input node to a second intermediate voltage output node. In a low voltage operation mode, the third switching element couples the first and second intermediate voltage input nodes to a ground reference voltage level, and the fourth switching element couples the first and second intermediate voltage output nodes to a supply voltage level.
Thu, 16 Feb 2017 08:00:00 ESTA charge pump circuit using more than one parallel source is described. A flying capacitor of the charge pump maintains a break-before-make time with respect to the switches within a side of the charge pump. A flying capacitor of the charge pump takes advantage of a make-before-break time with respect to the switches between the sides of the charge pump. This results in the shared load of the charge pump always receiving current from a flying capacitor. This slight change of control of the flying capacitor switching phases removes the need for a filtering capacitor within the charge pump.
Thu, 16 Feb 2017 08:00:00 ESTA system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.
Thu, 16 Feb 2017 08:00:00 ESTAn internal voltage generator includes: a comparison block suitable for comparing an internal voltage with a reference voltage and generating a first comparison signal having an analog level corresponding to a comparison result a first driving block suitable for driving an output terminal of the internal voltage with a source voltage in response to the first comparison signal; a logic block suitable for generating a second comparison signal having a logic level based on the first comparison signal; and a second driving block suitable for driving the output terminal of the internal voltage with the source voltage based on the second comparison signal.
Thu, 16 Feb 2017 08:00:00 ESTThere is provided a driving circuit for driving a capacitive load including: a modulation portion which generates a modulation signal pulse-modulated from a source signal; a gate driver which generates an amplification control signal based on the modulation signal; a transistor which generates an amplification modulation signal amplified from the modulation signal based on the amplification control signal; a low pass filter which demodulates the amplification modulation signal and generates a driving signal; a feedback circuit which sends back the driving signal to the modulation portion; a boosting circuit which supplies a voltage which has been boosted.
Thu, 09 Feb 2017 08:00:00 ESTA control method for a delay locked loop includes: delaying an input signal to generate an internal signal; delaying the internal signal to generate an output signal; and selectively providing a reference clock signal or the output signal as the input signal according to the output signal and the internal signal.
Thu, 09 Feb 2017 08:00:00 ESTA semiconductor device detects an edge of input data input into a data retention circuit to which a clock signal is supplied, resets a first count value obtained by counting an edge detection frequency with a clock signal, resets a second count value obtained by counting the edge detection frequency with an inverted clock signal, and thereby detects an abnormality of the clock signal in accordance with a situation that either of the first count value and the second count value has reached a value indicative of an overflow state.
Thu, 09 Feb 2017 08:00:00 ESTIn one embodiment, method for frequency division comprises propagating a modulus signal up a chain of cascaded divider stages from a last one of the divider stages to a first one of the divider stages, and, for each of the divider stages, generating a respective local load signal when the modulus signal propagates out of the divider stage. The method also comprises, for each of the divider stages, inputting one or more respective control bits to the divider stage based on the respective local load signal, the one or more respective control bits setting a divider value of the divider stage.
Thu, 09 Feb 2017 08:00:00 ESTA level shifter circuit includes a level shifting unit configured to receive signals that may vary in a first range via a positive input terminal and a negative input terminal, respectively and to output signals that may vary in a second range to a positive output terminal and a negative output terminal, respectively, where the second range is larger than the first range, a first pre-charging unit configured to pre-charge the positive output terminal to a predetermined level when a clock is in a first level, and a second pre-charging unit configured to pre-charge the negative output terminal to the predetermined level when the clock is in the first level.
Thu, 09 Feb 2017 08:00:00 ESTAn illustrative device includes a first silicon-controlled rectifier (SCR) and a second silicon-controlled rectifier (SCR) connected in anti-parallel and a first commutation module, which includes a first voltage source, a first diode, and a first self-commutating semiconductor switch. The device also includes a second commutation module including a second voltage source, a second diode, and a second self-commutating semiconductor switch. The first voltage source, the first diode, and the first self-commutating semiconductor switch of the first commutation module are connected in series. The second voltage source, the second diode, and the second self-commutating semiconductor switch of the second commutation module are connected in series. The first SCR, the second SCR, the first commutation module, and the second commutation module are connected in parallel. The commutation modules are configured to apply reverse bias voltages to the first and second SCRs to turn off the SCRs.
Thu, 09 Feb 2017 08:00:00 ESTTo provide a small driver IC, a driver IC with a narrow width, a driver IC capable of high-speed operation, a small semiconductor device, a semiconductor device with a narrow width, or a semiconductor device capable of high-speed operation. The semiconductor device includes first to third circuits. The first and second circuits each include transistors with a first channel width. The third circuit includes transistors with a second channel width. The second channel width is larger than the first channel width. The first circuit is configured to select one of first to 2N-th potentials (N is an integer of 1 or more). The second circuit is configured to select one of (2N+1)-th to 4N-th potentials. The third circuit is configured to select the potential selected by the first circuit or the potential selected by the second circuit. The first to third circuits are arranged in line.
Thu, 09 Feb 2017 08:00:00 ESTA Single-Pole-Single-Throw (SPST) switch for RF application is disclosed that can include a semiconductor MOSFET transistor T, wherein its drain terminal can be connected to a resistor R3 and capacitor C2. It can have a source terminal connected to a resistor R1 and capacitor C1, a gate terminal connected to resistor R2, a body connected by resistor R4 to GND, and the body can be connected to the anode of a diode DE The Cathode of diode D1 can be connected to a power supply Vdd through a resistor R6. The Cathode of diode D1 can also be connected to the cathode of another diode D2. The anode of D2 can be connected to GND through resistor R5. Capacitor C1 can be connected to an I/O port P1, and capacitor C2 can be connected to an I/O port P2. Inductor L1 can connect to ports P1 and P2, while inductor L2 can connect the source terminal and drain terminal of MOSPET T. This disclosure also provides a Single-Pole-Double-Throw (SPDT) switch and Single-Pole-Multiple-Throw (SPMT) switch based on the proposed SPST concept. The SPST disclosed can offer higher isolation and higher linearity to the transmit (TX) arm of the Radio-Frequency Front-End-Module (RF FEM), while maintaining relatively good performance in the receive (RX) arm of the RF FEM.
Thu, 09 Feb 2017 08:00:00 ESTAn apparatus for performing signal driving in an electronic device may include a decoupling capacitor and at least one switching unit (e.g. one or more switching units). The decoupling capacitor may have a first terminal and a second terminal, and may be positioned in an output stage within the electronic device and coupled between a first predetermined voltage level and another predetermined voltage level, where the apparatus may perform signal driving with aid of the output stage. In addition, the aforementioned at least one switching unit may be coupled between one terminal of the first and the second terminals of the decoupling capacitor and at least one of the first predetermined voltage level and the other predetermined voltage level, and may be arranged for selectively disabling the decoupling capacitor.
Thu, 09 Feb 2017 08:00:00 ESTA pulse-transformer-based isolated gate driver circuit uses a small count of high-temperature-qualified components to drive a power semiconductor switch with asymmetrical voltage biases. A differential driver generates a pulse signal from a pulse-width-modulated signal, which is passed to a charge and lock circuit through a transformer. The charge and lock circuit includes an activation path and a deactivation path, which are selectively open to current flow based on positive or negative voltage pulses in the pulse signal, to selectively turn the main semiconductor switch on or off. The charge and lock circuit can lock voltage across the main semiconductor switch to keep the main semiconductor switch in an “on” or and “off” state.
Thu, 09 Feb 2017 08:00:00 ESTAn integrated circuit controls one or more external back-to-back (anti-series) transistor switches with three pins per switch. Two pins couple the switch terminals of the external switch to terminals of an internal anti-series switch. An intermediate source node of the internal switch provides a reference voltage that is representative of the external switch's intermediate source node. A predriver of the integrated circuit drives a gate signal relative to the reference voltage, enabling fast, non-dissipative switching of the external switch. A disclosed method includes coupling switch terminal signals from an external anti-series switch to terminals of an internal anti-series switch; and driving a gate signal to the external anti-series switch relative to a reference voltage of an intermediate node of the internal anti-series switch.
Thu, 09 Feb 2017 08:00:00 ESTA driving circuit including: a voltage detector that detects the sum voltage of a positive bias voltage and a negative bias voltage, the negative bias voltage or the positive bias voltage; and a switching element that is connected to the control terminal of a power element and the negative side of a negative-voltage power supply; wherein, when the value of the detection target voltage becomes lower than a voltage setting value or when a voltage between the control terminal and the reference terminal in the power element increases in a state where the value of the detection target voltage is lower than the voltage setting value, the voltage detector turns on the switching element to thereby supply, between the above terminals in the power element, a voltage of 0V or lower.
Thu, 09 Feb 2017 08:00:00 ESTA multiplexer comprises: a first switch; a second switch; a dummy component coupled to the first switch and the second switch and configured to: reduce a first charge injection of the first switch, and reduce a second charge injection of the second switch; and an output coupled to the first switch, the second switch, and the dummy component. A method comprises: providing an output from either a first switch or a second switch; coupling, by a dummy component, to the first switch and the second switch; using a BBM action; and reducing, by the dummy component, a first charge injection of the first switch or a second charge injection of the second switch.
Thu, 09 Feb 2017 08:00:00 ESTThe disclosure generally relates to a method and an apparatus for providing an adjustable high resolution dead time, and more specifically, to a method and an apparatus for inserting an adjustable high resolution dead time in a PWM signal. A method for inserting an adjustable high resolution dead time in a PWM signal includes receiving a clock signal at a delaying circuitry and generating, by the delaying circuitry, a plurality of phases, receiving the generated plurality of phases at a first multiplexer, and selecting and forwarding, by the first multiplexer, a first phase of the plurality of phases based on a first high resolution dead time value. The method further includes shifting a rising edge and/or a falling edge of the PWM signal using the received first phase forwarded by the first multiplexer.
Thu, 09 Feb 2017 08:00:00 ESTA clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.
Thu, 09 Feb 2017 08:00:00 ESTApparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes a clock generator circuit configured to provide first and second clock signals responsive to an input dock signal. A duty phase interpolator circuit may be coupled to the dock generator circuit and configured to provide a first and second duty cycle corrected interpolated clock signals. A duty cycle adjuster circuit may be coupled to the duty phase interpolator circuit and configured to receive the first and second duty cycle corrected interpolated clock signals and provide a duty cycle corrected dock signal responsive thereto. A duty cycle detector may be coupled to the duty cycle adjuster circuit and configured to detect duty cycle error of the duty cycle corrected clock signal and provide the adjustment signals to correct the duty cycle error.
Thu, 09 Feb 2017 08:00:00 ESTA method and apparatus for measuring a voltage are disclosed. In an embodiment a method for controlling a supply voltage includes providing a first periodic signal by providing a reference voltage to an oscillator, providing a second periodic signal by providing the supply voltage (VOUT) of a voltage source to the oscillator, providing a first count by measuring first periods of the first periodic signal, providing a second count by measuring second periods of the second periodic signal and comparing the first count with the second count.
Thu, 09 Feb 2017 08:00:00 ESTA receiver according to one aspect comprises a latch configured to sample a data signal according to a sampling clock signal, and a plurality of offset-compensation segments, wherein each of the segments is coupled to an internal node of the latch. Each of the segments comprises a compensation transistor, and a step-adjustment transistor coupled in series with the compensation transistor. The receiver further comprises an offset controller configured to selectively turn on one or more of the compensations transistors to reduce an offset voltage of the latch, and a bias circuit configured to apply a bias voltage to a gate of each of one or more of the step-adjustment transistors.
Thu, 09 Feb 2017 08:00:00 ESTA latch and a D flip-flop, where the latch includes a switch, a resistive random-access memory, a bleeder circuit, and a voltage converter. The voltage converter is configured to output an output signal of the latch according to an input signal of the latch when the switch is in an on state, where the output signal remains consistent with the input signal. When the switch changes from the on state to an off state, the resistive random-access memory is configured to work together with the bleeder circuit to enable an output signal of the latch when the switch is in the off state to remain consistent with an output signal of the latch when the switch is in the on state, thereby implementing a nonvolatile latching function. A circuit structure of the latch is simple and integrity of an existing logic circuit can be improved.