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ULTRA LOW PHASE NOISE FREQUENCY SYNTHESIZER

Thu, 06 Apr 2017 08:00:00 EDT

A system for providing ultra low phase noise frequency synthesizers using Fractional-N PLL (Phase Lock Loop), Sampling Reference PLL and DDS (Direct Digital Synthesizer). Modern day advanced communication systems comprise frequency synthesizers that provide a frequency output signal to other parts of the transmitter and receiver so as to enable the system to operate at the set frequency band. The performance of the frequency synthesizer determines the performance of the communication link. Current days advanced communication systems comprises single loop Frequency synthesizers which are not completely able to provide lower phase deviations for errors (For 256 QAM the practical phase deviation for no errors is 0.4-0.5°) which would enable users to receive high data rate. This proposed system overcomes deficiencies of current generation state of the art communication systems by providing much lower level of phase deviation error which would result in much higher modulation schemes and high data rate.



ULTRA LOW PHASE NOISE FREQUENCY SYNTHESIZER

Thu, 06 Apr 2017 08:00:00 EDT

A system for providing ultra low phase noise frequency synthesizers using Fractional-N PLL (Phase Lock Loop), Sampling Reference PLL and DDS (Direct Digital Synthesizer). Modern day advanced communication systems comprise frequency synthesizers that provide a frequency output signal to other parts of the transmitter and receiver so as to enable the system to operate at the set frequency band. The performance of the frequency synthesizer determines the performance of the communication link. Current days advanced communication systems comprises single loop Frequency synthesizers which are not completely able to provide lower phase deviations for errors (For 256 QAM the practical phase deviation for no errors is 0.4-0.5°) which would enable users to receive high data rate. This proposed system overcomes deficiencies of current generation state of the art communication systems by providing much lower level of phase deviation error which would result in much higher modulation schemes and high data rate.



DATA TRANSMISSION CIRCUIT

Thu, 06 Apr 2017 08:00:00 EDT

A data transmission circuit may include a first driving block configured to drive an output terminal for a first time in response to a data driving signal and a level of the output terminal, and a second driving block configured to drive the output terminal for a second time after the first time, in response to the data driving signal.



CIRCUIT AND METHOD FOR MONITORING CORRELATED ELECTRON SWITCHES

Thu, 06 Apr 2017 08:00:00 EDT

A monitoring circuit for a CES element is provided. The circuit includes a control circuit and an output circuit. The control circuit is configured to vary a control signal provided to the CES element. The control signal may be varied for determining an impedance state of the CES element. The output circuit provided an output signal in dependence on the determined impedance state of the CES element.



POWER COMBINING DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

Provided is a power combining device including a comparison circuit configured to output low power comparison signals by comparing a first threshold voltage and levels of voltages of storage elements charged by external power sources according to low power control signals and output high power comparison signals by comparing a second threshold voltage and the levels of the voltages according to high power control signals, a switching signal generation circuit configured to output low power switching signals based on the low power comparison signals and output high power switching signals based on the high power comparison signals, and a switching circuit configured to select loads electrically coupled with the storage elements based on the low power switching signals and the high power switching signals.



GATE VOLTAGE CONTROL APPARATUS

Thu, 06 Apr 2017 08:00:00 EDT

A gate voltage control apparatus is configured to perform first to third processes when turning off the gate type switching device. In the first process, the gate voltage is decreased to a value lower than a threshold value so as to increase a voltage between main terminals. In the second process, the gate voltage is controlled at a value higher than the threshold voltage after timing on which the voltage between the main terminals makes a peak value during the first process. In the third process, the gate voltage is decreased to a value equal to or lower than a threshold voltage while the voltage between the main terminals remains at a value lower than the peak value and higher than the on voltage during the second process.



SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME

Thu, 06 Apr 2017 08:00:00 EDT

A semiconductor device includes: an initialization block suitable for initializing an internal voltage terminal based on a first voltage of a first voltage terminal; a feedback block suitable for generating a feedback voltage based on an internal voltage of the internal voltage terminal; a comparison block suitable for comparing the feedback voltage with a reference voltage to generate a comparison signal; a driving block suitable for driving the internal voltage terminal with a second voltage of a second voltage terminal in response to the comparison signal; and a leakage current prevention block suitable for selectively blocking a current path passing through the internal voltage terminal, the driving block and the second voltage terminal in response to a power-up signal corresponding to the first voltage.



Variable Frequency Charge Pump

Thu, 06 Apr 2017 08:00:00 EDT

A charge pump circuit that utilizes a sensing circuit for determining the current loading or status of the output supply generated by the charge pump circuit to determine a corresponding frequency for a variable rate clock for the charge pump circuit. When a current load is present, the clock frequency automatically ramps up to a relatively high level to increase the output current of the charge pump circuit. When the current load is removed and the supply is settled out, the clock frequency is automatically reduced to a relatively quieter level and the charge pump circuitry operates at a lower power level. Accordingly, the charge pump circuit is only noisy when it has to be, thus providing optimal power when required and being electrically quiet and operating at lower power at all other times.



TRANSITION METAL DICHALCOGENIDE-BASED SPINTRONICS DEVICES

Thu, 06 Apr 2017 08:00:00 EDT

Transition metal dichalcogenide (TMD)-based spintronics devices, each including a TMD thin film layer, a first gate electrode, a first insulating layer sandwiched between the TMD thin film layer and the first gate electrode, a second gate electrode, and a second insulating layer sandwiched between the TMD thin film layer and the second gate electrode. Such a device, when also including a source electrode and a drain electrode, functions as a spin filter. On the other hand, when also including one source electrode and two drain electrode terminals, such a device functions as a spin separator. Also disclosed are methods of using the above-described TMD-based spintronics devices.



NON-LINEAR FIN-BASED DEVICES

Thu, 06 Apr 2017 08:00:00 EDT

An embodiment includes an apparatus comprising: a non-planar fm having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one fmFET. Other embodiments are described herein.



SAMPLING DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

A sampling device samples a differential measuring voltage. The sampling device comprises a first holding device, a second holding device and a multiplexing circuit, which is configured to provide a differential sample of a sampled differential signal, derived from the differential measuring voltage by sampling with a first clock signal of a first clock rate, to the first holding device, at the occurrence of each HIGH-value of a second clock signal of a second clock rate being half of the first clock rate and provide a differential sample of the sample differential signal to the second holding device, at each LOW-value of the second clock signal. The sampling device comprises a reset device configured to reset the second holding device at or after each HIGH-value of the second clock signal and reset the first holding device at or after each LOW-value of the second clock signal.



SCAN DRIVER AND DRIVING METHOD THEREOF

Thu, 06 Apr 2017 08:00:00 EDT

A scan driver includes stages respectively located in channels, the stages outputting a sampling signal, corresponding to at least one clock signal, and a buffer unit including buffers respectively located between the stages and scan lines, the buffers each outputting a scan signal to an output terminal thereof, corresponding to the sampling signal supplied through an input terminal thereof where an ith (i is a natural number) buffer located in an ith channel is electrically coupled to at least one specific buffer located in another channel different from the ith channel.



METHOD FOR SMOOTHING A CURRENT CONSUMED BY AN INTEGRATED CIRCUIT AND CORRESPONDING DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

A method for smoothing current consumed by an electronic device is based on a series of current copying operations and on a current source delivering a reference current. The reference current is delivered in such a manner that current consumed as seen from the power supply depends on the reference current.