Thu, 03 Nov 2016 08:00:00 EDTA communication system includes a two-dimensional array of a plurality of plasmonic nano-antennas. Each plasmonic nano-antenna supports a surface plasmon polariton wave. A plurality of communications elements each excite a corresponding one of the plasmonic nano-antennas, thereby causing a surface plasmon polariton wave that corresponds to a signal to form on each of the plasmonic nano-antennas.
Thu, 03 Nov 2016 08:00:00 EDTA novel method for forming projections and depressions is provided. A novel sealing structure is provided. A novel light-emitting device is provided. A first step of forming a film containing at least two kinds of metals having different etching rates over a surface; a second step of heating the film so that the metal having a lower etching rate segregates; a third step of selectively etching the metal having a higher etching rate; and a fourth step of selectively etching the surface using a residue containing the metal having a lower etching rate are included.
Thu, 03 Nov 2016 08:00:00 EDTAn illuminator includes: a light-emitting element and a light-extraction layer which transmits light occurring from the light-emitting element. The light-emitting element includes a first electrode layer on the light-extraction layer side, the first electrode layer having a light transmitting property; a second electrode layer on the opposite side from the light-extraction layer; an emission layer between the first and the second electrode layers; and a feed portion disposed close to the first electrode layer, the second electrode layer, and the emission layer to apply a voltage between the first electrode layer and the second electrode layer. The light-extraction layer has a structure in which a low-refractive index layer having a relatively low refractive index and a high-refractive index layer having a higher refractive index than does the low-refractive index layer are stacked, an interface between the low-refractive index layer and the high-refractive index layer representing bump-dent features.
Thu, 03 Nov 2016 08:00:00 EDTProvided are an aromatic amine compound as represented by formula (1), used for improving light extraction efficiency and color purity of an organic light-emitting element, an organic light-emitting element material containing the aromatic amine compound, an organic light-emitting element covering layer material containing the aromatic amine compound, and an organic light-emitting element containing the aromatic amine compound. The organic light-emitting element achieves high light-emitting efficiency and color reproducibility. The organic light-emitting element can be used as organic EL display, backlight source for liquid crystal display, illumination, light source for measurement devices, indication board or identification lamp etc. The organic light-emitting element significantly improves light extraction efficiency and has superior color purity.
Thu, 03 Nov 2016 08:00:00 EDTAn organic light-emitting component includes a substrate on which a functional layer stack is applied, the stack including a first electrode, an organic functional layer stack thereover including an organic light-emitting layer and a translucent second electrode thereover, and a translucent halogen-containing thin-film encapsulation arrangement over the translucent second electrode, wherein a translucent protective layer having a refractive index of more than 1.6 is arranged directly on a translucent second electrode between the translucent second electrode and the thin-film encapsulation arrangement, and the thin-film encapsulation arrangement is arranged directly on the translucent protective layer.
Thu, 03 Nov 2016 08:00:00 EDTAn encapsulation structure of the display unit and a method of forming the same, mainly use the thin film encapsulation structure to hermetically protect the display unit (such as OLED display unit), that is sealing the display unit by inorganic thin film layer having the characteristics of transparency as well as containing moisture-resistance and oxygen-resistance; buffering the internal and external stresses of the thin film layers and restraining the falling off of the layers caused by the bending stress when forming flexible devices. Meanwhile, the bank features formed by multilayer stack can effectively inhibit the diffusion effect of inorganic coating and the increase of the number of side water retaining walls of thin film device can improve the effect of encapsulation, and the bank structures act as a support of the metal mask during the coating process to prevent the substrate from the damage caused by the metal mask.
Thu, 03 Nov 2016 08:00:00 EDTThe invention provides a display structure and manufacturing method of a display device, and relates to the field of display device technology. By forming a complex encapsulation film with the function of buffering and water-and-oxygen barrier on a display module directly, and attaching the cover on the complex encapsulation film, so as to ensure the sealing effect of the display module, and to efficiently prevent the display screen from breaking caused by the stress concentration generated by impact of external forces, thus the probability of breaking of display screen can be reduced effectively, and the structural strength of the display device as a whole is greatly improved.
Thu, 03 Nov 2016 08:00:00 EDTA thin film transistor array panel device comprises: a base substrate; a barrier layer disposed over the base substrate and comprising a plurality of transparent material layers; and an array of thin film transistors disposed over the barrier layer. A difference between a refractive index of the barrier layer and a refractive index of the base substrate may be within about 6%. The transparent material layers may be arranged such that the transparent material layers having compressive residual stress and the transparent material layers having tensile residual stress are alternately stacked. Each of the transparent material layers may comprise silicon oxynitride (SiON).
Thu, 03 Nov 2016 08:00:00 EDTA flexible display apparatus includes a flexible substrate, a display unit on the flexible substrate, a first encapsulation unit covering the display unit, defining a first through portion therethrough, and including a first organic layer, and a first inorganic layer on the first organic layer, and a first material in the first through portion that is different from a material of the first organic layer.
Thu, 03 Nov 2016 08:00:00 EDTA display module encapsulating structure and preparation method thereof, which relates to the field of display devices and can be applied to preparing AMOLED and other related display devices as described in the application, mainly use the thin film encapsulation structure to hermetically protect the display module (such as OLED display module), that is sealing the display module by inorganic thin film layer having the characteristics of transparency as well as containing moisture-resistance and oxygen-resistance; buffering the internal and external stresses of the thin film layers and restraining the falling off of the layers caused by the bending stress when preparing flexible devices. Meanwhile, the raised features formed by multilayer stack can effectively inhibit the diffusion effect of inorganic coating and increase the number of side water retaining walls of thin film device, therefore, effectively improve the encapsulating effect.
Thu, 03 Nov 2016 08:00:00 EDTA display module encapsulation structure and preparation method thereof, which relates to the field of display devices and can be applied in preparing AMOLED and other related display devices. The structure and method thereof mainly seals and protects the display module by utilizing the thin film encapsulation structure. That is to say, seal the display module by inorganic thin film layer which has the characteristics of transparency as well as water-resistance oxygen, buffer the internal and external stress of the thin film layer by preparing the organic module outside to the inorganic thin layer, and restrain the film layer falling off caused by the bending stress when making flexible devices. The thin film encapsulation instead of fit encapsulation can effectively improve the mechanical strength of the whole display device.
Thu, 03 Nov 2016 08:00:00 EDTAn organic light-emitting display apparatus includes: a substrate; an organic light-emitting device on the substrate; and an encapsulation layer including a first inorganic film covering the organic light-emitting device, an organic film on the first inorganic film, a second inorganic film between the first inorganic film and the organic film and having hydrophilicity, and a third inorganic film on the organic film. The second inorganic film may have a contact angle of 40° or less. A method of manufacturing an organic light-emitting display apparatus includes forming an organic light-emitting device on a substrate; forming a first inorganic film covering the organic light-emitting device; forming a second inorganic film having hydrophilicity on the first inorganic film; forming an organic film on the second inorganic film; and forming a third inorganic film on the organic film.
Thu, 03 Nov 2016 08:00:00 EDTA material for sealing a display apparatus, the material having an improved mechanical strength and improved flowability, an organic light-emitting display apparatus including the material, and a method of manufacturing the organic light-emitting display apparatus are provided. The organic light-emitting display apparatus includes a lower substrate having a display area and a peripheral area around the display area; a display unit on the display area of the lower substrate; an upper substrate on the display unit and facing the lower substrate; and a sealing member on the peripheral area of the lower substrate to adhere the lower substrate and the upper substrate together, the sealing member including a glass powder, a first filler including a ceramic material, and a second filler including iron oxide.
Thu, 03 Nov 2016 08:00:00 EDTAn organic light emitting display device may include a first auxiliary electrode, a first first-group first-color corresponding electrode, a second first-group first-color corresponding electrode, and a first group electrode. The second first-group first-color corresponding electrode is larger than the first first-group first-color corresponding electrode. The first group electrode overlaps both the first first-group first-color corresponding electrode and the second first-group first-color corresponding electrode. A first portion of the first group electrode directly contacts the first auxiliary electrode and is positioned closer to the first first-group first-color corresponding electrode than to the second first-group first-color corresponding electrode.
Thu, 03 Nov 2016 08:00:00 EDTA second electrode (130) is superimposed on a first electrode (110). An organic layer (120) is positioned between the first electrode (110) and the second electrode (130). Furthermore, the organic layer (120) includes a light emitting layer (123). Furthermore, the organic layer (120) includes an alkali-containing layer (which is an electron transporting layer (125) in an example in the present drawing, and is hereinafter described as the electron transporting layer (125)) between the light emitting layer (123) and the second electrode (130). The electron transporting layer (125) includes an alkali metal. In the electron transporting layer (125), a content of the alkali metal as an elemental substance is greater than the content of a compound of the alkali metal.
Thu, 03 Nov 2016 08:00:00 EDTAn object is to provide a novel organometallic complex. Another object is to provide an organometallic complex that can exhibit yellow to blue phosphorescence. A platinum complex with a tetracoordinate ligand including a phenothiazine skeleton or a phenoxazine skeleton is provided. In the ligand, nitrogen at the 10-position and carbon at the 2-position of the phenothiazine skeleton or the phenoxazine skeleton have a pyridyl group and a phenoxy group, respectively. A five-membered heteroaromatic residue is present at the 3-position of the phenoxy group. The five-membered heteroaromatic residue has two or three nitrogen atoms in its skeleton. Carbon at the 1-position of the phenothiazine skeleton or the phenoxazine skeleton and carbon at the 2-position of the phenoxy group are bonded to platinum, and nitrogen of the pyridyl group and nitrogen or carbene carbon of the five-membered heteroaromatic residue are coordinated to platinum.
Thu, 03 Nov 2016 08:00:00 EDTA light-emitting element of the present invention can have sufficiently high emission efficiency with a structure including a host material being able to remain chemically stable even if a phosphorescent compound having higher emission energy is used as a guest material. The relation between the relative emission intensity and the emission time of light emission obtained from the host material and the guest material contained in a light-emitting layer is represented by a multicomponent decay curve. The relative emission intensity of the slowest component of the multicomponent decay curve becomes 1/100 for a short time within a range where the slowest component is not interfered with by quenching of the host material (the emission time of the slowest component is preferably less than or equal to 15 μsec); thus, sufficiently high emission efficiency can be obtained.
Thu, 03 Nov 2016 08:00:00 EDTA fused fluoranthene compound which includes an indeno[3,2-b]fluoranthene skeleton having a hetero atom is a novel compound, which is useful as a material for organic electroluminescence devices for use in an organic electroluminescence device and an electronic equipment.
Thu, 03 Nov 2016 08:00:00 EDTAn organic light-emitting device includes: a first electrode; a second electrode facing the first electrode; and an organic layer between the first electrode and the second electrode, wherein the organic layer includes an emission layer including a compound represented by Formula 1: An organic light-emitting device using the compound of Formula 1 may have high efficiency, low voltage, high luminance, and long lifespan.
Thu, 03 Nov 2016 08:00:00 EDTA novel condensed cyclic compound and an organic light emitting device including the same are disclosed.
Thu, 03 Nov 2016 08:00:00 EDTThe disclosure provides a conjugated compound having phenoxathiinl, method for preparing the same and OLED. The conjugated compound has one of the following formulas: Different kinds of electron-rich conjugated aromatic units are reacted with intermediate having phenoxathiinl by Suzuki coupling, Buchwald-Hartwig coupling, or Cu-catalyzed amination of halogenated aromatic hydrocarbons for forming the conjugated compound having phenoxathiin. The prepared novel compound is fluorescent, so that it can be used as the material of light emitting layer of OLED devices.
Thu, 03 Nov 2016 08:00:00 EDTThe present disclosure provides an organic electroluminescent device including: an anode; a cathode; and one or more organic material layers interposed between the anode and cathode and selected from the group consisting of a hole injection layer, a hole transporting layer, a light emitting layer, an electron transporting layer, and an electron injection layer, and further including a lifetime enhancement layer (LEL) between the light emitting layer and the electron transporting layer.
Thu, 03 Nov 2016 08:00:00 EDTThe present invention discloses an organic electroluminescent device and a manufacturing method thereof. The host material of the light-emitting layer of the organic electroluminescent device is material in which the triplet state energy level of the CT excited state is higher than that of the n-π excited state by 0 to 0.3 eV; or the triplet state of the host material of the light-emitting layer is higher than that of the n-π excited state by more than 1.0 eV; in addition, the difference in energy level between the second triplet state of the n-π state and the first singlet state of the CT excited state is −0.1 to 0.1 eV; and the luminescent dye is a fluorescent dye. With regard to the organic electroluminescent device in the present invention, as new host material in the light-emitting layer is used and the host material has a donor group and an acceptor group, the triplet state in the light-emitting layer may be fully utilized to achieve a 100% light-emitting efficiency in the fluorescent device. Furthermore, no noble metal is required to be used, thus reducing the cost.
Thu, 03 Nov 2016 08:00:00 EDTAccording to one or more embodiments, an organic light-emitting device includes: a first electrode; a second electrode facing the first electrode; an emission layer between the first electrode and the second electrode; and a hole transport region between the first electrode and the emission layer. The hole transport region includes a first compound represented by Formula 1A and a second compound represented by Formula 1B:
Thu, 03 Nov 2016 08:00:00 EDTAccording to one or more embodiments, an organic light-emitting device includes: a first electrode; a second electrode; an emission layer between the first electrode and the second electrode; and a hole transport region between the first electrode and the emission layer. The hole transport region includes a first compound represented by Formula 1 and a second compound represented by Formula 2:
Thu, 03 Nov 2016 08:00:00 EDTAn organic light-emitting device includes a first electrode; a second electrode facing the first electrode; an emission layer between the first electrode and the second electrode; and a hole transport region between the first electrode and the emission layer, wherein the hole transport region includes a hole transport layer, and a hole auxiliary layer between the hole transport layer and the emission layer. The hole auxiliary layer includes a first compound represented by Formula 1, and the hole transport layer includes a second compound represented by Formula 2:
Thu, 03 Nov 2016 08:00:00 EDTAn organic light-emitting device including: a first electrode; a second electrode; an emission layer between the first electrode and the second electrode; and a hole transport region between the first electrode and the emission layer, wherein the hole transport region comprises a first compound represented by Formula 1 and a second compound represented by Formula 2: When the first compound represented by Formula 1 and the second compound represented by Formula 2 are used in the hole transport layer and the hole auxiliary layer, respectively, an organic light-emitting device may have improved driving voltage, efficiency, brightness, and lifespan characteristics.
Thu, 03 Nov 2016 08:00:00 EDTA compound represented by Formula 1 and an organic light-emitting device including the compound are disclosed, wherein descriptions of Formula 1 are provided in the detailed description in the present specification. An organic layer of the organic light-emitting device may include the compound represented by Formula 1. The compound represented by Formula 1 may be included in an emission layer of the organic layer.
Thu, 03 Nov 2016 08:00:00 EDTThe present invention discloses an organic material is represented by the following formula (1), the organic EL device employing the organic material as fluorescent emitting guest can display good performance like as lower driving voltage and power consumption, increasing efficiency and half-life time. wherein A, B ring, X, m, n, p and R1 to R6 are the same definition as described in the present invention.
Thu, 03 Nov 2016 08:00:00 EDTThe present invention relates to an electrically doped semiconducting material comprising at least one metallic element as n-dopant and at least one electron transport matrix compound comprising at least one phosphine oxide group, a process for its preparation, and an electronic device comprising the electrically doped semiconducting material.
Thu, 03 Nov 2016 08:00:00 EDTThe invention provides a conjugated compound containing a bis(phenylsulfonyl)benzene structure, a preparation method and an application thereof, the compound includes a chemical structure with one of structural general formulas as follows: the invention obtains a conjugated compound containing a bis(phenylsulfonyl)benzene structure by selecting multiple kinds of conjugated aromatic units to react with halogen-substituted bis(phenylsulfonyl)benzene in the manner of Suzuki coupling reaction, Buchwald-Hartwig coupling reaction or copper-catalyzed halogenated aromatic amination reaction. The novel compound prepared by the invention has the characteristic of fluorescence as well as a certain electrical conductivity, and thus can be applied to fabricate a light-emitting layer or an electron transport layer of an organic electroluminescent diode.
Thu, 03 Nov 2016 08:00:00 EDTA flexible organic light-emitting diode display and a method of manufacturing the same are disclosed. In one aspect, the display includes a substrate formed of a first material including a metal and an OLED formed over the substrate.
Thu, 03 Nov 2016 08:00:00 EDTResistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an area enclosed by the oxide material formed in the opening.
Thu, 03 Nov 2016 08:00:00 EDTA device includes a pillar-shaped insulating layer above a first pillar-shaped semiconductor layer. A resistance-changing film is around an upper portion of the pillar-shaped insulating layer and a lower electrode is around a lower portion of the pillar-shaped insulating layer and connected to the resistance-changing film. A reset gate insulating film surrounds the resistance-changing film, and a reset gate surrounds the reset gate insulating film.
Thu, 03 Nov 2016 08:00:00 EDTIn one embodiment, a magneto-resistive chip package includes a circuit board; a shielding body including a shielding base part positioned on the circuit board and a shielding intermediate part extending from one side of the shielding base part; a magneto-resistive chip positioned on the shielding base part and including a magneto-resistive cell array; an internal connection part electrically connecting the magneto-resistive chip to the circuit board; an encapsulation part encapsulating the magneto-resistive chip on the circuit board, and having an upper surface that is higher than an upper surface of the magneto-resistive chip; and a shielding cover positioned on the shielding intermediate part, and on the encapsulation part.
Thu, 03 Nov 2016 08:00:00 EDTA package includes a first lead electrode, a second lead electrode, and a resin molded body. The first lead electrode has a first upper surface and a first lower surface defining a depression and opposite to the first upper surface. The second lead electrode has a second upper surface and a second lower surface opposite to the second upper surface. The resin molded body defining a recess with a bottom surface including the first upper surface and the second upper surface, the resin molded body also covering the first lower surface and the second lower surface. The first electrode having a first region closer to the second lead electrode and a second region farther to the second lead electrode than the first region, and having a thickness smaller than a thickness of the first region due to the depression defined in the first lower surface.
Thu, 03 Nov 2016 08:00:00 EDTAn optoelectronic component includes a housing that includes a rectangular basic shape with four sides. The sides each merge into one another at a corner point. At least two carrier arms of two contact elements of a lead frame are guided to an edge of the housing. The two carrier arms are arranged on different sides of the housing. The two carrier arms are each at different spacings from the two corner points of the side on which the carrier arms are arranged. The spacings differ at least in the width of a carrier arm.
Thu, 03 Nov 2016 08:00:00 EDTAn LED package structure includes a multilayer circuit board, an LED chip, and a cover. The multilayer circuit board has a conductive layer, a first resin layer disposed on the conductive layer, and a first circuit layer disposed on the first resin layer. The first resin layer has a first opening, and a portion of the conductive layer is partially exposed from the first resin layer via the first opening such that a mounting region is exposed. The first circuit layer has a second opening, and the second opening exposes the mounting region. The LED chip is fixed on the mounting region by passing it through the first and second openings, and the LED chip is connected to the first circuit layer by wires. The cover is disposed on the first resin layer and covers the LED chip and the first circuit layer.
Thu, 03 Nov 2016 08:00:00 EDTAn LED package creates a narrow beam in a very compact package without use of a lens. A plastic is molded around a metal lead frame (12, 14) to form a molded cup (26), where the cup has parabolic walls extending from a bottom area of the cup to a top thereof. The lead frame forms a first set of electrodes exposed at the bottom area of the cup for electrically contacting a set of LED die electrodes (18, 20). The lead frame also forms a second set of electrodes outside of the cup for connection to a power supply. A reflective metal (28) is then deposited on the curved walls of the cup. An LED die (16) is mounted at the bottom area of the cup and electrically connected to the first set of electrodes. The cup is then partially filled with an encapsulant (64) containing a phosphor (66).
Thu, 03 Nov 2016 08:00:00 EDTA package, includes a cup-shaped resin component having a bottom surface and side walls that surround the bottom surface, an opening which is opened at an upper part of the side walls, a pair of leads exposed on part of the bottom surface, and a reflective film, the resin component having a 3-D shape defined by an X axis, a Y axis and a Z axis, the outer surface of the side walls that has a recess which is recessed in the Z axis direction and arranged in a position corresponding to the opening, and the reflective film being disposed in the recess.
Thu, 03 Nov 2016 08:00:00 EDTA silicone-grafted core-shell particle is described wherein the silicone-grafted core-shell particle comprises a core of an inorganic particle and a shell of a grafted poly(dimethylsiloxane) polymer formed from a bi-terminated poly(dimethylsiloxane) having reactive groups at each terminal end. The silicone-grafted core-shell particles may be dispersed in a polysiloxane polymer matrix and employed as an LED encapsulant.
Thu, 03 Nov 2016 08:00:00 EDTProvided are a light source circuit unit that improves light extraction efficiency, as well as an illuminator and a display that include such a light source circuit unit. The light source circuit unit includes: a circuit substrate having a wiring pattern on a surface thereof, the wiring pattern having light reflectivity, a circular pedestal provided on the circuit substrate, a water-repelling region provided at least from a peripheral edge portion of the pedestal to a part of a side face of the pedestal, and one or two or more light-emitting device chips mounted on the pedestal, and driven by a current that flows through the wiring pattern.
Thu, 03 Nov 2016 08:00:00 EDTA structure according to embodiments of the invention includes a light emitting device for emitting light having a first peak wavelength. A wavelength converting layer is disposed in a path of light emitted by the light emitting device. The wavelength converting layer absorbs light emitted by the light emitting device and emits light having a second peak wavelength. The wavelength converting layer includes a mixture of a wavelength converting material, a transparent material, and an adhesive material, wherein the adhesive material is no more than 15% of the weight of the wavelength converting layer.
Thu, 03 Nov 2016 08:00:00 EDTAn LED packaging structure comprises a silicon-based body and an LED chip. Discontinuous metal reflective layers are disposed on the obverse surface of the silicon-based body. A metal layer I and a metal layer II that are discontinuous are disposed in a silicon through hole. An LED chip electrode, a metal block/post, the metal reflective layer and the metal layer I are electrically connected. An LED chip electrode, a metal block/post, the metal reflective layer and the metal layer II are electrically connected. A metal layer III is located on a surface of an insulation layer II at the back of the silicon-based body and is located between the metal layer I and the metal layer II. According to the packaging structure, the LED packaging structure with omnidirectional light emission is obtained by means of a wafer level packaging technology; the LED packaging structure can reduce the thermal resistance, improve the reliability, enable the light emission angle not to be limited, and reduce design and manufacturing costs.
Thu, 03 Nov 2016 08:00:00 EDTAn optoelectric device can comprise a substrate and at least one junction configured to provide an active region within the substrate. Additionally, the device can comprise a metal-mesh semiconductor electrical contact structure attached to a surface of the substrate. The metal-mesh semiconductor electrical contact structure can further comprise a mesh line width, a mesh opening size, and a mesh thickness.
Thu, 03 Nov 2016 08:00:00 EDTAn optoelectronic device including semiconductor elements, each semiconductor element resting on a carrier through an aperture formed in a portion at least one first part of which is insulating and covers at least partially the carrier, the height of the aperture being larger than or equal to 100 nm and smaller than or equal to 3000 nm and the ratio of the height to the smallest diameter of the aperture being higher than or equal to 0.5 and lower than or equal to 10.
Thu, 03 Nov 2016 08:00:00 EDTA device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.
Thu, 03 Nov 2016 08:00:00 EDTThe disclosed light emitting device includes an intermediate layer interposed between the light emitting semiconductor structure and the substrate. The light emitting semiconductor structure includes a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer interposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, wherein the active layer has a multi quantum well structure including at least one period of a pair structure of a quantum barrier layer including AlxGa(1-x)N (0
Thu, 03 Nov 2016 08:00:00 EDTA light emitting device is provided. The light emitting device includes a substrate, an N type semiconductor layer formed on the substrate, an active layer, an electron-blocking layer, and a P type semiconductor layer formed on the electron-blocking layer. An N side electrode is formed on a first portion of the N type semiconductor layer, and the active layer is formed on a second portion of the N type semiconductor layer. The electron-blocking layer is a super lattice multi-layer structure formed on the active layer, the P type semiconductor layer is formed on the electron-blocking layer, and a P side electrode is formed on a portion of the P type semiconductor layer.
Thu, 03 Nov 2016 08:00:00 EDTA semiconductor device in an embodiment comprises a first chip in a first resin and a second resin covering the first resin. A first lead frame is in the first resin and has a first end portion extending through the second resin. A second end portion of the first lead frame terminates in the second resin. A second lead frame is spaced from the first lead frame in the first resin. The second lead frame has a first end portion in the first resin and a second end portion that terminates in the second resin. The first chip is disposed on the first end portion of the second lead frame, and a first bonding wire electrically connects the first chip to the first lead frame.
Thu, 03 Nov 2016 08:00:00 EDTA detector that includes an all-oxide, Schottky-type heterojunction. The “metal” side of the heterojunction is formed, for example, from a dysprosium (“Dy”) doped cadmium oxide (“CdO”) (i.e., CdO:Dy). The semiconductor side of the heterojunction is formed, for example, from cadmium magnesium oxide (“CdMgO”). On the metal side of the junction, “hot” electrons are created through the excitation of surface plasmon polaritons by infrared radiation. The hot electrons are able to cross the Schottky-type barrier of the heterojunction into the conduction band of the semiconductor where they can be detected. The working wavelength of infrared radiation that is being detected can be adjusted or tuned by modifying the Dy content of Dy-doped CdO. The height of the Schottky-type barrier can also be adjusted by modifying the composition of CdMgO, which allows for the optimization of the Schottky-type barrier height for a given working wavelength.
Thu, 03 Nov 2016 08:00:00 EDTA dielectric layer (2) is arranged on the main surface (10) of a semiconductor substrate (1), and a passivation layer (6) is arranged on the dielectric layer. A metal layer (3) is embedded in the dielectric layer above an opening (12) in the substrate, and a metallization (14) is arranged in the opening. The metallization contacts the metal layer and forms a through-substrate via to a rear surface (11) of the substrate. A layer or layer sequence (7, 8, 9) comprising at least one further layer is arranged on the passivation layer above the opening. In this way the bottom of the through-substrate via is stabilized. A plug (17) may additionally be arranged in the opening without filling the opening.
Thu, 03 Nov 2016 08:00:00 EDTAn optoelectronic device has a hybrid metal-dielectric optoelectronic interface including an array of nanoscale dielectric resonant elements (e.g., nanopillars), and a metal film disposed between the dielectric resonant elements and below a top surface of the resonant elements such that the dielectric resonant elements protrude through the metal film. The device may also include an anti-reflection coating. The device may further include a metal film layer on each of the dielectric resonant elements.
Thu, 03 Nov 2016 08:00:00 EDTAccording to one aspect, the invention relates to an element for quantum photodetection of an incident radiation in a spectral band centred around a central wavelength λ0, having a front surface intended for receiving said radiation, and including: a stack of layers of semiconductor material forming a PN or PIN junction and including at least one layer made of an absorbent semiconductor material having a cut-off wavelength λ0>λ0, the stack of layers of semiconductor material forming a resonant optical cavity; and a structure for coupling the incident radiation with the optical cavity such as to form a resonance at the central wavelength λ0 allowing the absorption of more than 80% in the layer of absorbent semiconductor material at said central wavelength, and an absence of resonance at the radiative wavelength λrad, wherein the radiative wavelength λrad is the wavelength for which, at operating temperature, the radiative recombination rate is the highest.
Thu, 03 Nov 2016 08:00:00 EDTA method to integrate a vertical IMPATT diode in a planar process.
Thu, 03 Nov 2016 08:00:00 EDTAn object is to improve reliability of a light-emitting device. A light-emitting device has a driver circuit portion including a transistor for a driver circuit and a pixel portion including a transistor for a pixel over one substrate. The transistor for the driver circuit and the transistor for the pixel are inverted staggered transistors each including an oxide semiconductor layer in contact with part of an oxide insulating layer. In the pixel portion, a color filter layer and a light-emitting element are provided over the oxide insulating layer. In the transistor for the driver circuit, a conductive layer overlapping with a gate electrode layer and the oxide semiconductor layer is provided over the oxide insulating layer. The gate electrode layer, a source electrode layer, and a drain electrode layer are formed using metal conductive films.
Thu, 03 Nov 2016 08:00:00 EDTA thin film transistor array panel, including a substrate; a gate electrode on the substrate; a semiconductor layer on the substrate; a gate insulating layer between the gate electrode and the semiconductor layer, the gate insulating layer including a first oxide insulating layer in contact with the semiconductor layer; a source electrode on the semiconductor layer; a drain electrode facing the source electrode; and a passivation layer covering the source electrode and the drain electrode, the passivation layer including a second oxide insulating layer in contact with the source electrode and the drain electrode, at least one of the first oxide insulating layer and the second oxide insulating layer having a varying hydrogen content distribution in a thickness direction.
Thu, 03 Nov 2016 08:00:00 EDTDisclosed is a semiconductor device using an oxide semiconductor, with stable electric characteristics and high reliability. In a process for manufacturing a bottom-gate transistor including an oxide semiconductor film, dehydration or dehydrogenation is performed by heat treatment and oxygen doping treatment is performed. The transistor including a gate insulating film subjected to the oxygen doping treatment and the oxide semiconductor film subjected to the dehydration or dehydrogenation by the heat treatment is a transistor having high reliability in which the amount of change in threshold voltage of the transistor by the bias-temperature stress (BT) test can be reduced.
Thu, 03 Nov 2016 08:00:00 EDTOxide layers which contain at least one metal element that is the same as that contained in an oxide semiconductor layer including a channel are formed in contact with the top surface and the bottom surface of the oxide semiconductor layer, whereby an interface state is not likely to be generated at each of an upper interface and a lower interface of the oxide semiconductor layer. Further, it is preferable that an oxide layer, which is formed using a material and a method similar to those of the oxide layers be formed over the oxide layers Accordingly, the interface state hardly influences the movement of electrons.
Thu, 03 Nov 2016 08:00:00 EDTA semiconductor device includes a semiconductor, a first conductor, a second conductor, a third conductor, a fourth conductor, a first insulator, a second insulator, a third insulator, and a fourth insulator. The first conductor and the semiconductor partly overlap with each other with the first insulator positioned therebetween. The second conductor and the third conductor have regions in contact with the semiconductor. The semiconductor has a region in contact with the second insulator. The fourth insulator has a first region and a second region. The first region is thicker than the second region. The first region has a region in contact with the second insulator. The second region has a region in contact with the third insulator. The fourth conductor and the second insulator partly overlap with each other with the fourth insulator positioned therebetween.
Thu, 03 Nov 2016 08:00:00 EDTA semiconductor structure includes a substrate and a first element disposed in the substrate and arranged along a first direction. The first element is made of a semiconductor oxide material. The semiconductor structure also includes a dielectric layer disposed on the first element, and a second element, disposed on the dielectric layer and arranged along the first direction. The second element is used as a gate of a transistor structure.
Thu, 03 Nov 2016 08:00:00 EDTA silicon germanium alloy is formed on sidewall surfaces of a silicon fin. An oxidation process or a thermal anneal is employed to convert a portion of the silicon fin into a silicon germanium alloy fin. In some embodiments, the silicon germanium alloy fin has a wide upper portion and a narrower lower portion. In such an embodiment, the wide upper portion has a greater germanium content than the narrower lower portion. In other embodiments, the silicon germanium alloy fin has a narrow upper portion and a wider lower portion. In this embodiment, the narrow upper portion of the silicon germanium alloy fin has a greater germanium content than the wider lower portion of the silicon germanium alloy fin.
Thu, 03 Nov 2016 08:00:00 EDTA semiconductor fin including a single crystalline semiconductor material is formed on a dielectric layer. A semiconductor shell including an epitaxial semiconductor material is formed on all physically exposed surfaces of the semiconductor fin by selective epitaxy, which deposits the semiconductor material only on semiconductor surfaces and not on dielectric surfaces. The epitaxial semiconductor material can be different from the single crystalline semiconductor material, and the semiconductor shell can be bilaterally strained due to lattice mismatch. A fin field effect transistor including a strained channel can be formed. Further, the semiconductor shell can advantageously alter properties of the source and drain regions, for example, by allowing incorporation of more dopants or by facilitating a metallization process.
Thu, 03 Nov 2016 08:00:00 EDTA semiconductor device includes a first gate stack and a second gate stack over a substrate, an isolation structure in the substrate, a first epitaxial (epi) material in the substrate between the first gate stack and the isolation structure, and a second epi material in the substrate between the first gate stack and the second gate stack. The first gate stack is between the isolation structure and the second gate stack. The first epi material includes a first upper surface having a first crystal plane. The second epi material includes a second upper surface having a second crystal plane and a third upper surface having a third crystal plane, and first crystal plane is different from both the second crystal plane and the third crystal plane.
Thu, 03 Nov 2016 08:00:00 EDTA semiconductor device includes a Fin FET transistor. The Fin FET transistor includes a first fin structure extending in a first direction, a gate stack and a source and a drain. The gate stack includes a gate electrode layer and a gate dielectric layer, covers a portion of the fin structure and extends in a second direction perpendicular to the first direction. Each of the source and drain includes a stressor layer disposed over the fin structure. The stressor layer applies a stress to a channel layer of the fin structure under the gate stack. The stressor layer penetrates under the gate stack. A vertical interface between the stressor layer and the fin structure under the gate stack in a third direction perpendicular to the first and second directions includes a flat area, and the flat area extends in the second direction and the third direction.
Thu, 03 Nov 2016 08:00:00 EDTA method of forming a semiconductor device includes forming a NMOS gate structure over a substrate. The method further includes forming an amorphized region in the substrate adjacent to the NMOS gate structure. The method also includes forming a lightly doped source/drain (LDD) region in the amorphized region. The method further includes depositing a stress film over the NMOS gate structure, performing an annealing process, and removing the stress film.
Thu, 03 Nov 2016 08:00:00 EDTA semiconductor device includes an active pattern protruding from a substrate and extending in a first direction, first and second gate electrodes intersecting the active pattern in a second direction intersecting the first direction, and a source/drain region disposed on the active pattern between the first and second gate electrodes. The source/drain region includes a first part adjacent to an uppermost surface of the active pattern and provided at a level lower than the uppermost surface of the active pattern, and a second part disposed under the first part so as to be in contact with the first part. A width of the first part along the first direction decreases in a direction away from the substrate, and a width of the second part along the first direction increases in a direction away from the substrate.
Thu, 03 Nov 2016 08:00:00 EDTThe present disclosure provides N-type fin field-effect transistors and fabrication methods thereof. A method for fabricating an N-type fin field-effect transistor includes providing a semiconductor substrate; forming at least one fin having a first side surface and a second side surface over the semiconductor substrate; forming a gate structure crossing over the fin over the semiconductor substrate; performing an ion implantation process on one of the first side surface and the second side surface of the fin at two sides of the gate structure; performing a thermal annealing process to cause doping ions to diffuse to the other one of the first side surface and the second side surface of the fin; and forming a source region and a drain region on the fin at the two sides of the gate structure, respectively.
Thu, 03 Nov 2016 08:00:00 EDTA semiconductor device includes a first pattern on a first active region, a second pattern on a second active region, and a third pattern on a third active region. The first pattern is spaced from the second pattern by a first interval corresponding to the width of a first recess between the first and second active regions. The second pattern is spaced from the third pattern by a second interval corresponding to the width of a second recess between the second and third active regions. The first, second, and third patterns includes gate patterns, and the first and second recesses include semiconductor material with a conductivity type different from the active regions. The semiconductor material in one recess extends higher than the semiconductor material in the other recess. The first, second, and third patterns have the same width, and the first and second recesses have different depths.
Thu, 03 Nov 2016 08:00:00 EDTA semiconductor device includes an electrical device and has an output capacitance characteristic with at least one output capacitance maximum located at a voltage larger than 5% of a breakdown voltage of the semiconductor device. The output capacitance maximum is larger than 1.2 times an output capacitance at an output capacitance minimum located at a voltage between the voltage at the output capacitance maximum and 5% of a breakdown voltage of the semiconductor device.
Thu, 03 Nov 2016 08:00:00 EDTA super-junction semiconductor device includes a junction termination area at a first surface of a semiconductor body and at least partly surrounding an active cell area. An inner part of the junction termination area is arranged between an outer part of the junction termination area and the active cell area. A charge compensation device structure includes first regions of a first conductivity type and second regions of a second conductivity type disposed alternately along a first lateral direction. First surface areas correspond to a projection of the first regions onto the first surface, and second surface areas correspond to a projection of the second regions onto the first surface. The super-junction semiconductor device further includes at least one of a first junction termination extension structure and a second junction termination extension structure.
Thu, 03 Nov 2016 08:00:00 EDTA semiconductor device includes compensation structures that extend from a first surface into a semiconductor portion. Sections of the semiconductor portion between neighboring ones of the compensation structures form semiconductor mesas. A field dielectric separating a field electrode in the compensation structures from the semiconductor portion includes a thermally grown portion, which directly adjoins the semiconductor portion. A not fully densified deposited portion of the field dielectric has a lower density than the thermally grown portion.
Thu, 03 Nov 2016 08:00:00 EDTA field effect transistor includes: a semiconductor substrate having a main surface; a plurality of source electrodes and a plurality of drain electrodes alternately disposed and ohmic-connected with the main surface of the semiconductor substrate; a plurality of gate electrodes Schottky-connected with the main surface of the semiconductor substrate and respectively disposed between the plurality of source electrodes and the plurality of drain electrodes; and a Schottky electrode Schottky-connected with the main surface of the semiconductor substrate, wherein each of the plurality of drain electrodes has first and second portions separated from each other, a sum of widths of the first and second portions of each drain electrode is smaller than a width of one source electrode, the Schottky electrode is disposed between the first portion and the second portion of the drain electrode.
Thu, 03 Nov 2016 08:00:00 EDTA method of manufacturing a flexible device including a two-dimensional (2D) material, e.g., graphene, includes forming a dielectric layer on a first substrate, forming a two-dimensional (2D) material layer on the dielectric layer; forming a pattern in the 2D material layer, forming a second substrate on the dielectric layer and the 2D material layer, the first substrate including a flexible material, removing the first substrate, and forming a source electrode, a drain electrode, and a gate electrode on the dielectric layer.
Thu, 03 Nov 2016 08:00:00 EDTAn electronic device can include a bidirectional HEMT. In an aspect, a packaged electronic device can include the bidirectional HEMT can be part of a die having a die substrate connection that is configured to be at a fixed voltage, electrically connected to drain/source or source/drain depending on current flow through the bidirectional HEMT, or electrically float. In another aspect, the electronic device can include Kelvin connections on both the drain/source and source/drain side of the circuit. In a further embodiment, a circuit can include the bidirectional HEMT, switch transistors, and diodes with breakdown voltages to limit voltage swings at the drain/source and source/drain of the switch transistors.
Thu, 03 Nov 2016 08:00:00 EDTA symmetrically-bidirectional power bipolar transistor having, on both surfaces of a semiconductor die, an n-type emitter/collector region which is completely surrounded by a first recessed field plate, which is itself completely surrounded by a p-type region including p+ contact areas. All of the p-type region is preferably bordered and surrounded by a second recessed field plate trench. The second recessed field plate trench is itself surrounded by an n-type region which is wholly or partially made of the same diffusion as the emitter/collector regions, but which is not connected to the metallization which connects the emitter/collector regions to extermal terminals.
Thu, 03 Nov 2016 08:00:00 EDTA bidirectional IGBT device, including a cellular structure including: two MOS structures, a substrate drift layer, two highly doped buried layers operating for carrier storage or field stop, two metal electrodes, and isolating dielectrics. Each MOS structure includes: a body region, a heavily doped source region, a body contact region, and a gate structure. Each gate structure includes: a gate dielectric and a gate conductive material. The two MOS structures are symmetrically disposed on the top surface and the back surface of the substrate drift layer. The heavily doped source region and the body contact region are disposed in the body region and independent from each other, and both surfaces of the heavily doped source region and the body contact region are connected to each of the two metal electrodes. The gate dielectric separates the gate conductive material from a channel region of each of the MOS structures.
Thu, 03 Nov 2016 08:00:00 EDTA heterojunction bipolar transistor, comprising an elongated base mesa, an “H” shaped emitter, two base electrodes, an elongated collector, and two elongated collector electrodes. The “H” shaped emitter is formed on the base mesa and has two recesses respectively on two opposite sides of the “H” shape, and the emitter has two elongated emitter electrodes formed on the “H” shaped emitter. The two base electrodes are formed on the base mesa respectively at the two recesses of the “H” shaped emitter, and each of the base electrodes has a base via hole at or near the center of the base mesa. The elongated collector is formed below the base mesa. The two elongated collector electrodes are formed on the collector respectively at two opposite sides of the base mesa.
Thu, 03 Nov 2016 08:00:00 EDTA lateral bipolar junction transistor including a base region on a dielectric substrate layer. The base region includes a layered stack of alternating material layers of a first lattice dimension semiconductor material and a second lattice dimension semiconductor material. The first lattice dimension semiconductor material is different from the second lattice dimension semiconductor material to provide a strained base region. A collector region is present on the dielectric substrate layer in contact with a first side of the base region. An emitter region is present on the dielectric substrate in contact with a second side of the base region that is opposite the first side of the base region.
Thu, 03 Nov 2016 08:00:00 EDTTunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.
Thu, 03 Nov 2016 08:00:00 EDTA tunneling field effect transistor is formed from a fin of semiconductor material on a support substrate. The fin of semiconductor material includes a source region, a drain region and a channel region between the source region and drain region. A gate electrode straddles over the fin at the channel region. Sidewall spacers are provided on each side of the gate electrode. The source of the transistor is made from an epitaxial germanium content source region grown from the source region of the fin and doped with a first conductivity type. The drain of the transistor is made from an epitaxial silicon content drain region grown from the drain region of the fin and doped with a second conductivity type.
Thu, 03 Nov 2016 08:00:00 EDTA method of forming a field effect transistor is provided. The method of forming a field effect transistor may include forming a dummy gate perpendicular to and covering a channel region of a semiconductor fin, such that a source drain region of the semiconductor fin remains uncovered, depositing a metal layer above and in direct contact with a sidewall of the dummy gate, and above and in direct contact with a top and a sidewall of the source drain region, and forming a metal silicide source drain in the source drain region by annealing the metal layer and the semiconductor fin, such that the metal silicide source drain overlaps the dummy gate.
Thu, 03 Nov 2016 08:00:00 EDTA semiconductor structure includes a semiconductor substrate, n-type source and drain stressors, and a gate stack. The semiconductor substrate has source and drain recesses therein. The n-type source and drain stressors are respectively present in the source and drain recesses. At least one of the n-type source and drain stressors has a hydrogen terminated surface. A gate stack is present on the semiconductor substrate and between the n-type source and drain stressors.
Thu, 03 Nov 2016 08:00:00 EDTBuffer layers on gates and methods of forming such are described. According to a method embodiment, a gate structure is formed. The gate structure includes a gate dielectric over a substrate, a work function tuning layer over the gate dielectric, and a metal-containing material over the work function tuning layer. A buffer layer is formed on the metal-containing material. A dielectric material is formed on the buffer layer. According to a structure embodiment, a gate structure includes a high-k gate dielectric and a metal gate electrode. A buffer layer is on the metal gate electrode. A dielectric cap is on the buffer layer. An inter-layer dielectric is over the substrate and around the gate structure. A top surface of the inter-layer dielectric is co-planar with a top surface of the dielectric cap.
Thu, 03 Nov 2016 08:00:00 EDTA method of producing a semiconductor device is presented. The method comprises: providing a semiconductor substrate having a surface; epitaxially growing, along a vertical direction (Z) perpendicular to the surface, a back side emitter layer on top of the surface, wherein the back side emitter layer has dopants of a first conductivity type or dopants of a second conductivity type complementary to the first conductivity type; epitaxially growing, along the vertical direction (Z), a drift layer having dopants of the first conductivity type above the back side emitter layer, wherein a dopant concentration of the back side emitter layer is higher than a dopant concentration of the drift layer; and creating, either within or on top of the drift layer, a body region having dopants of the second conductivity type, a transition between the body region and the drift layer forming a pn-junction (Zpn). Epitaxially growing the drift layer includes creating, within the drift layer, a dopant concentration profile (P) of dopants of the first conductivity type along the vertical direction (Z), the dopant concentration profile (P) in the drift layer exhibiting a variation of a concentration of dopants of the first conductivity type along the vertical direction (Z).
Thu, 03 Nov 2016 08:00:00 EDTGate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a first metal over the work function tuning layer, an adhesion layer over the first metal, and a second metal over the adhesion layer. In some embodiments, the adhesion layer can include an alloy of the first and second metals, and may be formed by annealing the first and second metals. In other embodiments, the adhesion layer can include an oxide of at least one of the first and/or second metal, and may be formed at least in part by exposing the first metal to an oxygen-containing plasma or to a natural environment.
Thu, 03 Nov 2016 08:00:00 EDTDisclosed herein is a thin film transistor array panel, including: an insulating substrate; a gate electrode formed on the insulating substrate; a gate insulating layer formed on the gate electrode; a semiconductor layer formed on the gate insulating layer; a source electrode and a drain electrode formed on the semiconductor layer and the gate insulating layer and facing each other; and a pixel electrode connected to the drain electrode and applied with a voltage from the drain electrode, wherein a thickness of the gate insulating layer which overlaps the drain electrode but does not overlap the semiconductor layer is formed to be thinner than that which overlaps the semiconductor.
Thu, 03 Nov 2016 08:00:00 EDTThis invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
Thu, 03 Nov 2016 08:00:00 EDTA semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure on the substrate; an interlayer dielectric (ILD) around the gate structure; a first contact plug in the ILD layer; a second dielectric layer on the ILD layer; a second contact plug in the second dielectric layer and electrically connected to the first contact plug; and a spacer between the second contact plug and the second dielectric layer.
Thu, 03 Nov 2016 08:00:00 EDTA semiconductor device, includes an n-type semiconductor layer provided with a first semiconductor layer with a low electron carrier concentration and a second semiconductor layer with a high electron carrier concentration, an electrode that is in Schottky-contact with a surface of the first semiconductor layer, and an ohmic electrode formed on a surface of the second semiconductor layer. The n-type semiconductor layer is formed of a Ga2O3-based single crystal. The first semiconductor layer has an electron carrier concentration Nd based on reverse withstand voltage VRM and electric field-breakdown strength Em of the Ga2O3-based single crystal.
Thu, 03 Nov 2016 08:00:00 EDTA lateral semiconductor device and/or design including a space-charge generating layer and an electrode or a set of electrodes located on an opposite side of a device channel as contacts to the device channel is provided. The space-charge generating layer is configured to form a space-charge region to at least partially deplete the device channel in response to an operating voltage being applied to the contacts to the device channel.
Thu, 03 Nov 2016 08:00:00 EDTA method for manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is prepared. A first heating step of heating the silicon carbide substrate in an atmosphere of oxygen is performed. A second heating step of heating the silicon carbide substrate to a temperature of 1300° C. or more and 1500° C. or less in an atmosphere of gas containing nitrogen atoms or phosphorus atoms is performed after the first heating step. A third heating step of heating the silicon carbide substrate in an atmosphere of a first inert gas is performed after the second heating step. Thus, the silicon carbide semiconductor device in which threshold voltage variation is small, and a method for manufacturing the same can be provided.
Thu, 03 Nov 2016 08:00:00 EDTA semiconductor device comprises a field effect transistor in a semiconductor substrate having a first main surface. The field effect transistor comprises a source region, a drain region, a body region, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel formed in the body region, and the gate electrode is disposed in gate trenches. The body region is disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The body region has a shape of a ridge extending along the first direction, the body region being adjacent to the source region and the drain region. The semiconductor device further comprises a source contact and a body contact, the source contact being electrically connected to a source terminal, the body contact being electrically connected to the source contact and to the body region.
Thu, 03 Nov 2016 08:00:00 EDTA fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of the top surface and the two opposed side surfaces, and a gate electrode covering at least a portion of the gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.
Thu, 03 Nov 2016 08:00:00 EDTTechniques in fabricating a fin field-effect transistor (FinFET) include providing a substrate having a fin structure and forming an isolation region having a top surface with a first surface profile. A dopant species is implanted using a tilt angle to edge portions of the top surface. The edge portions are then removed using an etch process. In this respect, the isolation region is modified to have a second surface profile based on an etching rate that is greater than an etching rate used at other portions of the top surface. The second surface profile has a step height that is smaller than a step height corresponding to the first surface profile. The tilt implantation and etching process can be performed before a gate structure is formed, after the gate structure is formed but before the fin structure is recessed, or after the fin structure is recessed.
Thu, 03 Nov 2016 08:00:00 EDTA method for producing fin structures, using Directed Self Assembly (DSA) lithographic patterning, in an area of a semiconductor substrate includes providing a semiconductor substrate covered with a shallow trench isolation (STI) layer stack on a side thereof; defining a fin area on that side of the substrate by performing a lithographic patterning step other than DSA, wherein the fin structures will be produced in the fin area; and producing the fin structures in the semiconductor substrate within the fin area according to a predetermined fin pattern using DSA lithographic patterning. The disclosure also relates to associated semiconductor structures.
Thu, 03 Nov 2016 08:00:00 EDTThe disclosure describes a tunneling field effect transistor having an overlapping structure between the source and drain regions providing a greater tunneling area. The source or drain region may be a doped region in a semi-conductive substrate. The other source or drain region may be formed by epitaxial deposition over the doped region. The gate is formed over the epitaxial region where the doped and epitaxial regions overlap. The doped region may be formed in a fin structure with the epitaxial region and gate being formed on the top and sides of the fin.
Thu, 03 Nov 2016 08:00:00 EDTThe invention relates to transferring, in one exposure, a single-mask feature to form two features on an underlying material. Specifically, a doubled walled structure (i.e. a center opening flanked by adjacent openings) is formed. Advantageously, the openings may be sub-resolution openings. The center opening may be a line flanked by two other lines. The center opening may be circular and surrounded by an outer ring, thus forming a double wall ring structure. In an electronic fuse embodiment, the double wall ring structure is a via filled with a conductor that contacts a lower and upper level metal. In deep trench embodiment, the double wall ring structure is a deep trench in a semiconductor substrate filled with insulating material. In such a way the surface area of the trench is increased thereby increasing capacitance.
Thu, 03 Nov 2016 08:00:00 EDTAn apparatus comprising a channel layer, a first layer, a hole barrier layer and a second layer is disclosed. The channel layer may be configured to carry a drain current in response to a voltage at a gate node. The first layer may be between the channel layer and the gate node. The first layer generally has a first bandgap. The hole barrier layer may be in contact with the first layer. The hole barrier layer generally has a second bandgap that (i) forms a valance band offset relative to the first bandgap and (ii) is configured to impede holes generated in one or more of the channel layer and the first layer from reaching the gate node. The gate node may be in contact with the second layer. The apparatus generally comprises a field effect transistor.
Thu, 03 Nov 2016 08:00:00 EDTIn one embodiment, a method for making a 3D Metal-Insulator-Metal (MIM) capacitor includes providing a substrate having a surface, forming an array of upstanding rods or ridges on the surface, depositing a first layer of an electroconductor on the surface and the array of rods or ridges, coating the first electroconductive layer with a layer of a dielectric, and depositing a second layer of an electroconductor on the dielectric layer. In some embodiments, the array of rods or ridges can be made of a photoresist material, and in others, can comprise bonded wires.