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NANOPARTICULATE ENCAPSULATION BARRIER STACK

Thu, 06 Apr 2017 08:00:00 EDT

A barrier stack for encapsulating a moisture and/or oxygen sensitive electronic device is provided. The barrier stack comprises a multilayer film having at least one barrier layer having low moisture and/or oxygen permeability, and at least one sealing layer arranged to be in contact with a surface of the barrier layer, wherein the sealing material comprises reactive nanoparticles capable of interacting with moisture and/or oxygen, thereby retarding the permeation of moisture and/or oxygen through defects present in the barrier layer.



DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

Thu, 06 Apr 2017 08:00:00 EDT

A display apparatus includes a substrate, a display element disposed on the substrate, a first inorganic film layer disposed on the display element, a first organic film layer disposed on the first inorganic film layer, a second organic film layer disposed on the first organic film layer and including a wrinkled upper surface, and a second inorganic film layer disposed on the second organic film layer and including a shape corresponding to the wrinkled upper surface of the second organic film layer.



DISPLAY APPARATUS

Thu, 06 Apr 2017 08:00:00 EDT

A display apparatus includes: a display substrate; a display on the display substrate, the display comprising a display device; a sealing substrate on the display substrate; a sealing member bonding the display substrate and the sealing substrate, the sealing member surrounding the display; a first metal line below the sealing member and surrounding the display; a second metal line on the display substrate and spaced apart from the first metal line; and one or more connectors connecting the first metal line and the second metal line with each other.



ORGANIC EL ELEMENT AND METHOD FOR MANUFACTURING SAME

Thu, 06 Apr 2017 08:00:00 EDT

In an organic EL element equipped with an anode, a cathode, a luminescent layer provided between the anode and the cathode, a hole transport layer provided between the anode and the luminescent layer, and an electron transport layer provided between the cathode and the luminescent layer, the cathode is composed of a reflecting electrode. The electron transport layer is composed of a doped electron transport layer to which an n-type dopant material is added and a non-doped electron transport layer to which an n-type dopant material is not added. A first reflection surface that reflects light from the luminescent layer is provided at an interface between the doped electron transport layer and the non-doped electron transport layer.



THIN FILM TRANSISTOR, METHOD OF MANUFACTURING SAME, AND ELECTRONIC DEVICE INCLUDING THIN SAME

Thu, 06 Apr 2017 08:00:00 EDT

A thin film transistor includes a gate electrode, a semiconductor overlapping the gate electrode, a gate insulator between the gate electrode and the semiconductor, and a source electrode and a drain electrode electrically connected to the semiconductor, wherein the gate insulator includes an inorganic insulation layer facing the gate electrode and an organic insulation layer facing the semiconductor. A method of manufacturing the thin film transistor and an electronic device including the thin film transistor are provided.



POLAR ELASTOMERS FOR HIGH PERFORMANCE ELECTRONIC AND OPTOELECTRONIC DEVICES

Thu, 06 Apr 2017 08:00:00 EDT

An electronic or optoelectronic device includes: (1) a semiconductor layer; (2) a pair of electrodes electrically coupled to the semiconductor layer; and (3) a dielectric layer in contact with the semiconductor layer and including a polar elastomer, where the elastomer has a glass transition temperature Tg that is no greater than 25° C.



ORGANIC ELECTROLUMINESCENT MATERIALS AND DEVICES

Thu, 06 Apr 2017 08:00:00 EDT

Ir phenyl parazole complexes substituted with strong electron withdrawing group such as cyano group resulted in enhancing the metal to ligand charge transfer (MLCT) which in turn resulted in enhanced emission efficiency and red shifted emission.



Organic Electroluminescent Materials and Devices

Thu, 06 Apr 2017 08:00:00 EDT

This invention discloses iridium complexes with ligands based on a phenyl quinoline backbone with at least a double substitution on the quinoline moiety. These complexes can be used as phosphorescent emitters in OLEDs.



ORGANOMETALLIC COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME

Thu, 06 Apr 2017 08:00:00 EDT

An organometallic compound represented by Formula 1: wherein, in Formula 1, b18, A11, L11, M, m, R18, and X11 to X17 are the same as described in the specification.



ORGANIC ELECTROLUMINESCENCE ELEMENT

Thu, 06 Apr 2017 08:00:00 EDT

An organic electroluminescence element comprising: an anode layer, a cathode layer, and an organic luminescence layer therebetween, the organic luminescence layer having a carbazole derivative with a glass-transition temperature of 110° C. or higher, and a phosphorescent dopant. This structure makes it possible to provide an organic electroluminescence element which can make use of the triplet exciton state of the carbazole derivative even at room temperature and which has a practical life and superior heat-resistance.



MULTI-COMPONENT HOST MATERIAL AND AN ORGANIC ELECTROLUMINESCENCE DEVICE COMPRISING THE SAME

Thu, 06 Apr 2017 08:00:00 EDT

The present invention relates to a multi-component host material and an organic electroluminescent device comprising the same. By comprising a specific combination of the multi-component host compounds, the organic electroluminescent device according to the present invention can provide high luminous efficiency and excellent lifespan characteristics.



ORGANIC ELECTROLUMINESCENT MATERIALS AND DEVICES

Thu, 06 Apr 2017 08:00:00 EDT

This invention relates to the development of heterocyclic materials with high triplet excitation energy, which can be used as host materials in electroluminescent devices such as a PHOLED. The materials improve the performance of such devices by enhancing the lifetime and efficiency of the device when the newly developed heterocyclic materials are utilized as a host.



ORGANIC ELECTROLUMINESCENT DEVICE AND DISPLAY INCLUDING THE SAME

Thu, 06 Apr 2017 08:00:00 EDT

An organic electroluminescent device and display, the device including a first electrode; a second electrode on the first electrode; an emission layer between the first and second electrodes; and an electron transport layer between the emission layer and the second electrode, the electron transport layer including a first electron transport layer on the emission layer; a second electron transport layer on the first electron transport layer; and a third electron transport layer on the second electron transport layer, wherein the first electron transport layer includes a first electron transport material, the second electron transport layer includes the first electron transport material, a second electron transport material, and a third electron transport material, the third electron transport layer includes the second electron transport material and the third electron transport material, and the first, second, and third electron transport materials are different from one another.



CONDENSED CYCLIC COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME

Thu, 06 Apr 2017 08:00:00 EDT

A condensed cyclic compound represented by Formula 1: wherein in Formula 1, Ar1 and R1 to R8 are the same as described in the specification.



COMPOSITION FOR ORGANIC OPTOELECTRIC DEVICE, ORGANIC OPTOELECTRIC DEVICE AND DISPLAY DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

A composition for an organic optoelectronic device includes at least one first compound represented by Chemical Formula 1, at least one second compound of a compound represented by Chemical Formula 2 and a compound consisting of a combination of a moiety represented by Chemical Formula 3 and a moiety represented by Chemical Formula 4, and at least one third compound of a compound represented by Chemical Formula 5 and a compound consisting of a combination of a moiety represented by Chemical Formula 6 and a moiety represented by Chemical Formula 7, an organic optoelectronic device includes the same, and a display device includes the organic optoelectronic device. Chemical Formulae 1 to 7 are the same as described in the detailed description.



HETEROCYCLIC COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE COMPRISING SAME

Thu, 06 Apr 2017 08:00:00 EDT

The present specification provides a hetero-cyclic compound and an organic light emitting device comprising the same.



Anthracene Derivative, Light-Emitting Element Using the Same, and Light-Emitting Device Using the Same

Thu, 06 Apr 2017 08:00:00 EDT

It is an object of the present invention to provide a light emitting element, which is resistant to repetition of an oxidation reaction. It is another object of the invention to provide a light emitting element, which is resistant to repetition of a reduction reaction. An anthracene derivative is represented by a general formula (1). In the general formula (1), R1 represents hydrogen or an alkyl group having 1 to 4 carbon atoms, R2 represents any one of hydrogen, an alkyl group having 1 to 4 carbon atoms and an aryl group having 6 to 12 carbon atoms, R3 represents any one of hydrogen, an alkyl group having 1 to 4 carbon atoms, and an aryl group having 6 to 12 carbon atoms, Ph1 represents a phenyl group, and X1 represents an arylene group having 6 to 15 carbon atoms.



DISPLAY APPARATUS

Thu, 06 Apr 2017 08:00:00 EDT

Exemplary embodiments of the inventive concept provide is a display apparatus. The display apparatus includes a display panel having a signal pad part including signal pads, impression pads, resistance measurement pads, and alignment pads. The display apparatus also includes a flexible circuit board having a connection pad part including first, second, third, and fourth pads which respectively correspond to the signal, impression, resistance measurement, and alignment pads. The signal, impression, and the resistance measurement pads are arranged along a first direction with a first gap therebetween, and the first, second, and third pads are arranged along the first direction with a second gap therebetween, the second gap being less than the first gap.



Organic Electroluminescent Element, Compound and Material For Organic Electroluminescent Element Capable of Being Used Therefor, Light Emitting Device, Display Device, and Illumination Device, Each Using The Element

Thu, 06 Apr 2017 08:00:00 EDT

An organic electroluminescent element including a substrate, a pair of electrodes including an anode and a cathode, disposed on the substrate, and at least one layer of organic layers including a light emitting layer, disposed between the electrodes, in which at least one of the organic layers contains a compound represented by the following general formula: (R1 to R18 each independently represent a hydrogen atom or a substituent, and at least one of R1 to R8 and R10 to R17 represents -L-NR19R20 (R19 and R20 each independently represent any of an alkyl group, an aryl group, a heteroaryl group. R19 and R20 may be combined to each other to form a ring. L represents a single bond or a divalent linking group). X1 to X18 each independently represent a carbon atom or a nitrogen atom, and when X1 to X18 represent nitrogen atoms, R1 to R18 for bonding do not present.)



Logic Compatible RRAM Structure and Process

Thu, 06 Apr 2017 08:00:00 EDT

A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.



SEMICONDUCTOR MEMORY DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

A semiconductor memory device according to an embodiment includes: a plurality of first conductive lines stacked in a first direction above a semiconductor substrate and extending in a second direction; a second conductive line extending in the first direction; semiconductor layers arranged between the first conductive lines and the second conductive line and extending in the first direction; a conductive layer in contact with a bottom surface of the semiconductor layer with a first impurity of a first conductivity type; and variable resistance films arranged at intersections between the first conductive lines and the semiconductor layer, the semiconductor layer having a first semiconductor part arranged from the bottom surface of the semiconductor layer to a position equal to or lower than a bottom surface of the first conductive line at a lowermost layer in the first direction with a second impurity of a second conductivity type.



DOUBLE SPIN FILTER TUNNEL JUNCTION

Thu, 06 Apr 2017 08:00:00 EDT

A memory device that includes a first magnetic insulating tunnel barrier reference layer present on a first non-magnetic metal electrode, and a free magnetic metal layer present on the first magnetic insulating tunnel barrier reference layer. A second magnetic insulating tunnel barrier reference layer may be present on the free magnetic metal layer, and a second non-magnetic metal electrode may be present on the second magnetic insulating tunnel barrier. The first and second magnetic insulating tunnel barrier reference layers are arranged so that their magnetizations are aligned to be anti-parallel.



SEMICONDUCTOR DEVICE HAVING MAGNETIC TUNNEL JUNCTION STRUCTURE AND METHOD OF FORMING THE SAME

Thu, 06 Apr 2017 08:00:00 EDT

A semiconductor device includes a magnetic tunnel junction structure on a lower electrode, an intermediate electrode on the magnetic tunnel junction structure, and an upper electrode on the intermediate electrode, wherein the intermediate electrode includes a lower portion and an upper portion having a side surface profile different from that of the lower portion.



LIGHT EMITTING DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

Disclosed herein is a light emitting device manufactured by separating a growth substrate in a wafer level. The light emitting device includes: a base; a light emitting structure disposed on the base; and a plurality of second contact electrodes disposed between the base and the light emitting structure, wherein the base includes at least two bulk electrodes electrically connected to the light emitting structure and an insulation support disposed between the bulk electrodes and enclosing the bulk electrodes, the insulation support and the bulk electrodes each including concave parts and convex parts engaged with each other on surfaces facing each other, and the convex parts including a section in which a width thereof is changed in a protrusion direction.



LOW OPTICAL LOSS FLIP CHIP SOLID STATE LIGHTING DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

Flip chip LEDs incorporate multi-layer reflectors and light transmissive substrates patterned along an internal surface adjacent to semiconductor layers. A multi-layer reflector may include a metal layer and a dielectric layer containing conductive vias. Portions of a multi-layer reflector may wrap around a LED mesa including an active region, while being covered with passivation material. A substrate patterned along an internal surface together with a multi-layer reflector enables reduction of optical losses. A light transmissive fillet material proximate to edge emitting surfaces of an emitter chip may enable adequate coverage with lumiphoric material. An emitter chip may be elevated with increased thickness of solder material and/or contacts, and may reduce luminous flux loss when reflective materials are present on a submount. Methods for coating emitter chips with lumiphoric material include one or more of angled spray coating, fillet formation prior to spray coating, stencil island coating, and releasable tape coating.



DISPLAY CONTRAST

Thu, 06 Apr 2017 08:00:00 EDT

Display devices with improved display contrast and methods of manufacturing the display devices. Some embodiments include a method of manufacturing a light emitting diode (LED) array. The method includes forming two mesa areas on a substrate, where a trench is defined between the two mesa areas. A pixel and a N-bus formation is formed on each of the two mesa areas to create a first LED and a second LED separated by the trench between the two mesa areas. At least a portion of the trench is filled with a non-transparent or substantially non-transparent polymeric material that absorbs light emitted from the first and second LEDs.



LIGHT EMITTING DEVICE WITH BEVELED REFLECTOR AND MANUFACTURING METHOD OF THE SAME

Thu, 06 Apr 2017 08:00:00 EDT

A light emitting device, including an LED semiconductor die, a photoluminescent structure and a reflector, is disclosed. The photoluminescent structure with a beveled edge surface is disposed on top of the LED semiconductor die, wherein a lower surface of the photoluminescent structure adheres to an upper surface of the LED semiconductor die. A reflective resin material is disposed surrounding edge surfaces of the LED semiconductor die and the photoluminescent structure forming a beveled reflector. A method to manufacture the above light emitting device is also disclosed. Advantages of this light emitting device with beveled reflector include increasing the light extraction efficiency, making the viewing angle tunable, improving spatial color uniformity and reducing the light source etendue realized in a compact form-factor size.



LIGHT EMITTING DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

A light emitting device includes at least one semiconductor light emitting element, and a wavelength conversion layer which is formed on a surface of the semiconductor light emitting element and which includes a resin layer containing a wavelength conversion member for converting a wavelength of light emitted from the semiconductor light emitting element. The wavelength conversion layer covers an upper surface or the upper surface and a side surface of the semiconductor light emitting element. A content of an inorganic material including the wavelength conversion member, or a content of an inorganic material including the wavelength conversion member and an inorganic filler, in the resin layer is 30% by mass or more and 99% by mass or less.



LIGHT EMITTING DIODE DEVICES WITH ZINC OXIDE LAYER

Thu, 06 Apr 2017 08:00:00 EDT

LED devices having high-quality single crystal ZnO structures for spreading currents and extracting light out of the LEDs are disclosed. In one aspect, a LED device is provided to include a substrate; a first semiconductor layer exhibiting a first conductivity type and formed over the substrate; an active light-emitting structure formed over the first semiconductor layer, the active light-emitting structure operable to emit light under electrical excitation; a second semiconductor layer exhibiting a second conductivity type and formed over the active light-emitting structure; and a single crystal ZnO structure formed over the second semiconductor layer and including a bottom single crystal ZnO portion over the second semiconductor layer and a top single crystal ZnO portion extending from the bottom single crystal ZnO portion, wherein the bottom single crystal ZnO portion is a contiguous single crystal ZnO portion without having voids.



Contact Configuration for Optoelectronic Device

Thu, 06 Apr 2017 08:00:00 EDT

An optoelectronic device with a multi-layer contact is described. The optoelectronic device can include a n-type semiconductor layer having a surface. A mesa can be located over a first portion of the surface of the n-type semiconductor layer and have a mesa boundary. A n-type contact region can be located over a second portion of the surface of the n-type semiconductor contact layer entirely distinct from the first portion, and be at least partially defined by the mesa boundary. A first n-type metallic contact layer can be located over at least a portion of the n-type contact region in proximity of the mesa boundary, where the first n-type metallic contact layer forms an ohmic contact with the n-type semiconductor layer. A second n-type metallic contact layer can be located over a second portion of the n-type contact region, where the second n-type metallic contact layer is formed of a reflective metallic material.



Light Emitting Diode

Thu, 06 Apr 2017 08:00:00 EDT

A light emitting diode includes: a substrate; a semiconductor light emitting laminate on the substrate, including from bottom up a first semiconductor layer, an active layer, and a second semiconductor layer electrically dissimilar to the first semiconductor layer; a transparent conductive layer with an opening portion; the first electrode electrically connected with the first semiconductor layer; and the second electrode electrically connected with the second semiconductor layer; the second electrode fills the opening portion, and the position where the second electrode contacts the transparent conductive layer is arranged with a recessed portion, and the second electrode is embedded in the transparent conductive layer. The recessed portion is formed on the second electrode, having the second electrode embedded in the transparent conductive layer, increasing the counter force of the second electrode against the horizontal thrust during encapsulation of the LED structure and avoiding detachment during wire bonding for encapsulation.



NITRIDE SEMICONDUCTOR LIGHT EMITTING ELEMENT

Thu, 06 Apr 2017 08:00:00 EDT

A nitride semiconductor light emitting element 1 includes a second conductivity type nitride semiconductor layer which is formed above thea first conductivity type nitride semiconductor layer, a first electrode 17a which is formed on a first region of the second conductivity type nitride semiconductor layer with a first current non-injection layer 13a in between, a first current diffusing layer 14a which is formed between the first current non-injection layer 13a and the first electrode 17a, a second electrode 17b which is formed on a second region of the second conductivity type nitride semiconductor layer with a second current non-injection layer 13b in between, a second current diffusing layer 14b which is formed on the second region and on the second current non-injection layer 13b, and an extending portion 17c which extends from the first electrode 17a and reaches the exposed first conductivity type nitride semiconductor layer.



MATERIAL LAYER STACK, LIGHT EMITTING ELEMENT, LIGHT EMITTING PACKAGE, AND METHOD OF FABRICATING LIGHT EMITTING ELEMENT

Thu, 06 Apr 2017 08:00:00 EDT

Disclosed herein are a material layer stack, a light emitting element, a light emitting package, and a method of fabricating a light emitting element. The material layer stack includes: a substrate having a first lattice constant; and a semiconductor layer grown on the substrate, the semiconductor layer having a second lattice constant that is different from the first lattice constant. Using the material layer stack, a light emitting element having a low leakage current, a low operation voltage, and an excellent luminous efficiency can be obtained.



LIGHT-EMITTING DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

A light-emitting device is provided. The light-emitting device comprises a light-emitting stack comprising a first semiconductor layer, a second semiconductor layer and an active layer between the first semiconductor layer and the second semiconductor layer. The light-emitting device further comprises a third semiconductor layer on the light-emitting stack and comprising a first sub-layer, a second sub-layer and a roughened surface, wherein the first sub-layer has the same composition as that of the second sub-layer, and the composition of the first sub-layer is with a different atomic ratio from that of the second sub-layer. A method for manufacturing the light-emitting device is also provided.



LIGHT-EMITTING ELEMENT, LIGHT-EMITTING ELEMENT UNIT, AND LIGHT-EMITTING ELEMENT PACKAGE

Thu, 06 Apr 2017 08:00:00 EDT

In a light-emitting element (1), a light-emitting layer (4), a second conductivity type semiconductor layer (5), a transparent electrode layer (6), a reflecting electrode layer (7) and an insulating layer (8) are stacked in this order on a first conductivity type semiconductor layer (3), while a first electrode layer (10) and a second electrode layer (12) are stacked on the insulating layer (8) in an isolated state. The light-emitting element (1) includes a plurality of insulating tube layers (9), discretely arranged in plan view, passing through the reflecting electrode layer (7), the transparent electrode layer (6), the second conductivity type semiconductor layer (5) and the light-emitting layer (4) continuously from the insulating layer (8) and reaching the first conductivity type semiconductor layer (3), first contacts (11), continuous from the first electrode layer (10), connected to the first conductivity type semiconductor layer (3) through the insulating layer (8) and the insulating tube layers (9), and second contacts (13), continuous from the second electrode layer (12), passing through the insulating layer (8) to be connected to the reflecting electrode layer (7).



Light Emitting Heterostructure with Partially Relaxed Semiconductor Layer

Thu, 06 Apr 2017 08:00:00 EDT

A light emitting heterostructure including a partially relaxed semiconductor layer is provided. The partially relaxed semiconductor layer can be included as a sublayer of a contact semiconductor layer of the light emitting heterostructure. A dislocation blocking structure also can be included adjacent to the partially relaxed semiconductor layer.



SCHOTTKY DIODE AND METHOD OF MANUFACTURING THE SAME

Thu, 06 Apr 2017 08:00:00 EDT

A Schottky diode comprises: a substrate; a first semiconductor layer located on the substrate; a second semiconductor layer located on the first semiconductor layer, two-dimensional electron gas being formed at an interface between the first semiconductor layer and the second semiconductor layer; a cathode located on the second semiconductor layer and forming an ohmic contact with the second semiconductor layer; a first passivation dielectric layer located on the second semiconductor layer; a field plate groove formed in the first passivation dielectric layer; and an anode covering the field plate groove and a portion of the first passivation dielectric layer.



SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Thu, 06 Apr 2017 08:00:00 EDT

A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a semiconductor layer, a gate electrode on the semiconductor layer, a first insulating layer between the semiconductor layer and the gate electrode; a second insulating layer on the gate electrode, source and drain electrodes corresponding to both ends of the semiconductor layer and disposed on the second insulating layer, and a doping layer disposed along contact holes of the first and second insulating layers, which expose the both ends of the semiconductor layer, such as, between the both ends of the semiconductor layer and the source and drain electrodes.



DEVICES HAVING TRANSITION METAL DICHALCOGENIDE LAYERS WITH DIFFERENT THICKNESSES AND METHODS OF MANUFACTURE

Thu, 06 Apr 2017 08:00:00 EDT

An embodiment is a structure including a first active device in a first region of a substrate, the first active device including a first layer of a two-dimensional (2-D) material, the first layer having a first thickness, and a second active device in a second region of the substrate, the second active device including a second layer of the 2-D material, the second layer having a second thickness, the 2-D material including a transition metal dichalcogenide (TMD), the second thickness being different than the first thickness.



TWO-DIMENSIONAL HETEROJUNCTION INTERLAYER TUNNELING FIELD EFFECT TRANSISTORS

Thu, 06 Apr 2017 08:00:00 EDT

A two-dimensional (2D) heterojunction interlayer tunneling field effect transistor (Thin-TFET) allows for particle tunneling in a vertical stack comprising monolayers of two-dimensional semiconductors separated by an interlayer. In some examples, the two 2D materials may be misaligned so as to influence the magnitude of the tunneling current, but have a modest impact on gate voltage dependence. The Thin-TFET can achieve very steep subthreshold swing, whose lower limit is ultimately set by the band tails in the energy gaps of the 2D materials produced by energy broadening. These qualities in turn make the Thin-TFET an ideal low voltage, low energy solid state electronic switch.



THIN FILM TRANSISTORS WITH TRENCH-DEFINED NANOSCALE CHANNEL LENGTHS

Thu, 06 Apr 2017 08:00:00 EDT

Thin film transistors (TFTs), including radiofrequency TFTs, with submicron-scale channel lengths and methods for making the TFTs are provided. The transistors include a trench cut into the layer of semiconductor that makes up the body of the transistors. Trench separates the source and drain regions and determines the channel length of the transistor.



THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE, DISPLAY DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

Embodiments of the present invention disclose a thin film transistor and a manufacturing method thereof, an array substrate, and a display device, which relates to the field of display technology, and solves the problem that the adhesion of the electrode thin film with the adjacent thin film layer in the thin film transistor of the prior art is relatively bad. More specifically, an embodiment of the present invention provides a thin film transistor, comprising a gate, a source, a drain and a buffer layer, the buffer layer is located at one side or two sides of the gate, the source or the drain, the material of the buffer layer is a copper alloy material, the copper alloy material contains nitrogen element or oxygen element, the copper alloy material further contains aluminum element.



Engineered Ferroelectric Gate Devices

Thu, 06 Apr 2017 08:00:00 EDT

Coupling of switchable ferroelectric polarization with the carrier transport in an adjacent semiconductor enables a robust, non-volatile manipulation of the conductance in a host of low-dimensional systems, including the two-dimensional electron liquid that forms at the LaAlO3-SrTiO3 interface. However, the strength of the gate-channel coupling is relatively weak, limited in part by the electrostatic potential difference across a ferroelectric gate. Compositionally grading of PbZr1-xTixO3 ferroelectric gates enables a more than twenty-five-fold increase in the LAO/STO channel conductance on/off ratios. Incorporation of polarization gradients in ferroelectric gates can enable significantly enhanced performance of ferroelectric non-volatile memories.



SEMICONDUCTOR TRANSISTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Thu, 06 Apr 2017 08:00:00 EDT

A semiconductor transistor device includes an oxide semiconductor layer having an active surface, a source electrode, a drain electrode, a gate electrode and a control capacitor. The gate electrode, the source electrode and the drain electrode are directly in contact with the active surface. The gate electrode is disposed between the drain electrode and the source electrode. The gate electrode, the source electrode and the drain electrode are separated from each other. The control capacitor is electrically connected to the gate electrode through a connection.



SEMICONDUCTOR DEVICES, FINFET DEVICES AND METHODS OF FORMING THE SAME

Thu, 06 Apr 2017 08:00:00 EDT

Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate over the substrate. Besides, the gate include a first portion, a second portion overlying the first portion and a third portion overlying the second portion, and the critical dimension of the second portion is smaller than each of the critical dimension of the first portion and the critical dimension of the third portion.



SEMICONDUCTOR DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

A semiconductor device includes a substrate, a gate structure, a sidewall spacer, and an epitaxial layer. The gate structure is disposed on the substrate, and the substrate has at least one recess disposed adjacent to the gate structure. The sidewall spacer is disposed on at least two sides of the gate structure. The sidewall spacer includes a first spacer layer and a second spacer layer, and the first spacer layer is disposed between the gate structure and the second spacer layer. The epitaxial layer is disposed in the recess, and the recess is a circular shaped recess. A distance between an upmost part of the recess and the gate structure is less than a width of the sidewall spacer.



SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Thu, 06 Apr 2017 08:00:00 EDT

A manufacturing method of a semiconductor structure includes the following steps. An epitaxial region is formed in a semiconductor substrate. A dielectric layer is formed on the epitaxial region, and a contact hole is formed in the dielectric layer. The contact hole exposes a part of the epitaxial region, and an oxide-containing layer is formed on the epitaxial region exposed by the contact hole. A contact structure is formed in the contact hole and on the oxide-containing layer. The oxide-containing layer is located between the contact structure and the epitaxial region. A semiconductor structure includes the semiconductor substrate, at least one epitaxial region, the contact structure, the oxide-containing layer, and a silicide layer. The contact structure is disposed on the epitaxial region. The oxide-containing layer is disposed between the epitaxial region and the contact structure. The silicide layer is disposed between the oxide-containing layer and the contact structure.



Field Effect Transistors and Methods of Forming Same

Thu, 06 Apr 2017 08:00:00 EDT

Semiconductor devices and methods of forming the same are provided. A first source/drain layer is formed over a substrate. A channel layer is formed over the first source/drain layer. A second source/drain layer is formed over the channel layer. The first source/drain layer, the channel layer, and the second source/drain layer are patterned to form a fin-shaped structure. A gate stack is formed on a sidewall of the fin-shaped structure. The fin-shaped structure is patterned to expose a top surface of the first source/drain layer.



Termination Region Architecture for Vertical Power Transistors

Thu, 06 Apr 2017 08:00:00 EDT

A vertical power switching device, such as a vertical superjunction metal-oxide-semiconductor field-effect-transistor (MOSFET), in which termination structures in the corners of the integrated circuit are stretched to efficiently shape the lateral electric field. Termination structures in the device include such features as doped regions, field plates, insulator films, and high-voltage conductive regions and elements at the applied substrate voltage. Edges of these termination structures are shaped and placed according to a 2nd-order smooth, non-circular analytic function so as to extend deeper into the die corner from the core region of the device than a constant-distance path. Also disclosed are electrically floating guard rings in the termination region, to inhibit triggering of parasitic p-n-p-n structures.



SHIELD WRAP FOR A HETEROSTRUCTURE FIELD EFFECT TRANSISTOR

Thu, 06 Apr 2017 08:00:00 EDT

Devices are disclosed for providing heterojunction field effect transistor (HFETs) having improved performance and/or reduced noise generation. A gate electrode is over a portion of the active region and is configured to modulate a conduction channel in the active region of an HFET. The active region is in a semiconductor film between a source electrode and a drain electrode. A first passivation film is over the active region. An encapsulation film is over the first passivation film. A first metal pattern on the encapsulation film includes a shield wrap over the majority of the active region and is electrically connected to the source electrode



SEMICONDUCTOR DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

Provided is a semiconductor device in which electron mobility is improved by applying sufficiently large tensile stress in a predetermined direction without occurrence of cracks in a nitride semiconductor. The semiconductor device includes: substrate (101), electron transit layer (103) that is disposed on substrate (101) and is formed by GaN; and electron supply layer (104) that is disposed on electron transit layer (103) and is formed by AlGaN. A coefficient of thermal expansion of substrate (101) is different between a first direction in a main surface of substrate (101) and a second direction that is perpendicular to the first direction in the main surface, and tensile stress occurs in electron transit layer (103).



AVALANCHE ENERGY HANDLING CAPABLE III-NITRIDE TRANSISTORS

Thu, 06 Apr 2017 08:00:00 EDT

A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.



SEMICONDUCTOR DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

A semiconductor device includes: an electron transit layer constituted of GaN; an electron supply layer constituted of Inx1Aly1Ga1-x1-y1N (0≦x1



DIODE, SEMICONDUCTOR DEVICE, AND MOSFET

Thu, 06 Apr 2017 08:00:00 EDT

Disclosed is a technique capable of reducing loss at the time of switching in a diode. A diode disclosed in the present specification includes a cathode electrode, a cathode region made of a first conductivity type semiconductor, a drift region made of a low concentration first conductivity type semiconductor, an anode region made of a second conductivity type semiconductor, an anode electrode made of metal, a barrier region formed between the drift region and the anode region and made of a first conductivity type semiconductor having a concentration higher than that of the drift region, and a pillar region formed so as to connect the barrier region to the anode electrode and made of a first conductivity type semiconductor having a concentration higher than that of the barrier region. The pillar region and the anode are connected through a Schottky junction.



IMPLEMENTING STRESS IN A BIPOLAR JUNCTION TRANSISTOR

Thu, 06 Apr 2017 08:00:00 EDT

Device structure and fabrication methods for a bipolar junction transistor. One or more trench isolation regions are formed in a substrate to define a device region having a first width. A protect layer is formed on a top surface of the one or more trench isolation regions and a top surface of the device region. An opening is formed in the protect layer. The opening is coincides with the top surface of the first device region and has a second width that is less than or equal to the first width of the first device region. A base layer is formed that has a first section on the device region inside the first opening and a second section on the protect layer.



DIELECTRIC ISOLATED SiGe FIN ON BULK SUBSTRATE

Thu, 06 Apr 2017 08:00:00 EDT

A method for forming fins on a semiconductor device includes etching trenches into a monocrystalline substrate to form first fins and forming a first dielectric layer at bottoms of the trenches. Second fins of a material having a different composition than the substrate are grown on sidewalls of the trenches. A second dielectric layer is formed over the second fins. The first fins are removed by etching. The second fins are processed to form fin field effect transistor devices.



SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME

Thu, 06 Apr 2017 08:00:00 EDT

Provided is a semiconductor structure including a substrate, a first gate, a second gate, a third gate and an inter-gate dielectric layer. The substrate has a first area and a second area, and the first surface of the first area is lower than the second surface of the second area. The first gate is disposed on the first surface of the first area. The second gate includes metal and is disposed on the first gate. The inter-gate dielectric layer is disposed between the first and second gates. The third gate includes metal and is disposed on the second surface of the second area. A method of foaming a semiconductor structure is further provided.



SIC EPITAXIAL WAFER, MANUFACTURING APPARATUS OF A SIC EPITAXIAL WAFER, FABRICATION METHOD OF A SIC EPITAXIAL WAFER, AND SEMICONDUCTOR DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

The SiC epitaxial wafer includes a substrate, and an SiC epitaxial growth layer disposed on the substrate, wherein an Si compound gas is used for a supply source of Si, and a Carbon (C) compound gas is used as a supply source of C, for the SiC epitaxial growth layer, wherein any one or both of the Si compound gas and the C compound gas is provided with a compound gas containing Fluorine (F), as the supply source. The Si compound is generally expressed with SinHxClyFz (n>=1, x>=0, y>=0, z>=1, x+y+z=2n+2), and the C compound is generally expressed with CmHqClrFs (m>=1, q>=0, r>=0, s>=1, q+r+s=2m+2) . There are provided a high quality SiC epitaxial wafer having few surface defects and having excellent film thickness uniformity and carrier density uniformity, a manufacturing apparatus of such an SiC epitaxial wafer, a fabrication method of such an SiC epitaxial wafer, and a semiconductor device.



SEMICONDUCTOR DEVICE AND METHOD OF FORMATION

Thu, 06 Apr 2017 08:00:00 EDT

A semiconductor device and method of formation are provided. The semiconductor device includes a substrate, a first active area over the substrate, a second active area over the substrate, a graphene channel between the first active area and the second active area, and a first in-plane gate. In some embodiments, the graphene channel, the first in-plane gate, the first active area, and the second active area include graphene. A method of forming the first in-plane gate, the first active area, the second active area, and the graphene channel from a single layer of graphene is also provided.



FIN-TYPE FIELD EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME

Thu, 06 Apr 2017 08:00:00 EDT

Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.



ORGANIC LIGHT-EMITTING DISPLAY APPARATUS

Thu, 06 Apr 2017 08:00:00 EDT

An organic light-emitting display apparatus includes a pixel electrode, a light emission layer over the pixel electrode, an opposite electrode covering the light emission layer, a plurality of upper layers over the opposite electrode, a light-shielding layer over the upper layers. A distance L between an edge of an emission area of the light emission layer and an edge of the light-shielding layer when viewed in a thickness direction satisfies Inequality below: L≥∑i=1mditan(sin-1(nairnisinθair))+dBMtan(sin-1(nairnCFsinθair))[Inequality] wherein m represents the number of the upper layers, ni and di represent a refraction index and a thickness of each of the upper layers, respectively, dBM represents a thickness of the light-shielding layer, nCF represents a refraction index of the color filter layer, nair represents a refraction index of air, and θair represents a refraction angle in external air after light generated from the light emission layer passes through the color filter layer.



ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD FOR MANUFACTURING THE SAME

Thu, 06 Apr 2017 08:00:00 EDT

An organic light emitting diode (OLED) display includes a base substrate, a first electrode on the base substrate, a pixel definition layer on the first electrode and having an opening exposing the first electrode, spacers on the pixel definition layer and having a smaller modulus than the pixel definition layer, an organic emission layer on the first electrode to correspond to the opening, and a second electrode on the organic emission layer.



LIGHT EMITTING DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME

Thu, 06 Apr 2017 08:00:00 EDT

The light emitting display device comprises: a substrate including a plurality of pixels that are arranged in a first direction and a second direction that crosses the first direction; a first electrode for each pixel on the substrate; a pixel defining layer on the substrate, the pixel defining layer having an opening for exposing the first electrode; a hole injection layer on the first electrode; a lyophilic pattern extending on the hole injection layer to cover the first electrode and the pixel defining layer that are on a same line in the first direction, and extending up to an outer region of outermost pixels of the plurality of pixels in the first direction; a hole transport layer on the lyophilic pattern; a light emitting layer on the hole transport layer; and a second electrode on the light emitting layer, wherein the lyophilic pattern includes a first lyophilic pattern having a plurality of grooves on one end portion thereof in the first direction and a second lyophilic pattern having a plurality of grooves on another end portion thereof in the first direction, and wherein the first lyophilic pattern and the second lyophilic pattern are alternately arranged in the second direction.



ORGANIC LIGHT EMITTING DIODE DISPLAY

Thu, 06 Apr 2017 08:00:00 EDT

An organic light emitting diode (OLED) display includes a substrate, a first electrode disposed on the substrate, an organic emission layer disposed on the first electrode, a second electrode disposed on the organic emission layer, and a capping layer disposed on the second electrode, in which an optical thickness of the capping layer is in a range of about 1100 Å to about 1400 Å.



Vertical Bit Line Non-Volatile Memory Systems And Methods Of Fabrication

Thu, 06 Apr 2017 08:00:00 EDT

Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and methods of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. The gates overlie the global bit lines with one or more insulating layers therebetween to provide adequate isolation between the gates and the global bit lines. Processes for fabricating the vertical TFT select devices utilize a gate dielectric and optional dielectric bases to provide isolation between the gates and bit lines.



SWITCH DEVICE AND STORAGE UNIT

Thu, 06 Apr 2017 08:00:00 EDT

A switch device includes: a first electrode; a second electrode arranged to face the first electrode; and a switch layer provided between the first electrode and the second electrode. The switch layer includes a first layer containing a chalcogen element, and a second layer containing a high resistance material.



SWITCH DEVICE AND STORAGE UNIT

Thu, 06 Apr 2017 08:00:00 EDT

A switch device includes: a first electrode; a second electrode arranged to face the first electrode; and a switch layer provided between the first electrode and the second electrode. The switch layer includes a first layer containing a chalcogen element, and a second layer containing a high resistance material.



SYSTEMS AND METHODS FOR FABRICATION OF SUPERCONDUCTING INTEGRATED CIRCUITS

Thu, 06 Apr 2017 08:00:00 EDT

Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.



IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME

Thu, 06 Apr 2017 08:00:00 EDT

Provided is an image sensor having improved characteristics. An image sensor in accordance with an embodiment of the present invention may include first and second photoelectric conversion elements formed in a substrate, wherein the first photoelectric conversion element has a first impurity region; a device isolation trench formed in the substrate and between the first and the second photoelectric conversion elements, wherein a sidewall of the device isolation trench is in contact with the first impurity region; and an epitaxial layer filling the device isolation trench, and having different conductivity from the first impurity region.



STACKED IMAGE SENSOR

Thu, 06 Apr 2017 08:00:00 EDT

A stacked image sensor includes a first photoelectric conversion layer including a plurality of first photoelectric conversion regions; a second photoelectric conversion layer disposed on the first photoelectric conversion layer, and including a plurality of second photoelectric conversion regions; and a plurality of color filters disposed on the plurality of second photoelectric conversion regions, wherein at least one of the plurality of first photoelectric conversion regions includes a plurality of third photoelectric conversion regions that perform auto-focusing.



Structure and Method for 3D Image Sensor

Thu, 06 Apr 2017 08:00:00 EDT

An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.



CHIP SCALE SENSING CHIP PACKAGE AND A MANUFACTURING METHOD THEREOF

Thu, 06 Apr 2017 08:00:00 EDT

This present invention provides a chip scale sensing chip package, comprising: a sensing chip with a first top surface and a first bottom surface opposite to each other, wherein the first top surface has a first insulating layer formed thereon, and the sensing chip comprises a sensing device adjacent to the first top surface and a plurality of conductive pads formed within the first insulating and adjacent to the sensing device, and a wiring layer formed on the first bottom surface to respectively connect to each of the conductive pads; and a dam formed on the first insulating layer adjacent to the sensing device.



SEMICONDUCTOR DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

A semiconductor device including a substrate, at least one sensor, a dielectric layer, at least one light pipe structure, at least one pad, a shielding layer, and a protection layer is provided. The sensor is located in the substrate of a first region. The dielectric layer is located on the substrate. The light pipe structure is located in the dielectric layer of the first region. The light pipe structure corresponds to the sensor. The pad is located in the dielectric layer of a second region. The shielding layer is located on the dielectric layer, wherein the light pipe structure is surrounded by the shielding layer. The protection layer is located on the shielding layer. At least one pad opening is disposed in the dielectric layer, the shielding layer, and the protection layer above the pad. The pad opening exposes a top surface of the corresponding pad.



SOLID-STATE IMAGE PICKUP APPARATUS, AND IMAGE PICKUP SYSTEM USING SOLID-STATE IMAGE PICKUP APPARATUS

Thu, 06 Apr 2017 08:00:00 EDT

A solid-state image pickup apparatus includes a photoelectric conversion unit, a charge storage unit, and a floating diffusion unit, all disposed on a semiconductor substrate. The solid-state image pickup apparatus further includes a first gate electrode disposed on the semiconductor substrate and extending between the photoelectric conversion unit and charge storage unit, and a second gate electrode disposed on the semiconductor substrate and extending between the charge storage unit and the floating diffusion unit. The solid-state image pickup apparatus further includes a light shielding member including a first part and a second part, wherein the first part is disposed over the charge storage unit and at least over the first gate electrode or the second gate electrode, and the second part is disposed between the first gate electrode and the second gate electrode such that the second part extends from the first part toward a surface of the semiconductor substrate.



SOLID-STATE IMAGING APPARATUS

Thu, 06 Apr 2017 08:00:00 EDT

A solid-state imaging apparatus includes: a solid-state imaging device photoelectrically converting light taken by a lens; and a light shielding member shielding part of light incident on the solid-state imaging device from the lens, wherein an angle made between an edge surface of the light shielding member and an optical axis direction of the lens is larger than an incident angle of light to be incident on an edge portion of the light shielding member.



IMAGING ELEMENT AND IMAGING DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

An imaging element according to the present disclosure includes: a first pixel and a second pixel each including a light receiving section and a light condensing section, in which the light receiving section includes a photoelectric conversion element, and the light condensing section is configured to allow entering light to be condensed toward the light receiving section; a trench provided between the first pixel and the second pixel; a first light shielding film embedded in the trench; and a second light shielding film provided on part of a light receiving surface of the light receiving section of the second pixel, in which the second light shielding film is continuous with the first light shielding film.



IMAGE SENSOR INCLUDING COLOR SEPARATION ELEMENT

Thu, 06 Apr 2017 08:00:00 EDT

An image sensor includes a pixel array including a first pixel row, in which a plurality of first pixels and a plurality of second pixels are alternately arranged, and a second pixel row, in which a plurality of second pixels and a plurality of third pixels are alternately arranged; first color separation elements configured to allow light having a second wavelength band, among incident light, to pass therethrough and travel in a downward direction, and to allow a mixture of light having a first wavelength band and light having a third wavelength band, among the incident light, to pass therethrough and travel in a lateral direction; and first color filters on at least a portion of the plurality of first pixels, the first color filters being configured to transmit only the light having the first wavelength band.



SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS

Thu, 06 Apr 2017 08:00:00 EDT

A solid-state imaging device having a backside illuminated structure, includes: a pixel region in which pixels each having a photoelectric conversion portion and a plurality of pixel transistors are arranged in a two-dimensional matrix; an element isolation region isolating the pixels which is provided in the pixel region and which includes a semiconductor layer provided in a trench by an epitaxial growth; and a light receiving surface at a rear surface side of a semiconductor substrate which is opposite to a multilayer wiring layer.



DISPLAY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING DISPLAY DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

A display device according to the present disclosure includes: a transistor section (100) that includes a gate insulating film (130), a semiconductor layer (140), and a gate electrode layer (120), the semiconductor layer being laminated on the gate insulating film, the gate electrode film being laminated on an opposite side to the semiconductor layer of the gate insulating film; a first capacitor section (200) that includes a first metal film (210) and a second metal film (220), the first metal film being disposed at a same level as wiring layers (161, 162) that are electrically connected to the semiconductor layer and is disposed over the transistor section, the second metal film being disposed over the first metal film with a first interlayer insulating film (152) in between; and a display element that is configured to be controlled by the transistor section.



LOW TEMPERATURE POLY-SILICON TFT SUBSTRATE STRUCTURE AND MANUFACTURE METHOD THEREOF

Thu, 06 Apr 2017 08:00:00 EDT

The present invention provides a Low Temperature Poly-silicon TFT substrate structure and a manufacture method thereof. By providing the amorphous silicon layers in the drive TFT area and the display TFT area with different thicknesses, of which the thickness of the amorphous silicon layer in the drive TFT area is smaller, and the thickness of the amorphous silicon layer in the display TFT area is larger, and thus, in the Excimer Laser Annealing process, different crystallization results are generated with the amorphous silicon layers in the drive TFT area and the display TFT area under the function of the laser with the same energy to achieve the control to the grain diameters of the crystals. The polysilicon layer with larger lattice dimension is formed in the drive TFT area in the crystallization process to raise the electron mobility. The fractured crystals of polysilicon layer in the display TFT area can be obtained in the crystallization process for ensuring the uniformity of the grain boundary and raising the uniformity of the current. Accordingly, the electrical property demands for the different TFTs can be satisfied to raise the light uniformity of the OLED.



THIN FILM TRANSISTOR SUBSTRATE, DISPLAY APPARATUS INCLUDING THIN FILM TRANSISTOR SUBSTRATE, METHOD OF MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE, AND METHOD OF MANUFACTURING DISPLAY APPARATUS

Thu, 06 Apr 2017 08:00:00 EDT

A thin film transistor (TFT) substrate in which properties of a TFT may be modified according to a function of the TFT, a display apparatus including the TFT substrate, a method of manufacturing the TFT substrate, and a method of manufacturing the display apparatus. The thin film transistor (TFT) substrate includes a substrate; a first TFT disposed on the substrate and comprising a first active pattern and a first gate electrode at least partially overlapping with the first active pattern and disposed between the substrate and the first active pattern; and a second TFT disposed on the substrate and comprising a second active pattern and a second gate electrode at least partially overlapping with the second active pattern.



HYBRID SUBSTRATE ENGINEERING IN CMOS FINFET INTEGRATION FOR MOBILITY IMPROVEMENT

Thu, 06 Apr 2017 08:00:00 EDT

A method for forming a hybrid complementary metal oxide semiconductor (CMOS) device includes orienting a semiconductor layer of a semiconductor-on-insulator (SOI) substrate with a base substrate of the SOI, exposing the base substrate in an N-well region by etching through a mask layer, a dielectric layer, the semiconductor layer and a buried dielectric to form a trench and forming spacers on sidewalls of the trench. The base substrate is epitaxially grown from a bottom of the trench to form an extended region. A fin material is epitaxially grown from the extended region within the trench. The mask layer and the dielectric layer are restored over the trench. P-type field-effect transistor (PFET) fins are etched on the base substrate, and N-type field-effect transistor (NFET) fins are etched in the semiconductor layer.



INTEGRATED CIRCUITS (ICS) ON A GLASS SUBSTRATE

Thu, 06 Apr 2017 08:00:00 EDT

An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.



SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Thu, 06 Apr 2017 08:00:00 EDT

In the case where a signal delay is found in a circuit operation in a semiconductor chip, when a repeater for delay reduction is additionally formed as a result of a design change, an increase in the area of the semiconductor chip and an increase in the manufacturing cost of a semiconductor device are prevented. The inverter forming the repeater is formed of transistors formed in the upper portion of stacked wiring layers, not transistors in the vicinity of a main surface of a semiconductor substrate. By thus implementing a design change such that the repeater is added, the number of the wiring layers which need a layout change is reduced.



SEMICONDUCTOR DEVICE INCLUDING A REPEATER/BUFFER AT HIGHER METAL ROUTING LAYERS AND METHODS OF MANUFACTURING THE SAME

Thu, 06 Apr 2017 08:00:00 EDT

A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include one or more transition metal dichalcogenide materials such as MoS2, WS2, WSe2, and/or combinations thereof.



APPARATUSES HAVING A FERROELECTRIC FIELD-EFFECT TRANSISTOR MEMORY ARRAY AND RELATED METHOD

Thu, 06 Apr 2017 08:00:00 EDT

An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to form a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having the plurality of FeFET memory cells accessible by neighboring gates.



SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Thu, 06 Apr 2017 08:00:00 EDT

According to one embodiment, the plurality of charge storage films are separated in a stacking direction with a second air gap interposed. The plurality of insulating films are provided on side surfaces of electrode layers opposing the charge storage films, on portions of surfaces of the electrode layers continuous from the side surfaces and opposing a first air gap between the electrode layers, and on corners of the electrode layers between the portions and the side surfaces. The plurality of insulating films are divided in the stacking direction with a third air gap interposed and without the charge storage films being interposed. The third air gap communicates with the first air gap and the second air gap between the first air gap and the second air gap.



SEMICONDUCTOR MEMORY DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

According to an embodiment, a semiconductor memory device comprises a first region, a second region, and a third region. The first region includes: a part of a stacked body that includes a plurality of conductive layers; and a memory columnar body which has its side surface covered by the stacked body and configures a memory string. The second region includes: a contact; a contact portion connected to the contact, of the conductive layer; and a plurality of first columnar bodies. The third region includes a second columnar body. In a plane parallel to the substrate, a total area of the second columnar body in a small region that has the same area as one or more contact portions, in the third region is larger than a total area of the first columnar body in the one or more contact portions.



Semiconductor Memory Devices

Thu, 06 Apr 2017 08:00:00 EDT

A semiconductor memory device includes insulating patterns and gate patterns alternately stacked on a substrate, a channel structure that intersects the insulating patterns and the gate patterns and connected to the substrate, a charge storage structure between the channel structure and the gate patterns, and a contact structure on the substrate at a side of the insulating patterns and the gate patterns. One of the gate patterns includes a first barrier pattern between a first insulating pattern of the insulating patterns and a second insulating pattern of the insulating patterns adjacent the first insulating pattern in a first direction perpendicular to a main surface of the substrate, the first barrier pattern defining a concave region between a first portion of the first barrier pattern extending along the first insulating pattern and a second portion extending along the second insulating pattern, and a metal pattern in the concave region.



THREE-DIMENSIONAL MEMORY STRUCTURE HAVING A BACK GATE ELECTRODE

Thu, 06 Apr 2017 08:00:00 EDT

A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.



SEMICONDUCTOR DEVICE HAVING CAPACITOR AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

A semiconductor device having a capacitor includes a substrate which has a transistor, a first insulating pattern which is formed on the substrate and does not overlap a first contact node formed in the substrate, a second insulating pattern which is formed on the substrate, does not overlap a second contact node formed in the substrate, and is separated from the first insulating pattern, a first lower electrode which is formed on part of the substrate and sidewalls of the first insulating pattern, a second lower electrode which is formed on part of the substrate and sidewalls of the second insulating pattern, a dielectric layer pattern which is formed on the first lower electrode and the second lower electrode, and an upper electrode which is formed on the dielectric layer pattern. Related fabrication methods are also discussed.



SEMICONDUCTOR DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

A semiconductor device includes: a first semiconductor layer stacked body including a compound semiconductor; a first field-effect transistor element including a first drain electrode, a first source electrode, and a first gate electrode that are provided on the first semiconductor layer stacked body; a second semiconductor layer stacked body including a compound semiconductor; and a second field-effect transistor element including a second drain electrode, a second source electrode, and a second gate electrode that are provided on the second semiconductor layer stacked body. The second gate electrode forms a Schottky junction or a p-n junction with the second semiconductor layer stacked body, the second drain electrode is connected to the first drain electrode, the second source electrode is connected to the first gate electrode, and the second gate electrode is connected to the first source electrode.



INTEGRATED CIRCUIT HAVING FIELD-EFFECT TRASISTORS WITH DIELECTRIC FIN SIDEWALL STRUCTURES AND MANUFACTURING METHOD THEREOF

Thu, 06 Apr 2017 08:00:00 EDT

An integrated circuit includes a first semiconductor fin, a first epitaxy structure, and at least two first dielectric fin sidewall structures. The first epitaxy structure is disposed on the first semiconductor fin. The first dielectric fin sidewall structures are disposed on opposite sidewalls of the first epitaxy structure. The first dielectric fin sidewall structures have different heights.



SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR SUBSTRATE, SILICON CARBIDE SEMICONDUCTOR LAYER, UNIT CELLS, SOURCE, AND GATE

Thu, 06 Apr 2017 08:00:00 EDT

A semiconductor device includes a first silicon carbide semiconductor layer, a source including a source pad and a source wiring, a gate including a gate pad and a gate wiring, first unit cells disposed in a first element region, and second unit cells disposed in a second element region. In a plan view, the first and second element regions are adjacent to each other with the gate wiring between the first and second element regions. A first electrode including the gate electrode of each first unit cell is disposed in the first element region and electrically connected to the gate. A second electrode including the gate electrode of each second unit cell is disposed in the second element region and not electrically connected to the gate. The first and second electrodes are separated below the gate wiring.



ESD DEVICE COMPATIBLE WITH BULK BIAS CAPABILITY

Thu, 06 Apr 2017 08:00:00 EDT

A device having an electrostatic discharge structure includes a bulk substrate having a first dopant conductivity, first wells formed adjacent to a surface of the bulk substrate, including a second dopant conductivity, and second wells formed adjacent to the surface of the bulk substrate within the first wells, including the first dopant conductivity. A supply bus is formed in one of the first wells outside the second well. A ground bus has a first portion formed in another first well outside the second well, and a second portion is formed inside the second well such that a charge input to the second wells is dissipated without accumulating in the bulk substrate.



SCRS with Checker Board Layouts

Thu, 06 Apr 2017 08:00:00 EDT

An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips.



ESD PROTECTION DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

An electrostatic protection includes a buried layer having an outer region and an inner region which are heavily doped regions of a first conductivity type. The inner region is surrounded by an undoped or lightly doped ring region. The ring region is surrounded by the outer region. The device further includes a semiconductor region over the buried layer, a first well of the first conductivity type in the semiconductor region, a first transistor in the semiconductor region, and a second transistor in the semiconductor region. The first well forms a collector of the first transistor and a collector of the second transistor.



HIGH VOLTAGE BIPOLAR STRUCTURE FOR IMPROVED PULSE WIDTH SCALABILITY

Thu, 06 Apr 2017 08:00:00 EDT

According to an embodiment, a bipolar transistor is disclosed for Electrostatic discharge (ESD) management in integrated circuits. The bipolar transistor enables vertical current flow in a bipolar transistor cell configured for ESD protection. The bipolar transistor includes a selectively embedded P-type floating buried layer (PBL). The floating P-region is added in a standard NPN cell. During an ESD event, the base of the bipolar transistor extends to the floating P-region with a very small amount of current. The PBL layer can provide more holes to support the current resulting in decreased holding voltage of the bipolar transistor. With the selective addition of floating P-region, the current scalability of the bipolar transistor at longer pulse widths can be significantly improved.



LED MODULE AND METHOD OF MANUFACTURING THE SAME

Thu, 06 Apr 2017 08:00:00 EDT

A compact LED module and a method of manufacturing such an LED module are provided. The LED module includes a first-pole first lead, a first-pole second lead, a first-pole third lead, a second-pole first lead, a second-pole second lead, a second-pole third lead, a first LED chip, a second LED chip, a third LED chip, and a housing. A distal end of the first-pole first lead is offset toward a second-pole side in a first direction with respect to both a distal end of the second-pole second lead and a distal end of the second-pole third lead.



SEMICONDUCTOR DEVICE HAVING JUMPER PATTERN

Thu, 06 Apr 2017 08:00:00 EDT

According to an exemplary embodiment of the present inventive concept, a semiconductor device is provided as follows. An active region is disposed in one side of a gate line. A non-active region is disposed in the other side of the gate line. A jumper pattern crosses a top portion of the gate line, overlapping the active region and the non-active region. A boundary between the active region and the non-active region is underneath the gate line.