Thu, 23 Feb 2017 08:00:00 ESTA keyboard scanning circuit includes a plurality of switching elements, M scanning lines and N sensing lines. Each of the sensing lines has a common node extended to M transmission lines. A switching element is coupled where one of the transmission lines and one of the scanning lines intersects. Two scanning lines correspondingly coupled through two switching elements to two transmission lines extended from one sensing line are different from each other.
Thu, 23 Feb 2017 08:00:00 ESTA system and method for sampling an RF signal are described. The system comprises a plurality of capacitors, a plurality of resistors, and a sampling circuit. A first port of each capacitor of the plurality of capacitors is coupled to the RF signal. A first port of each resistor of the plurality of resistors is coupled to one of a plurality of reference levels. A second port of each resistor of the plurality of resistors is coupled to a second port of a corresponding capacitor of the plurality of capacitors. The sampling circuit produces a plurality of digital outputs by sampling the second port of each resistor of the plurality of resistors.
Thu, 23 Feb 2017 08:00:00 ESTSystem and method for the calibration of interleave time errors in an n-level PAM Digital to Analog Converter (DAC), according to which a set of two samplers with adjustable sample time and threshold are introduced at the output of the DAC, which are separated in time. The set of samplers is swept through a n unit interval (UI) window and the n-UI window is classified to periods of transitions and non-transitions on an eye diagram. The relative timing of the lower rate clocks into an n:1 multiplexer is controlled using a control loop, to force equal eye width within the n-UI window and the interleaved timing errors are measured and corrected, until the uneven distribution is being reduced below a predetermined level.
Thu, 16 Feb 2017 08:00:00 ESTAn arithmetic encoder is provided for converting an event sequence comprised of a plurality of events to an information sequence comprised of at least one information piece, and includes a core engine for receiving an event of the event sequence, and a probability estimate from a probability estimator, and generating zero or more pieces of the information sequence responsive to the received event and the probability estimate by bounding the ratio of events to information pieces. An arithmetic encoder is provided that is capable of constraining a number of events in at least one event sequence as a function of the number of generated information pieces in at least one information sequence. An arithmetic decoder is provided for converting an information sequence comprised of at least one information piece to an event sequence comprised of a plurality of events, and includes a core engine for processing at least one information piece of the information sequence from the sequencer responsive to a probability estimate received from a probability estimator to generate at least one event by accounting for a bounded ratio of events to information pieces in the information sequence.
Thu, 16 Feb 2017 08:00:00 ESTA method for determining an encoding used for a sequence of bytes may be provided. The method comprises providing a set of candidate code pages and transforming them into different groups of sequences of bytes, wherein each group of sequences of bytes corresponds to one of the candidate code pages. Thereby each code point is transformed by applying a transformation from one of the candidate code pages to a reference code point value relating to a reference encoding for each code point. The method comprises further separating each of the transformed sequences of bytes into groups of tokens, wherein each group of tokens relates to one candidate code page, and providing an index relating to a text corpus. Furthermore, the method comprises selecting a code page from the set of candidate code pages at least partially based on how many tokens are found in the index.
Thu, 16 Feb 2017 08:00:00 ESTReduction in signal intensity of a harmonic component included in an output of a delta-sigma modulator is suppressed. A signal processing device includes: a delta-sigma modulator 11 that outputs a pulse signal; a first processor 12 that generates, from the pulse signal PO outputted from the delta-sigma modulator 11, a discontinuous pulse signal PC in which each of one-pulse sections in the pulse signal PO has a low level region on at least one of a rear end and a front end of the one-pulse section; and a second processor that generates a short-width pulse signal PS having a pulse width shorter than a pulse width of the discontinuous pulse signal PC generated by the first processor 12.
Thu, 16 Feb 2017 08:00:00 ESTA system includes an analog-to-digital converter receiving a plurality of input signals. One particular input signal has a particular analog value and the analog-to-digital converter uses a fixed reference to convert the particular analog value to a particular digital value. The analog-to-digital converter uses the particular analog value as a reference for converting the analog values of the remaining input signals.
Thu, 16 Feb 2017 08:00:00 ESTAnalog-digital converter configured for conversion of an input voltage, represented by a pair of input potentials, into a binary code using successive approximation. The analog-digital converter comprises a reference voltage generator (RVG) supplying a first pair of reference potentials and a second pair of reference potentials. The analog-digital converter further comprises a switched capacitor array (SCA) configured to receive the first and the second pair of reference potentials as well as a control unit (CTRL) coupled to the switched capacitor array (SCA) and configured to switch capacitors of the switched capacitor array (SCA) either to the first pair of reference potentials or to the second pair of reference potentials depending on a progress of the conversion.
Thu, 16 Feb 2017 08:00:00 ESTIn one embodiment, an amplifier is configured to include a pre-drive circuit that forms an estimated value of an output signal of the amplifier and forces the output to the estimated value before the amplifier forms the output signal.
Thu, 16 Feb 2017 08:00:00 ESTThe present disclosure describes a channel selector for use in an analog-to-digital converter that has a sampling circuit for converting an analog input to a digital output within a fault tolerance range. The channel selector includes a reception channel, a diagnostic channel, and an impedance compensator. The reception channel receives an analog signal for delivery to the sampling circuit when it is selected for coupling with the sampling circuit. The diagnostic channel receives a diagnostic signal for verifying the digital output of the sampling circuit when it is selected for coupling with the sampling circuit. The impedance compensator is configured to offset a high channel impedance of the reception channel based on the fault tolerance range of the sampling circuit and when the diagnostic channel is selected.
Thu, 16 Feb 2017 08:00:00 ESTAn analog-to-digital conversion system comprises a first processor, a bank of N analog-to-digital converters, and a second processor. The first processor is configured to receive M input signal streams, perform a wave-front multiplexing transform in analog domain on the M input signal streams and output concurrently N mixed signal streams, M and N being integers and N≧M>1. The wave-front multiplexing transform comprises a first set of wave-front vectors. The bank of N analog-to-digital converters is coupled to the first processor. The N analog-to-digital converters convert the N mixed signal streams from analog format to digital format and output concurrently N digital data streams. The second processor is coupled to the bank of N analog-to-digital converters. The second processor is configured to receive the N digital data streams, perform a wave-front de-multiplexing transform in digital domain on the N digital data streams and output concurrently N output data streams such that the N output data streams comprise M output data streams that correspond respectively to the M input signal streams. The wave-front de-multiplexing transform comprises a second set of wave-front vectors.
Thu, 16 Feb 2017 08:00:00 ESTA capacitive sensitive key structure includes a key, support component, fixing pad, substrate and conductive portion. The key includes a key body and a connection wall which encloses a receiving space. The support component is disposed in the receiving space and includes a body, conical wall, buffering space, and extending pad connected to the conical wall. The body abuts against the key body. The conductive portion is disposed at the bottom of the body and inside the buffering space. The substrate is connected to the fixing pad and has thereon a circuit unit and a sensing layer. The substrate is coated with an insulating layer which covers the sensing layer. When the key body is pressed to press against the support component, electrostatic changes occur because of changes in the distance between the conductive portion and the sensing layer; hence, the circuit unit sends electrical signals for driving electronic apparatuses.
Thu, 09 Feb 2017 08:00:00 ESTA data compression and decompression algorithm performing the function of data compression and decompression by using the steps of: dividing a main data stream into sub data streams, calculating frequency of occurrence of sub data streams in the main data stream, repeating the process of calculating frequency of occurrence by changing the number of digits in sub data stream and by changing the starting digit position in main data stream, assigning codes to sub data streams based on their frequency occurrence values, calculating group dimension index for each group, selecting the group with the lowest group dimension index and placing codes of the group with the lowest group dimension index in a multi dimensional space wherein vector placement is utilized to eliminate the need to use digits that are common to neighboring codes therefore providing an additional compression.
Thu, 09 Feb 2017 08:00:00 ESTAn encoder for compressing input data to generate corresponding encoded data is provided. The encoder is operable to process the input data to identify reoccurrence of mutually similar multi-dimensional patterns of data bits and/or data symbols therein. The encoder is then operable to represent one or more duplicate reoccurrences of the mutually similar multi-dimensional patterns of data bits and/or data symbols by way of one or more duplication symbols uniquely identifying the mutually similar patterns.
Thu, 09 Feb 2017 08:00:00 ESTA method for multi-dimensional modulation of a network protocol including control data and payload data. The method includes encoding a first sine wave with the control data; encoding a second sine wave with the payload data; and summing the first and second sine waves to generate a compound sine wave. In some embodiments, the control data is header information for a first Ethernet packet and post-payload data for a second Ethernet packet; and the payload data is payload data for the second Ethernet packet.
Thu, 09 Feb 2017 08:00:00 ESTThe disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.
Thu, 09 Feb 2017 08:00:00 ESTA digital to analog converter with output impedance compensation has an encoding unit, a current cell array, a summing unit and a compensation unit. The compensation unit is connected to output terminals of the DAC and provides a nonlinear impedance to compensate an original output impedance of the DAC. With the compensated output impedance, the SFDR performance and the linearity of the DAC are improved to obtain a superior input-to-output transfer curve.
Thu, 09 Feb 2017 08:00:00 ESTA driver arrangement (10) comprises a digital controller (11) that is configured to receive a digital input signal (SDI) and a driver (12) that comprises a driver input (14) and a driver output (15) and is configured to provide an analog output signal (SANO) at the driver output (15). The driver arrangement (10) comprises a coupling circuit (13) that comprises a digital-to-analog converter (19) and a feedback circuit (24). The digital-to-analog converter (19) comprises a converter input (20) coupled to the digital controller (11) and a converter output (21) coupled to the driver input (14). The feedback circuit (24) is coupled to the driver output (15) and to a feedback input (17) of the digital controller (11).
Thu, 09 Feb 2017 08:00:00 ESTA successive comparison A/D conversion circuit includes: an comparison circuit including a differential amplification circuit which includes a pair of differential input terminals, amplifies a pair of first differential signals input into the pair of differential input terminals, and outputs a pair of second differential signals, and a latch circuit which compares voltages of the second differential signals output from the differential amplification circuit, retains an comparison result, and outputs the retained comparison result; a digital circuit which generates a digital signal corresponding to the first differential signal, based on the comparison result; an arithmetic circuit which generates a reference signal based on the digital signal, generates the first differential signal by subtracting the reference signal from a third differential signal or adding the reference signal to the third differential signal, and outputs the generated first differential signal to the pair of differential input terminals; and a control circuit.
Thu, 09 Feb 2017 08:00:00 ESTA circuit comprises a successive approximation analog-to-digital converter that comprises a feedback path and is operated for example in accordance with the successive approximation method. The feedback path is configured to translate a digital signal in accordance with a prescribed function and to furthermore convert the translated digital signal into an analog feedback signal. For example, the prescribed function can be an exponential function. As such, it can be possible to convert an input signal into an output signal by means of a nonlinear characteristic.
Thu, 09 Feb 2017 08:00:00 ESTThe disclosure provides a current steering digital to analog converter (DAC) that includes a plurality of DAC elements. At least one DAC element of the plurality of DAC elements is coupled to a calibration circuit. The calibration circuit includes a fixed current source coupled to a primary node of the DAC element through a first estimation switch. A digital code generator is coupled to the primary node, and generates a first digital code corresponding to a primary voltage generated at the primary node. The digital code generator generates a second digital code. A correction DAC is coupled to the digital code generator and generates a bias voltage based on the second digital code. The bias voltage is provided to the DAC element such that a current flowing through each DAC element of the plurality of DAC elements is equal.
Thu, 09 Feb 2017 08:00:00 ESTA system includes an analog-to-digital converter (ADC) including an ADC input terminal; an ADC output terminal; and analog components configured to convert an analog signal received at the ADC input terminal to a digital signal. The system also includes a histogram estimation circuit coupled to the ADC output terminal and configured to generate information on a plurality of codes generated by the ADC and determine a region defining a range of codes corresponding to an occurrence of an error caused by the analog components of the ADC. The system also includes a dither circuit coupled to the ADC input terminal and configured to introduce a dither in the analog signal to generate a modified analog signal.
Thu, 09 Feb 2017 08:00:00 ESTA dual delta-sigma modulator includes a first modulator, a second modulator, and a shared amplifier coupled to the first and second modulators. The first modulator includes an integrator configured to generate a first modulator output signal. The second modulator includes a second integrator configured to generate a second modulator output signal. The shared amplifier is configured to assist the first integrator integrating a difference between a first analog input signal and a first modulator output signal from the first modulator during a first period of time and to assist the second integrator integrate a difference between a second analog input signal and a second modulator output signal from the second modulator during a second period of time.
Thu, 09 Feb 2017 08:00:00 ESTA system. The system includes a first tracking filter configured to track a frequency domain mismatch profile between component analog-to-digital convertors (ADCs) of an interleaved ADC (IADC), and a second tracking filter configured to a track a frequency independent timing delay mismatch and a timing delay mismatch correction error based on frequency domain mismatch profile estimates. An output of the first tracking filter determines a correction of a frequency dependent mismatch profile in an output of the interleaved ADC and an output of the second tracking filter determines a correction of the timing delay mismatch correction error in the output of the interleaved ADC.
Thu, 09 Feb 2017 08:00:00 ESTA method to implement circuits and circuit elements having one or more ports may include digitizing, using analog-to-digital converters, continuous-time input signals received from one or more ports of a circuit to form discrete-time input signals. At a digital signal processor, the discrete-time input signals are received and the discrete-time input signals are processed to calculate a desired discrete-time output signals. Using digital-to-analog converters, the calculated desired discrete-time output signal are calculated to form outputs of continuous-time output signals at the one or more ports of the circuit. The continuous-time output signals are output to the same one or more ports that receive the continuous-time input signals; and producing, thereby, a desired relationship between the continuous-time output signals and the continuous-time input signals at the one or more ports.
Thu, 09 Feb 2017 08:00:00 ESTEmbodiments of the present invention provide a time-to-digital converter, where the time-to-digital converter includes a delay unit, a first sampling unit, and a second sampling unit. The delay unit is connected to the first sampling unit and is configured to receive a first clock signal and delay the first clock signal; the first sampling unit is configured to perform sampling on the first clock signal and generate a first phase signal, so that a first phase-locked module adjusts a frequency of the first clock signal; the delay unit is further connected to the second sampling unit and is configured to receive a frequency-adjusted first clock signal and delay the frequency-adjusted first clock signal; and the second sampling unit is configured to perform sampling on the frequency-adjusted first clock signal and generate a second phase signal.
Thu, 02 Feb 2017 08:00:00 ESTA method includes: first setting a first and a second storage regions; first comparing a compression target data in a file with data in the first storage region; first creating a first compression code of the compression target data based on the data in the first storage region when a predetermined first consistency between the compression target data and the data in the first storage region is detected; second comparing the compression target data with data in the second storage region when the predetermined first consistency between the compression target data and the data in the first storage region is not detected, the compression target data being moved to the second storage region after the second comparing; and first storing the compression target data into the first storage region when a predetermined second consistency between the compression target data and the data in the second storage region is detected.
Thu, 02 Feb 2017 08:00:00 ESTThe invention to mismatch and ISI shaping in a data converter. The invention provides a dynamic element matching technique that incorporates both mismatch and inter symbol interference shaping. A digital decoder is provided that controls the number of ‘on’ and ‘off’ transitions so that the resulting signal does not contain noise or distortion. The element selection technique of the invention is suitable for high resolution multi-bit continuous time oversampling data converters.
Thu, 02 Feb 2017 08:00:00 ESTA delta-sigma modulator includes a signal subtraction circuit, a loop filter, a quantizer, a digital-to-analog converter (DAC), and a control circuit. The signal subtraction circuit subtracts an analog feedback signal from an analog input signal to generate a difference signal. The loop filter performs a filtering operation upon the difference signal to generate a filtered signal. The quantizer quantizes the filtered signal into a digital out put signal, wherein at least one inherent circuit characteristic of the quantizer are adjusted in response to a digital code input. The DAC generates the analog feedback signal according to the digital output signal. The control circuit generates the digital code input to the quantizer for setting an excess loop delay (ELD) compensation.
Thu, 02 Feb 2017 08:00:00 ESTAnalog-to-digital converter (ADC) circuitry includes a first binary-weighted capacitor array having a total capacitance of 2n-2C. The value of n represents number of bits of a digital signal that represents an analog signal. The ADC circuitry also includes a second binary-weighted capacitor array having a total capacitance of 2n-2C. In addition to that, the ADC circuitry further includes a comparator circuit having first and second terminals. The first terminal is coupled to the first binary-weighted capacitor array, and the second terminal is coupled to the second binary weighted capacitor array. The switching circuit within the second binary-weighted capacitor array may be configurable to couple a largest capacitance capacitor within the second binary-weighted capacitor array from remaining capacitors within the second binary weighted capacitor array.
Thu, 26 Jan 2017 08:00:00 ESTA data compression device including a processor to perform a procedure comprising: obtaining data of a predetermined number (Z) of digits in a time series; and performing a compression process on the data. The data is obtained by encoding a vibration state of a measurement target. The compression process includes: deleting upper digits when the upper digits do not include significant information; and adding a unique code to a top of the upper digits when the upper digits include significant information. A digit number (X) of the upper digits is smaller than the predetermined number (Z).
Thu, 26 Jan 2017 08:00:00 ESTA semiconductor device includes an integrator, a successive approximation register analog-to-digital converter (SAR ADC) and a residue capacitor. The integrator is configured to receive a signal and generate a first analog signal during a first operation mode using a capacitor module comprising one or more capacitors. The SAR ADC is configured to receive the first analog signal, convert the first analog signal into a first digital signal using the capacitor module, and generate a first residue signal in a second operation mode. The residue capacitor is connected to the capacitor module in parallel, and is configured to receive the first residue signal in the second operation mode and provide the first residue signal to the integrator in the first operation mode.
Thu, 26 Jan 2017 08:00:00 ESTA device can be used for compensating bandwith mismatches of time interleaved analog to digital converters. A processor of the device determines, for each original sample stream, an estimated difference between the time constant of a low pass filter representative of the corresponding converter and a reference time constant of a reference low pass filter, and uses this estimated difference and a filtered stream to correct the original stream and deliver a corrected stream of corrected samples.
Thu, 26 Jan 2017 08:00:00 ESTA semiconductor device is provided that includes a first chip that generates a single signal by connecting a first signal line and a second signal line, to which differential signals are respectively provided, and outputs the single signal to a third signal line. The first chip is driven by a first power supply voltage. The semiconductor device also includes a second chip comprising an analog-to-digital converter (ADC) that receives the single signal through the third signal line, compares the single signal with a reference voltage, and outputs a digital signal based on the comparison. The semiconductor device also includes a controller that monitors the digital signal and adjusts the reference voltage to be approximately equivalent to the first power supply voltage.
Thu, 19 Jan 2017 08:00:00 ESTThe encoding apparatus registers, in a dynamic dictionary, strings in input text data that are not contained in a static dictionary. The encoding apparatus adds, to first hashed data obtained by individually N-dimensionally hashing words contained as registered items in the static dictionary, hashed data obtained by individually hashing strings registered in the dynamic dictionary. The encoding apparatus 100 determines, by using the first hashed data, whether each input string has been registered in the static dictionary 124 and whether the string has been registered in the dynamic dictionary 122. In accordance with the result of the determination, the encoding apparatus 100 performs encoding based on a content registered in the static dictionary or the dynamic dictionary.
Thu, 19 Jan 2017 08:00:00 ESTA dimensional compression unit 13 multiplies a feature quantity extracted from an image by a check matrix of an error correcting code which consists of binary elements each of which is 0 or 1, to compress the image.
Thu, 19 Jan 2017 08:00:00 ESTA sigma-delta modulator comprising a plurality of filter stages in series with each other, wherein at least one of the plurality of filter stages is configured to provide a filter-output-signal; and a plurality of gain stages, each gain stage configured to provide a gain-output-signal. The sigma-delta modulator also includes a filter-output-switching-element configured to selectively couple the filter-output-signal to an input terminal of one of the plurality of gain stages; and a plurality of filter-input-switching-elements. Each of the plurality of filter-input-switching-elements is associated with one of the plurality of filter stages, wherein the plurality of filter-input-switching-elements are configured to selectively couple one of the gain-stage-output-signals to an input terminal of its associated one of the plurality of filter stages.
Thu, 19 Jan 2017 08:00:00 ESTA multiplying analog to digital converter including an analog to digital converter (ADC) having a sample input and a feedback input and an ADC output configured with a feedback path configured to couple the ADC output to a digital to analog converter. A feedback attenuator is disposed in the feedback path, the feedback attenuator being configured to attenuate a feedback signal coupled to the feedback input, the feedback attenuator being configured to provide analog multiplication observed at the ADC output. A barrel shifter is configured to provide digital multiplication of the ADC output. The feedback attenuator may be configured as a divider network. The feedback attenuator may be configured to provide attenuation using only passive components. The feedback attenuator may be configured as a capacitive divider network. The feedback attenuator may be configured to provide attenuation ranging between 1 and 0.5.
Thu, 19 Jan 2017 08:00:00 ESTThe present invention is directed to data communication. More specifically, embodiments of the present invention provide an offset correction technique for a SERDES system. A CTLE module for receiving input data signal is set to an isolation mode, and one or more sense amplifiers perform data sampling asynchronously during the isolation mode. During the isolation mode, CLTE(s) that are not directly connected to the sense amplifiers are shut. Data sampled during the isolation mode are used to determine an offset value that is later used in normal operation of the SERDES system. There are other embodiments as well.
Thu, 19 Jan 2017 08:00:00 ESTMethods and systems are provided for enhanced digital-to-analog conversions. A segmentation-based digital-to-analog converter (DAC) may be configured for applying digital-to-analog conversions to N-bit inputs. The segmentation-based DAC may comprise a plurality of DAC elements, with each DAC element being operable to apply digital-to-analog conversion based on a single bit, and an encoder operable to generate an x-bit output. The number of DAC elements may be different than number of bits (N) in inputs to the DAC. One or more bits of the N-bit input may be applied to the encoder to generate the x-bit output, with each bit in the x-bit output being applied to a corresponding one of the plurality of DAC elements. Remaining one or more bits of the N-bit input, if any, may be applied directly to a corresponding one or more of the plurality of DAC elements.
Thu, 19 Jan 2017 08:00:00 ESTA switch module of a photoelectric integrated mechanical shaft keyboard, having a casing and a key cap a driving device, a photoelectric switch, a movable optical module and a fixed optical module. The photoelectric switch has a PCB, an SMD IR integrated on the PCB and an SMD PT tube. By pressing down the key cap, the driving device drives the movable optical module to move up and down to control the relative positions of the movable optical module and the fixed optical module. When light emitted by the SMD IR tube is coupled into the SMD PT tube, an optical path is connected, so that the photoelectric switch is turned on and when the light emitted by the SMD IR tube cannot be coupled into the SMD PT tube, the optical path is disconnected, so that the photoelectric switch is turned off.
Thu, 12 Jan 2017 08:00:00 ESTRepresentative implementations of devices and techniques provide gain calibration for analog to digital conversion of time-discrete analog inputs. An adjustable capacitance arrangement is used to reduce or eliminate gain error caused by capacitor mismatch within the ADC. For example, the capacitance arrangement may include an array of multiple switched capacitances arranged to track gain error during search algorithm operation.
Thu, 12 Jan 2017 08:00:00 ESTAn A/D converter including first and second A/D converters and a recombination module. The first A/D converter receives an analog input signal, converts the analog input signal to a first digital signal, and includes a successive approximation module, which performs a successive approximation to generate the first digital signal. The second A/D converter converts an analog output of the first A/D converter to a second digital signal. The analog output of the first A/D converter is generated based on the analog input signal. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter. The second A/D converter performs the delta-sigma conversion process and includes a decimation filter that suppresses noise which reduces amplification and power consumption requirements of the first A/D converter and performs a delta-sigma decimation process to generate the second digital signal based on the analog output of the first A/D converter.
Thu, 12 Jan 2017 08:00:00 ESTA hybrid D/A converter is provided including first and second D/A converters. The first D/A converter receives a digital signal having an input voltage and converts a first most-significant-bit of the digital signal to be converted to an analog signal. The first D/A converter includes first capacitors, which are charged by the input voltage and reference voltages during a sampling phase of the digital signal. Charges of the first capacitors are shared during successive approximations of first bits of the digital input signal received by the hybrid D/A converter. The second D/A converter converts a first least-significant-bit of the digital input signal. The second D/A converter includes second capacitors, which are charged based on a common mode voltage during the sampling phase. The second D/A converter performs charge redistribution by connecting the second capacitors to receive the reference voltages during successive approximations of second bits of the digital signal.
Thu, 12 Jan 2017 08:00:00 ESTOne or more first signals and one or more second signals, wherein the second signal(s) are slowly varying or low frequency signals in comparison with the first signals and are converted from analog to digital by sampling the first signals and the second signals to produce samples thereof for analog-to-digital conversion, subjecting the samples of the first signals to conversion to digital at a certain conversion rate, subjecting the samples of the second signal to conversion to digital by segments so that these segments are subjected to conversion to digital along with the samples of the first signals at the respective conversion rate, and reconstructing digital converted samples of the second signal from the segments subjected to conversion to digital.
Thu, 12 Jan 2017 08:00:00 ESTA pipeline analog-to-digital converter (ADC) converts an analog input signal over several stages, where a stage generates a residue for the subsequent stage to digitize. The residue is generated by coarsely quantizing the analog input signal to generate a digital code, which is used to reconstruct the analog input signal, and the residue is the difference between the analog input signal and the reconstructed version of the analog input signal. The coarse quantization can have errors which are attributed to comparator offsets and bandwidth mismatch. To estimate the comparator offsets while being insensitive to bandwidth mismatch, peak and trough detectors are used to track maximum and minimum values of the residue or the output of the ADC over time, and an expected value estimating the comparator offset can be computed based on the maximum and minimum values. The expected value advantageously “averages” out the bandwidth mismatch contribution to the offset.
Thu, 12 Jan 2017 08:00:00 ESTAn A/D converter including a sample and hold circuit, first and second A/D converters and a combination circuit. The sample and hold circuit samples an analog input signal to generate bits. The first A/D converter generate a first digital signal based on the analog input signal and includes charge-sharing and charge-redistribution D/A converters that convert respectively a most-significant-bit and a first least significant bit. The first digital signal is generated based on outputs of the charge-sharing and charge redistribution D/A converters. The second A/D converter generates a second digital signal based on an output of the first A/D converter and includes a delta sigma D/A converter, which converts a second least significant bit. The second digital signal is generated based on an output of the delta sigma D/A converter. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter.
Thu, 12 Jan 2017 08:00:00 ESTThe present invention relates to nonlinear signal processing, and, in particular, to adaptive nonlinear filtering of real-, complex-, and vector-valued signals utilizing analog Nonlinear Differential Limiters (NDLs), and to adaptive real-time signal conditioning, processing, analysis, quantification, comparison, and control. More generally, this invention relates to methods, processes and apparatus for real-time measuring and analysis of variables, and to generic measurement systems and processes. This invention also relates to methods and corresponding apparatus for measuring which extend to different applications and provide results other than instantaneous values of variables. The invention further relates to post-processing analysis of measured variables and to statistical analysis. The NDL-based filtering method and apparatus enable improvements in the overall properties of electronic devices including, but not limited to, improvements in performance, reduction in size, weight, cost, and power consumption, and, in particular for wireless devices, NDLs enable improvements in spectrum usage efficiency.
Thu, 05 Jan 2017 08:00:00 ESTDescribed is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.
Thu, 05 Jan 2017 08:00:00 ESTA successive approximation ADC capable of reducing deterioration in AD conversion accuracy due to noise is provided. An AD converter according to an embodiment includes: a DA converter that generates a comparison voltage based on a sampling value obtained by sampling an analog signal, and a successive approximation control signal; a reference voltage generation circuit that generates a reference voltage used for the successive approximation process; a comparator that compares the comparison voltage with the reference voltage and outputs a successive approximation result; a successive approximation processing unit that generates the successive approximation control signal based on the successive approximation result; and a storage unit that stores an expected value of the AD conversion process. The reference voltage generation circuit generates the reference voltage based on the expected value stored in the storage unit.