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SYSTEM, APPARATUS, AND METHOD FOR DECOMPRESSING DATA

Thu, 25 Aug 2016 08:00:00 EDT

A system for data decompression may include a processor coupled to a remote memory having a remote dictionary stored thereon and coupled to a decompression logic having a local memory with a local dictionary. The processor may decompress data during execution by accessing the local dictionary, and if necessary, the remote dictionary.



SYSTEM AND METHOD FOR COMPRESSING DATA USING ASYMMETRIC NUMERAL SYSTEMS WITH PROBABILITY DISTRIBUTIONS

Thu, 25 Aug 2016 08:00:00 EDT

A data compression method using the range variant of asymmetric numeral systems to encode a data stream, where the probability distribution table is constructed using a Markov model. This type of encoding results in output that has higher compression ratios when compared to other compression algorithms and it performs particularly well with information that represents gene sequences or information related to gene sequences.



MULTIPLYING ANALOG TO DIGITAL CONVERTER AND METHOD

Thu, 25 Aug 2016 08:00:00 EDT

A multiplying analog to digital converter (ADC) including a successive-approximation-register (SAR) analog to digital converter (ADC) having a sample input and a feedback input and an ADC output configured with a feedback path configured to couple the ADC output to a digital to analog converter. A feedback attenuator is disposed in the feedback path, the feedback attenuator being configured to attenuate a feedback signal coupled to the feedback input, the feedback attenuator being configured to provide analog multiplication observed at the ADC output. A barrel shifter is configured to provide digital multiplication of the ADC output. The feedback attenuator may be configured as a divider network. The feedback attenuator may be configured to provide attenuation using only passive components. The feedback attenuator may be configured as a capacitive divider network. The feedback attenuator may be configured to provide attenuation ranging between 1 and 0.5.



A/D CONVERSION DEVICE

Thu, 25 Aug 2016 08:00:00 EDT

An A/D conversion device includes: a level shifter circuit configured to level-shift an analog voltage of an input voltage signal to generate a conversion signal; an A/D converter configured to A/D-convert a voltage of the conversion signal supplied from the level shifter circuit. The level shifter circuit subtracts an instantaneous voltage value of the input voltage signal from a reference voltage so as to output a signal value as the conversion signal.



Circuit and Method for Comparator Offset Error Detection and Correction in an ADC

Thu, 25 Aug 2016 08:00:00 EDT

A method includes sampling an input voltage signal applied to an ADC, comparing the sampled input voltage signal with an output signal of a feedback DAC, and determining in a search logic block a digital code representation for the comparison result. The method may also include performing a calibration by: performing an additional cycle, wherein a last comparison carried out for determining a least significant bit of the digital code representation is repeated with a second comparator resolution mode different from a first comparator resolution mode, so obtaining an additional comparison; determining from a difference between results of the additional comparison and the last comparison a sign of a comparator offset error between the comparator resolution modes; and tuning, in accordance with a sign of the comparator offset error, a programmable capacitor connected at an input of the comparator, thereby inducing a voltage step to counteract the comparator offset error.



NARROWBAND ANALOG NOISE CANCELLATION

Thu, 25 Aug 2016 08:00:00 EDT

A method, including receiving an input analog signal containing noise at a specific noise frequency and digitizing the input analog signal to form a digitized signal. The method also includes recovering a first amplitude and a first phase of the noise from the digitized signal, and generating an analog correction signal at the specific noise frequency. The analog correction signal has a second amplitude equal to the first amplitude and a second phase opposite to the first phase. The method further includes summing the input analog signal with the analog correction signal to generate an output analog signal.



A/D CONVERTER CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT

Thu, 25 Aug 2016 08:00:00 EDT

An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.



ERROR-FEEDBACK DIGITAL-TO-ANALOG CONVERTER (DAC)

Thu, 25 Aug 2016 08:00:00 EDT

In one embodiment, a method for converting an input digital signal into an analog signal is provided. The method comprises modulating the input digital signal into a modulated digital signal, and converting the modulated digital signal into the analog signal using a digital-to-analog converter (DAC). The modulation shapes quantization noise of the DAC to place a notch at a frequency within an out-of-bound frequency band to reduce the quantization noise within the out-of-bound frequency band.



SIGNAL MODULATION CIRCUIT

Thu, 18 Aug 2016 08:00:00 EDT

Provided is a modulation circuit that can correct an output state in real time and reliably modulate an input signal to output the modulated signal. The signal modulation circuit includes a subtractor, an integrator, a chopper circuit, a frequency divider, and a D-type flip-flop. A delay circuit of a sigma delta modulation circuit is not provided to a feedback circuit, and a signal is delayed and quantized in the D-type flip-flop. The chopper circuit inserts a zero level at timing synchronized with a clock signal, so that pulse density modulation is performed.



ASYNCHRONOUS SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND INTERNAL CLOCK GENERATOR INCLUDED THEREIN

Thu, 18 Aug 2016 08:00:00 EDT

An asynchronous successive approximation register analog-to-digital converter and an internal clock generator included in the same are disclosed. The internal clock generator in an SAR ADC comprises a detection unit configured to generate an up pulse or a down pulse by sensing generation time of a final internal clock and next external clock; and a delay block configured to increase or decrease delay time by controlling a bias voltage according to the generated up pulse or the generated down pulse.



TWO-STAGE DIGITAL DOWN-CONVERSION OF RF PULSES

Thu, 18 Aug 2016 08:00:00 EDT

A two-stage digital down-conversion device for optimal detection of varying RF pulses incorporates a front end analog to digital converter (ADC), which samples an input RF signal and performs a first stage digital down conversion in wide bandwidth by means of two digital local oscillator multipliers, low pass filters and decimators. A stream of first stage quadrature I and Q samples is analyzed by a first stage I/Q processor. The I/Q processor generates an RF pulse trigger based on a first-stage envelope signal, center frequency and frequency span data which are used for a second stage narrow band digital down-conversion. The second stage digital down-conversion is based on mixing the first stage I and Q data samples with a second stage local oscillator, further low pass filtering and decimation using a second bandwidth. A stream of second stage I/Q quadrature samples has an optimal signal to noise ratio and allows accurate estimation of RF pulse parameters (magnitude, phase and frequency) by means of a second I/Q signal processor and/or by storing second I/Q data for subsequent processing and analysis.



Efficient Context Save/Restore During Hardware Decompression of DEFLATE Encoded Data

Thu, 11 Aug 2016 08:00:00 EDT

An approach is provided in which a hardware accelerator receives a request to decompress a data stream that includes multiple deflate blocks and multiple deflate elements compressed according to block-specific compression configuration information. The hardware accelerator identifies a commit point that is based upon an interruption of a first decompression session of the data stream and corresponds to one of the deflate blocks. As such, the hardware accelerator configures a decompression engine based upon the corresponding deflate block's configuration information and, in turn, recommences decompression of the data stream at an input bit location corresponding to the commit point.



VLSI EFFICIENT HUFFMAN ENCODING APPARATUS AND METHOD

Thu, 11 Aug 2016 08:00:00 EDT

A compression algorithm based on Huffman coding is disclosed that is adapted to be readily implemented using VLSI design. A data file may be processed to replace duplicate data with a copy commands including an offset and length, such as according to the LV algorithm. A Huffman code may then be generated for parts of the file. The Huffman code may be generated according to a novel method that generates Huffman code lengths for literals in a data file without first sorting the literal statistics. The Huffman code lengths may be constrained to be no longer than a maximum length and the Huffman code may be modified to provide an acceptable overflow probability and be in canonical order. Literals, offsets, and lengths may be separately encoded. The different values for these data sets may be assigned to a limited number of bins for purpose of generating usage statistics used for generating Huffman codes.



DATA COMPRESSION APPARATUS AND DATA DECOMPRESSION APPARATUS

Thu, 11 Aug 2016 08:00:00 EDT

The present invention guarantees throughput for decompressing compressed data. A data compression apparatus includes: a division unit that divides plaintext data inputted to the division unit into a plurality of plaintext blocks each having a prescribed plaintext block length; a compression unit that creates a payload for each plaintext block of the plurality of plaintext blocks by compressing the plaintext block using a sliding dictionary-type compression algorithm, creates a header indicating the length of the payload, and creates a compression block that includes the header and the payload; and a concatenation unit that creates compressed data by concatenating a plurality of compression blocks created from the plurality of plaintext blocks.



LOW POWER ANALOG TO DIGITAL CONVERTER

Thu, 11 Aug 2016 08:00:00 EDT

Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.



High Bandwidth Oscilloscope

Thu, 11 Aug 2016 08:00:00 EDT

A method for improving bandwidth of an oscilloscope involves, in preferred embodiments, the use of frequency up-conversion and down-conversion techniques. In an illustrative embodiment the technique involves separating an input signal into a high frequency content and a low frequency content, down-converting the high frequency content in the analog domain so that it may be processed by the oscilloscope's analog front end, digitizing the low frequency content and the down-converted high frequency content, and forming a digital representation of the received analog signal from the digitized low frequency content and high frequency content.



CIRCUIT AND METHOD OF ADAPTIVE FILTERING DIGITAL CALIBRATION OF ADC

Thu, 11 Aug 2016 08:00:00 EDT

An adaptive filtering digital calibration circuit of ADC, which includes a control module, a fixed-point adder, and a fixed-point multiplier; the control module includes a finite-state machine, a shift register, and a register array; the fixed-point adder allows an addend and an augend to be added together after being encoded; the control module controls to complete all the calibration algorithmic operation, which includes the following steps: the control module controls to obtain an original binary value from an external ADC; calculating an error value according to weight and disturbance signals, and carrying out the weight updating operation and the disturbance signal updating operation according to the error value; carrying out the gain calibration operation; and carrying out the final result operation. The present invention also discloses a method of the adaptive filtering digital calibration of ADC.



Cross-Coupled Input Voltage Sampling and Driver Amplifier Flicker Noise Cancellation in a Switched Capacitor Analog-to-Digital Converter

Thu, 11 Aug 2016 08:00:00 EDT

A switching component comprises a plurality of switches configured to receive a differential signal at an input and is configured to provide a non-inverted version of the differential signal at an output during a first phase of operation and an inverted version of the differential signal at an output during a second phase of operation. A driver amplifier component is configured to receive the non-inverted version of the differential signal at an input during the first phase of operation and the inverted version of the differential signal at an input during the second phase of operation. A sampling capacitor component is configured to sample the output of the driver amplifier component during the first phase of operation and the second phase of operation.



Method and Apparatus for Excess Loop Delay Compensation in Continuous-Time Sigma-Delta Analog-to-Digital Converters

Thu, 11 Aug 2016 08:00:00 EDT

A CT-SDADC of the present disclosure converts the analog input signal from a representation in an analog signal domain to a representation in a digital signal domain to provide the digital output signal. The CT-SDADC achieves the analog-to-digital conversion and ELDC by switching between two phases in the SAR sub-ADC: a sampling phase and a conversion phase. During the sampling phase, the SAR sub-ADC captures the analog input signal across multiple arrays of switchable capacitors. The conversion phase comprises a number of steps, and one or more bits of the digital output signal are resolved at each step of the conversion phase. A portion of the SC-DAC is driven by the delayed CT-SDADC output during the conversion phase to effectively compensate for excess loop delay caused by the CT-SDADC feedback loop.



FREQUENCY DIVIDING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT

Thu, 11 Aug 2016 08:00:00 EDT

A plurality of latch circuits driven at rising of a clock signal and a plurality of latch circuits driven at falling of the clock signal are alternately connected, and generation circuit generates a plurality of frequency divided clock signals with different phases based on combinations of levels of outputs of the plurality of latch circuits.



Touch-on-Metal Keypad with N-1 Key Scan Averaging

Thu, 04 Aug 2016 08:00:00 EDT

For touch-on-metal (ToM) apparatus, an N-1 key scan averaging (with baseline drift compensation) technique, including: (a) during successive key-scan periods, scanning each N key-touch sense circuits, to determine a respective touch-key sense signal, including a key-press sense signal, determine a respective touch-key baseline value based on the touch-key sense signal independent of any key-press condition; and (b) during each key-scan period, for each touch key averaging the touch-key baseline values for the other N-1 touch-keys to generate a respective N-1 key-scan average value, comparing the touch-key sense signal to a threshold value based on the respective N-1 key-scan average value, and signaling a key-press condition if at least one touch-key output signal is greater in magnitude than the respective N-1 key-scan average value by the threshold value. Touch-key baseline values can be determined by incrementing the touch-key baseline value if the touch-key sense signal is greater than the touch-key baseline value, decrementing the touch-key baseline value if the touch-key sense signal is less than the touch-key baseline value, and generating the normalized touch-key baseline value by subtracting the touch-key baseline value from the touch-key sense signal.



ENCODING METHOD AND ENCODING DEVICE

Thu, 04 Aug 2016 08:00:00 EDT

An encoding device searches input text data for a date-time notation string that represents at least a date or time. The encoding device generates, upon finding the date-time notation string by the search unit, a converted date and time code including an identification code for identifying the date-time notation string and a normalized date and time notation formed by converting the date-time notation string into a specific date-time notation format. The encoding device converts the input text data based on conversion information that associates the converted date-time code generated by the generation unit with the date-time notation string.



NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM, COMPRESSION METHOD, DECOMPRESSION METHOD, COMPRESSION DEVICE, AND DECOMPRESSION DEVICE

Thu, 04 Aug 2016 08:00:00 EDT

At a preliminary stage, a compressing unit generates frequency information, outputs a compression code associated with a piece of first data of the longest matching character string among the pieces of first data contained in the frequency information, when the longest matching character string has a length smaller than the predetermined length and outputs a compression code associated with a piece of position information matching with position information about the longest matching character string among the pieces of position information about the second data contained in the frequency information and a compression code associated with length information about the longest matching character string among the pieces of first data contained in the frequency information, when the longest matching character string has a length equal to or larger than the predetermined length.



SYSTEM AND METHOD FOR DIGITAL SIGNALING

Thu, 04 Aug 2016 08:00:00 EDT

Systems and methods for communicating digital data over a group of conductors include encoding data based on electromagnetic parameter values associated with two or more group symbols each having an independent encoding value such that a mathematical function of the encoding values in the group symbols yields a known value and communicating the encoded data by applying signals associated with the electromagnetic parameter values to the group of conductors.



ADAPTIVE COMPRESSION OF DATA

Thu, 04 Aug 2016 08:00:00 EDT

A method of encoding data includes determining a magnitude of change between a first value associated with first data and a second value associated with second data based on a comparison of the first value and the second value. The first value is encoded into a first set of bits having a first number of bits. The method also includes encoding the magnitude of change into a second set of bits utilizing a sign-interspersed two's complement encoding scheme. The second set of bits has a second number of bits that is less than the first number of bits



ADAPTIVE COMPRESSION OF DATA

Thu, 04 Aug 2016 08:00:00 EDT

A method of encoding data includes determining a magnitude of change between a first value associated with first data and a second value associated with second data based on a comparison of the first value and the second value. The first value is encoded into a first set of bits having a first number of bits. The method includes determining, based on the comparison of the first value and the second value, a second number of bits (that is less than the first number of bits) to be used to encode the magnitude of change. The method includes encoding the magnitude of change into a second set of bits having the second number of bits. The method further includes sending the second set of bits and a first indicator, with the first indicator indicating that the magnitude of change is encoded into the second number of bits.



COMPRESSION OF INTEGER DATA USING A COMMON DIVISOR

Thu, 04 Aug 2016 08:00:00 EDT

According to one embodiment of the present invention, a system for compressing data determines a common divisor for a set of values comprising integers. The system divides each value within the set of values by the common divisor to produce reduced values, and represents the set of values in the form of data indicating the common divisor and the reduced values. Embodiments of the present invention further include a method and computer program product for compressing data in substantially the same manners described above.



NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM, COMPRESSION METHOD, DECOMPRESSION METHOD, COMPRESSION DEVICE AND DECOMPRESSION DEVICE

Thu, 04 Aug 2016 08:00:00 EDT

An information processing apparatus according to an embodiment determines whether a target character string is registered in a first dictionary, the target character string being a compression target contained in input data, outputs a compression code corresponding to the target character string when the target string is registered in the first dictionary, searches the target character string in first data when the target character string is not registered in the first dictionary, the first date accumulating character strings that are a part of the input data and have been determined to be not registered in the first dictionary, registers a matched character string in a second dictionary different from the first dictionary when the target character string is searched in the first data and outputs a compression code corresponding to a registration number of the target character string in the second dictionary.



D/A CONVERSION CIRCUIT, OSCILLATOR, ELECTRONIC APPARATUS, AND MOVING OBJECT

Thu, 04 Aug 2016 08:00:00 EDT

A D/A conversion circuit includes a plurality of resistors that are formed on a semiconductor substrate and that are connected in series to each other and a plurality of switches that are connected to the plurality of resistors, respectively, in which the plurality of resistors are configured using resistive element and a plurality of contacts that are provided to the resistive element, in which the plurality of switches are arranged side by side along a first direction when the semiconductor substrate is viewed from above, in which distances in the first direction between the plurality of contacts are equal to each other, and in which lengths in a second direction that is perpendicular to the first direction, of the plurality of resistors are unequal to each other.



SUCCESSIVE APPROXIMATION RESISTER ANALOG-TO-DIGITAL CONVERTER HAVING SEPARABLE DUAL CAPACITOR ARRAY

Thu, 04 Aug 2016 08:00:00 EDT

A successive approximation register analog-to-digital converter including separable dual capacitor array is disclosed. The disclosed successive approximation register analog-to-digital converter comprises: a dual capacitor array configured to include a first capacitor array for converting most significant hits of n bits and a second capacitor array for converting least significant bits of the n bits; a comparator configured to compare a level signal outputted from the first capacitor array with a level signal outputted from the second capacitor array; and an SAR logic circuit configured to convert an analog input voltage into a digital signal having the n bits by using the comparison result. Here, the first capacitor array includes a 1-1 capacitor circuit and a 1-2 capacitor circuit and the second capacitor array includes a 2-1 capacitor circuit and a 2-2 capacitor circuit. Each of the capacitor circuits includes capacitors connected in parallel each other.



SWITCH CIRCUIT, ANALOG-TO-DIGITAL CONVERTER, AND INTEGRATED CIRCUIT

Thu, 04 Aug 2016 08:00:00 EDT

A switch circuit includes: a sampling transistor including a source connected to an input node and a drain connected to an output node; a control circuit which is connected to a gate of the sampling transistor and configured to control turning on or off of the sampling transistor; a voltage holding circuit which is provided between the gate and the source of the sampling transistor and configured to maintain a voltage between the gate and the source of the sampling transistor constant when the sampling transistor is turned on; and a protection circuit which is provided in parallel to the control circuit and configured to lower a voltage that is applied to the gate of the sampling transistor when the sampling transistor makes a transition from on to off.



SYSTEM FOR ANALYSING THE FREQUENCY OF A SIGNAL, A METHOD THEREOF AND A SYSTEM FOR MEASURING THE RELATIVE PHASE BETWEEN TWO INPUT SIGNALS

Thu, 04 Aug 2016 08:00:00 EDT

There is provided a frequency analysis system, comprising: an analogue to digital converter having a sampling frequency fs; a first band pass filter and a second band pass filter, the first band pass filter and the second band pass filter being arranged in parallel with one another; and a feedback loop from an output to an input of the system, wherein the system has an initial centre frequency equal to a nominal frequency f0, and a revised centre frequency dependent upon the output of the system that is fed back into the input of the system, wherein the transfer functions of the first and second band pass filters have the same poles, and wherein the system is configured such that, when the centre frequency fc equals the frequency of the signal fi the output of the first band pass filter is in phase with the input, the output of the second band pass filter lags the output of the first band pass filter at a constant phase of π2, and the two band pass filters have equal gain amplitude. There is also provided a method for analysing the frequency fi of a signal and a phase measurement system based on the frequency analysis system.



METHOD AND APPARATUS FOR DENSE HYPER IO DIGITAL RETENTION

Thu, 28 Jul 2016 08:00:00 EDT

System and method to encode and decode raw data. The method to encode includes receiving a block of uncoded data, decomposing the block of uncoded data into a plurality of data vectors, mapping each of the plurality of data vectors to a respective bit marker, wherein the respective bit marker is shorter than said respective mapped data vector, and storing the bit marker in a memory to produce an encoded representation of the uncoded data. Encoding may further include decomposing the block of uncoded data into default data and non-default data, and mapping only the non-default data. In some embodiments, bit markers may include a seed value and replication rule, or a fractalized pattern.



PAD ENCODING AND DECODING

Thu, 28 Jul 2016 08:00:00 EDT

A system, method and computer program product for encoding an input string of binary characters representing alphanumeric characters. A system includes: a register for storing a multi-dimensional cellular shape definition including a starting empty cell; a character writing engine for writing a binary character to an empty cell with a predefined initial position; a next cell determination engine for determining a next empty cell by traversing neighboring cells in the multi-dimensional shape until an empty cell is located; a loop facilitator for looping back to the character writing engine and the next cell determining engine until there are no more data characters or a next empty cell is not determined; and a serialization engine for serializing the multi-dimensional cells into a one dimensional binary string of characters representing an encoded string of alphanumeric characters.



PROCESSING SYSTEM WITH ENCODING FOR PROCESSING MULTIPLE ANALOG SIGNALS

Thu, 28 Jul 2016 08:00:00 EDT

A system for converting several analog signals to digital signals using a single analog to digital converter. Each of the analog signals is encoded, using multiplication, with a different binary code, and the encoded analog signals are summed, and converted to digital form by an analog to digital converter. Multiple digital data streams are then formed from the digital output stream produced by the analog to digital converter, by forming correlations of the digital output stream with each of the binary codes.



SIGNAL PROCESSING APPARATUS AND METHOD

Thu, 28 Jul 2016 08:00:00 EDT

A signal processing apparatus and a method are disclosed, in which the signal processing apparatus may convert an analog signal to a digital signal and store the digital signal. The signal processing apparatus may convert analog signals, transmitted by multiple analog channels, to digital signals using analog-to-digital converters (ADCs), hold the digital signals for a predetermined holding time, sequentially read the held digital signals for each digital channel, and store the sequentially read digital signals.



BUILT IN SELF-TEST

Thu, 28 Jul 2016 08:00:00 EDT

A method for testing a DAC comprising controlling the DAC digitally to cause it to produce a known desired analogue output, for example a fixed amplitude sine wave; determining the duration of fixed voltage segments of the actual output of the DAC and using the duration of the fixed voltage segments to assess or determine performance of the DAC.



ADC AND ANALOG-TO-DIGITAL CONVERTING METHOD

Thu, 28 Jul 2016 08:00:00 EDT

An analog-to-digital converter includes a successive approximation converter, a voltage comparator, and a controller. The successive approximation converter receives an analog input voltage and a first reference voltage, determines the level of a voltage of a first node as a negative level of the analog input voltage, and using a successive approximation method determines an output logic value corresponding to one bit of the N-bit output digital code at every one successive approximation cycle while adjusting the level of the voltage of the first node based on a level of the first reference voltage. The voltage comparator compares the level of the voltage of the first node with a level of a second reference voltage to generate a comparison logic value. When the output logic value or the comparison logic value satisfies a condition, the controller terminates conversion and determines the N-bit output digital code.



SYSTEM AND METHOD FOR LOW-POWER DIGITAL SIGNAL PROCESSING

Thu, 21 Jul 2016 08:00:00 EDT

A system and method for low-power digital signal processing, for example, comprising adjusting a digital representation of an input signal.



CONVERTING DEVICE AND CONVERTING METHOD

Thu, 21 Jul 2016 08:00:00 EDT

An information processing apparatus receives a compressed file in which character string data with a first character code is compressed by a unit of character string including a single character or a plurality of characters. The information processing apparatus converts compression information included in the compressed file into converted compression information, the compression information mapping each of compressed character string data in the compressed file to each of corresponding unit of character string with the first character code, thereby the converted compression information mapping each of the compressed character string data in the compressed file to each of the corresponding unit of character string with a second character code. The information processing apparatus generates a converted compression file from the converted compression information and each of the compressed character string data.



SYSTEM AND METHOD FOR MEASURING THE DC-TRANSFER CHARACTERISTIC OF AN ANALOG-TO-DIGITAL CONVERTER

Thu, 21 Jul 2016 08:00:00 EDT

Systems and methods for measuring and compensating a DC-transfer characteristic of analog-to-digital converters are described. A test-signal generator comprising a sigma-delta modulator may provide calibration signals to an ADC. An output from the ADC may be filtered with a notch filter to suppress quantization noise at discrete frequencies introduced by the sigma-delta modulator. The resulting filtered signal may be compared against an input digital signal to the test-signal generator to determine a transfer characteristic of the ADC.



D/A CONVERSION CIRCUIT, OSCILLATOR, ELECTRONIC APPARATUS, AND MOVING OBJECT

Thu, 21 Jul 2016 08:00:00 EDT

A D/A conversion circuit includes a plurality of resistors that are connected to each other in series, and a plurality of MOS transistors that are connected to terminals of the plurality of resistors, respectively. The plurality of resistors and the plurality of MOS transistors are formed on a semiconductor substrate. Each of the plurality of resistors is constituted by a resistive element and a plurality of contacts provided in the resistive element. The plurality of MOS transistors are disposed so that a plurality of virtual straight lines that pass through each of the plurality of contacts and are perpendicular to a longitudinal direction of the resistive element pass between gate electrodes of two adjacent MOS transistors, when seen in a plan view of the semiconductor substrate.



D/A CONVERSION CIRCUIT, OSCILLATOR, ELECTRONIC APPARATUS, AND MOVING OBJECT

Thu, 21 Jul 2016 08:00:00 EDT

A D/A conversion circuit includes a plurality of resistors connected to each other in series, a plurality of MOS transistors connected to each other so as to correspond to a plurality of contacts, and a plurality of dummy electrodes respectively disposed on sides opposite to the plurality of MOS transistors with a resistive element interposed therebetween when seen in a plan view of a semiconductor substrate. Each of the dummy electrodes is set to be in a second potential state when a gate electrode of the MOS transistor disposed on a side opposite thereto with the resistive element interposed therebetween is in a first potential state, and is set to be in a first potential state when the gate electrode of the MOS transistor is in a second potential state.



HYBRID PIPELINED ANALOG-TO-DIGITAL CONVERTER

Thu, 21 Jul 2016 08:00:00 EDT

An analog-to-digital converter (ADC) that comprises a first ADC stage and a second ADC stage. The first ADC stage comprises a successive approximation register (SAR). The first ADC is configured to convert an analog input signal into a first digital signal corresponding to a most-significant-bits (MSB) portion of a digital output signal. The first ADC stage is also configured to generate a residual voltage corresponding to a difference between a voltage value of the analog input signal and the first digital signal. The second ADC stage comprises a plurality of time-to-digital converter (TDC) cells coupled in series. The second ADC is configured to convert the residual voltage into a plurality of second digital signals generated by the TDC cells. The second digital signals correspond to a least-significant-bits (LSB) portion of the digital output signal. The digital output signal is a digital representation of the analog input signal.



Analog to Digital Converter Circuits and Methods of Operation Thereof

Thu, 21 Jul 2016 08:00:00 EDT

An analog to digital converter (ADC) circuit includes an input stage for supplying an input signal to an ADC for conversion to a digital signal and a control unit of the ADC. The ADC circuit further includes an operational parameter setting device configured to receive an operational parameter setting signal indicative of an operating parameter for the input stage from the control unit. The operational parameter setting device is configured to set an operating parameter for the input stage based on the operational parameter setting signal.



DIGITALLY-CORRECTED ANALOG-TO-DIGITAL CONVERTERS

Thu, 21 Jul 2016 08:00:00 EDT

A method and apparatus for a digitally-corrected analog-to-digital converter (ADC) are disclosed. The apparatus comprises a nonlinearity generator that generates one or more nonlinear characteristics of a time varying input signal and that causes unwanted signal components at frequencies other than a frequency of the time varying input signal, a frequency modifier coupled to the nonlinearity generator that modifies the unwanted signal components by altering an amplitude of the unwanted signal components, a frequency compensator coupled to the frequency modifier, wherein the frequency compensator compensates for the modification introduced by the frequency modifier to provide a filtered digital signal, and an inverse nonlinearity generator coupled to the frequency compensator for receiving the filtered digital signal, wherein the inverse nonlinearity generator compensates for the one or more nonlinear characteristics.



HIERARCHICAL DATA COMPRESSION AND COMPUTATION

Thu, 14 Jul 2016 08:00:00 EDT

According to embodiments of the present invention, machines, systems, methods and computer program products for hierarchical compression of data are presented comprising creating a compression hierarchy of compression nodes, wherein each compression node is associated with a compression operation to produce compressed data. An output of any of the compression nodes may be compressed by another compression node or the same compression node. A path of one or more compression nodes is determined through said compression hierarchy based upon compression statistics to compress data, and the data is compressed by the compression nodes of the path. Various computational techniques are presented herein for manipulating the compression hierarchy to defer or reduce computation during query evaluation.



HIERARCHICAL DATA COMPRESSION AND COMPUTATION

Thu, 14 Jul 2016 08:00:00 EDT

According to embodiments of the present invention, machines, systems, methods and computer program products for hierarchical compression of data are presented comprising creating a compression hierarchy of compression nodes, wherein each compression node is associated with a compression operation to produce compressed data. An output of any of the compression nodes may be compressed by another compression node or the same compression node. A path of one or more compression nodes is determined through said compression hierarchy based upon compression statistics to compress data, and the data is compressed by the compression nodes of the path. Various computational techniques are presented herein for manipulating the compression hierarchy to defer or reduce computation during query evaluation.



HIERARCHICAL DATA COMPRESSION AND COMPUTATION

Thu, 14 Jul 2016 08:00:00 EDT

According to embodiments of the present invention, machines, systems, methods and computer program products for hierarchical compression of data are presented comprising creating a compression hierarchy of compression nodes, wherein each compression node is associated with a compression operation to produce compressed data. An output of any of the compression nodes may be compressed by another compression node or the same compression node. A path of one or more compression nodes is determined through said compression hierarchy based upon compression statistics to compress data, and the data is compressed by the compression nodes of the path. Various computational techniques are presented herein for manipulating the compression hierarchy to defer or reduce computation during query evaluation.



ENHANCED COMPRESSION, ENCODING, AND NAMING FOR RESOURCE STRINGS

Thu, 14 Jul 2016 08:00:00 EDT

Technology is disclosed herein for compressing, encoding, and otherwise reducing the size of resource files. In at least one implementation, similarity compression is employed to reduce the size of a resource file. In another implementation, map-less encoding is employed to reduce the number of bytes used to represent a resource string. Bit-level compression is employed in another implementation to reduce the quantity of bits used to encode each character in a string. In addition, implementations are disclosed related to technology for naming strings and accelerated string location and retrieval.