Thu, 27 Oct 2016 08:00:00 EDTDisclosed are methods and systems for significantly compressing sparse multidimensional ordered series data comprised of indexed data sets, wherein each data set comprises an index, a first variable and a second variable. The methods and systems are particularly suited for compression of data recorded in double precision floating point format.
Thu, 27 Oct 2016 08:00:00 EDTIn one respect, there is provided a method for analog-to-digital conversion. The method may include: receiving, at an analog-to-digital converter, an analog signal; determining, based on a total distortion caused by at least a sampler and an encoder, a sampling rate below the Nyquist rate and/or a quantization rate; and converting, by the analog-to-digital converter, the received analog signal to a digital signal by at least sampling at the determined sampling rate, when operation at the determined sampling rate does not worsen the total distortion. Related systems and articles of manufacture are also disclosed.
Thu, 27 Oct 2016 08:00:00 EDTThe disclosure provides a capacitor array. The capacitor array includes one or more first metal plates vertically stacked parallel to each other. A second metal plate is horizontally stacked to couple one end of each first metal plate of the one or more first metal plates. One or more third metal plates are vertically stacked parallel to the one or more first metal plates. Each third metal plate of the one or more third metal plates is stacked between two first metal plates.
Thu, 27 Oct 2016 08:00:00 EDTIn described examples, an analog to digital converter (ADC) includes a main ADC and a reference ADC. The main ADC generates a zone information signal and a digital output in response to an input signal. The reference ADC receives a plurality of reference voltages from the main ADC. The plurality of reference voltages includes a first reference voltage and a second reference voltage. The reference ADC generates a reference output in response to the input signal, the first reference voltage and the second reference voltage. A subtractor generates an error signal in response to the digital output and the reference output. A logic block generates one of a first offset correction signal, a second offset correction signal and a gain mismatch signal in response to the zone information signal, the error signal and the reference output.
Thu, 20 Oct 2016 08:00:00 EDTDecomposing a value range of the respective syntax elements into a sequence of n partitions with coding the components of z laying within the respective partitions separately with at least one by VLC coding and with at least one by PIPE or entropy coding is used to greatly increase the compression efficiency at a moderate coding overhead since the coding scheme used may be better adapted to the syntax element statistics. Accordingly, syntax elements are decomposed into a respective number n of source symbols si with i=1 . . . n, the respective number n of source symbols depending on as to which of a sequence of n partitions into which a value range of the respective syntax elements is sub-divided, a value z of the respective syntax elements falls into, so that a sum of values of the respective number of source symbols si yields z, and, if n>1, for all i=1 . . . n−1, the value of si corresponds to a range of the ith partition.
Thu, 20 Oct 2016 08:00:00 EDTThe invention relates to an encoder and a decoder and methods therein for supporting split gain shape vector encoding and decoding. The method performed by an encoder, where the encoding of each vector segment is subjected to a constraint related to a maximum number of bits, BMAX, allowed for encoding a vector segment. The method comprises, determining an initial number, Np—init, of segments for a target vector x; and further determining an average number of bits per segment, BAVG, based on a vector bit budget and Np—init. The method further comprises determining a final number of segments to be used, for the vector x, in the gain shape vector encoding, based on energies of the Np—init segments and a difference between BMAX and BAVG. The performing of the method enables an efficient allocation of the bits of the bit budget over the target vector.
Thu, 20 Oct 2016 08:00:00 EDTDisclosed herein is an integrator including: a resistive element connected to an input terminal; an operational amplifier configured to receive, through the resistive element, an input signal that has been supplied to the input terminal; and a voltage regulator circuit connected to an intermediate node between the resistive element and the operational amplifier. The voltage regulator circuit has a first current source connected to the intermediate node, and a switch connected between the intermediate node and the first current source and selectively turning ON or OFF.
Thu, 20 Oct 2016 08:00:00 EDTMethods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.
Thu, 20 Oct 2016 08:00:00 EDTSystems and methods are provided for a successive approximation register (SAR) analog-to-digital converter (ADC) with an ultra-low burst error rate. Analog-to-digital conversions may be applied via a plurality of successive conversion cycles, with each conversion cycle corresponding to a particular bit in a corresponding digital output. Meta-stability may be detected during each one of the plurality of successive conversion cycles, and for each one of the plurality of successive conversion cycles, a next one of the plurality of successive conversion cycles may be triggered based on a cycle termination event. After completion of all of the plurality of successive conversion cycles, a meta-stability state of each of the plurality of successive conversion cycles may be assessed, and the digital output may be controlled based on the assessment.
Thu, 20 Oct 2016 08:00:00 EDTA semiconductor device and operating method thereof are provided. The semiconductor device includes a mode controller configured to output a control signal of a first level in a first mode, and output a control signal of a second level that is different from the first level in a second mode that is different from the first mode; and a successive approximation register analog-to-digital converter (SAR ADC) configured to convert an analog input signal into a digital output signal using a plurality of variable sampling capacitors, wherein each of the plurality of variable sampling capacitors comprises a first sampling capacitor having a first capacitance, and a second sampling capacitor having a second capacitance, wherein, in the first mode, the SAR ADC is configured to receive the control signal of the first level and connect the first sampling capacitor and the second sampling capacitor to either of a first voltage and a second voltage that is different from the first voltage to convert the analog input signal into the digital output signal, and wherein, in the second mode, the SAR ADC is configured to receive the control signal of the second level and connect any one of the first sampling capacitor and the second sampling capacitor to either of the first voltage and the second voltage to convert the analog input signal into the digital output signal.
Thu, 20 Oct 2016 08:00:00 EDTAn angle encoder is disclosed. The angle encoder has first and second components rotatable with respect to each other, and an encoder pattern comprising codewords for indicating the angle between the first and second components. The encoder pattern comprises a set of base encoder channels coded with a conventional Gray code, and a set of Booster channels for improving the resolution of angle measurement.
Thu, 20 Oct 2016 08:00:00 EDTSystems and methods are provided for digital-to-analog converter (DAC) with digital offsets. A digital offset may be applied to an input of a digital-to-analog converter (DAC), and digital-to-analog conversions are then applied via the DAC to the input with the digital offset. The digital offset is set to account for one or more conditions relating to inputs to the DAC, with the one or more conditions affect switching characteristics of one or more of a plurality of conversion elements in the DAC, and where each conversion element handles a particular bit in inputs to the DAC. The digital offset may be determined dynamically and adaptively, such as based on the input and/or conditions relating to the input. Alternatively, the digital offset may be pre-determined and fixed. One or more adjustments may be selectively applied to the digital offset for particular input conditions.
Thu, 20 Oct 2016 08:00:00 EDTSystems and methods are provided for digital-to-analog converter (DAC) with partial constant switching. A digital-to-analog converter (DAC) comprising a plurality of conversion elements may be configured to apply constant switching in only some of the conversion elements. Only conversion elements applying constant switching may incorporate circuitry for providing such the constant switching. Alternatively, each conversion element may incorporate constant switching circuitry and functionality, and the constant switching may then be turned on or off for each conversion element adaptively, such as based on input conditions.
Thu, 20 Oct 2016 08:00:00 EDTSystems and methods are provided for digital-to-analog converters (DACs) with enhanced dynamic element matching (DEM) and calibration. DEM may be adapted based on assessment of one or more conditions that may affect the DACs or DEM functions thereof. The one or more condition may comprise amount of signal backoff. The adaption may comprise switching the DEM function (as a whole, or partially—e.g., individual DEM elements) on or off based on the assess conditions. The DACs may incorporate use of calibration. The DEM and/or the calibration may be applied to only a portion of the DAC, such as a particular segment (e.g., a middle segment comprising bits between the MSBs and the LSBs).
Thu, 20 Oct 2016 08:00:00 EDTAt least one asymmetry element is configured to receive an input signal and is coupled to a first branch of a bi-stable flip-flop comprising the first branch and a second branch. An asymmetry between the first branch and the second branch depends on the input signal. A value indicative of the input signal is determined based on received output signals of a plurality of readout events.
Thu, 20 Oct 2016 08:00:00 EDTA piezoelectric device is connected in parallel with a diode, and outputs a power generation voltage when depressed. When the power generation voltage exceeds a first threshold voltage, a load switch control circuit makes a load switch be conductive, and when the generated voltage becomes lower than a second threshold voltage, the load switch is cut off. Further, when depression is released, the piezoelectric device is discharged by the diode such that the amount of charge remaining in the piezoelectric device becomes zero.
Thu, 13 Oct 2016 08:00:00 EDTAn apparatus and method for encoding data are disclosed that may allow for variable run length encoding of data to be transmitted. An ordered stream of data bits is received from a logic circuit, and N sequential data bits of the stream are selected, where N is a positive integer. Of the N sequential data bits, M sequential data bits are selected, wherein M is a positive integer less than N. The M sequential data bits are then encoded to generate a code word that includes P data bits, wherein P is a positive integer greater than M and less than N. The code word is then concatenated with a subset of the N sequential data bits that excludes the M sequential data bits to form a transmission word. A transmit unit then sends the data bits of the transmission word in a serial fashion.
Thu, 13 Oct 2016 08:00:00 EDTA digital-to-analog conversion (DAC) circuit has a resistor ladder circuit controlled by high order bits and a resistor string circuit controlled by low order bits. The resistor ladder circuit includes a stem resistor and a branch resistor. The stem resistor has a stem resistance, and the branch resistor has a branch resistance that is substantially equal to two times of the stem resistance. The resistor string circuit includes a string current source, a string resistor, and a bridge resistor. The string current source is configured to generate a string current that is based on a ratio of a reference voltage divided by a predetermined resistance. The string resistor has a string resistance that corresponds to the predetermined resistance, and it is configured to selectively receive the string current based on a selection signal decoded from the low order bits.
Thu, 13 Oct 2016 08:00:00 EDTA receiver having an analog to digital converter with adjustable reference voltages that are calibrated to account for process variations. The receiver comprises an analog to digital converter. The analog to digital converter includes a reference generator to generate a set of N reference voltages. The reference generator adjusts voltage levels of the set of N reference voltages based on one or more control signals. A plurality of comparators compare an input signal to the set of N reference voltages. A calibration circuit generates the one or more control signals for adjusting the voltage levels of the N reference voltages based on outputs of the comparators.
Thu, 13 Oct 2016 08:00:00 EDTAn information input and output device comprises a casing, an outer ring body, a magnetic wheel and an encoding module. The casing comprises an annulus sidewall and a base. A first surface of the outer ring body is close to the annulus sidewall. A single groove of the outer ring body is formed on the first surface. The magnetic wheel is fixed into the groove. The outer ring body and the magnetic wheel are rotatably disposed around an outer wall surface of the annulus sidewall. The encoding module comprises a circuit board and an information processing unit. When the outer ring body is rotated, the information processing unit is configured to detect a number of times and a direction in changes of the magnetic field of the magnetic wheel and convert the detected results into a position information and a direction information.
Thu, 06 Oct 2016 08:00:00 EDTThis invention relates to a system, method and computer program product for encoding an input string of binary characters including: a cellular data structure definition including a starting empty cell; one or more path definitions defining paths through the data structure; a character reading and writing engine for writing a binary character to an empty cell with a predefined initial position; a next cell determination engine for determining a next empty cell by methodically checking cells along one of the paths in the data structure until an empty cell is located; a loop facilitator for looping back to the writing next character step and the determining next cell step until there are no more data characters or a next empty cell is not determined; and a serialization deserialization engine for methodically serializing the data structure into a one dimensional binary string of characters representing an encoded string of alphanumeric characters.
Thu, 06 Oct 2016 08:00:00 EDTA method includes: setting a first and a second storage regions; first creating a first compression code of a compression target data in a file using a identifier indicating the data in the first storage region when a predetermined first consistency between the compression target data and the data in the first storage region is detected; comparing the compression target data with data in the second storage region when the predetermined first consistency between the compression target data and the data in the first storage region is not detected, the compression target data being moved to the second storage region after the comparing; and storing the compression target data into the first storage region associated with a identifier indicating the data in the first storage region when a predetermined second consistency between the compression target data and the data in the second storage region is detected.
Thu, 06 Oct 2016 08:00:00 EDTApproaches for staged data compression are provided, where each stage reflects a progressive increase in granularity, resulting in a scalable approach that exhibits improved efficiency and compression performance. The first stage comprises a long-range block-level compressor that determines redundancies on a block-level basis (based on entire data blocks, as opposed to partial segments within data blocks). The second stage comprises a long-range byte-level compressor that compresses an uncompressed block based on byte segments within the block that match previously transmitted segments. The duplicate segments are replaced with pointers to matching segments within a decompressor cache. Nonmatching segments of the data block are left uncompressed and passed to a third stage short-range compressor (e.g., a grammar-based compressor). The staged progression in granularity provides advantages of maximizing the compression gain while minimizing processing and storage requirements of the compressor and decompressor.
Thu, 06 Oct 2016 08:00:00 EDTAspects of dynamic data compression selection are presented. In an example method, as uncompressed data chunks of a data stream are compressed, at least one performance factor affecting selection of one of multiple compression algorithms for the uncompressed data chunks of the data stream may be determined. Each of the multiple compression algorithms may facilitate a different expected compression ratio. One of the multiple compression algorithms may be selected separately for each uncompressed data chunk of the data stream based on the at least one performance factor. Each uncompressed data chunk may be compressed using the selected one of the multiple compression algorithms for the uncompressed data chunk.
Thu, 06 Oct 2016 08:00:00 EDTThe present disclosure provides an R-2R ladder resistor circuit including: plural first resistance elements, one end of each being connected to an input terminal; plural second resistance elements, one end of each being connected to a reference potential; plural third resistance elements, one end of each being connected to an output terminal; and plural switching connection sections that are each in correspondence relationships with th first resistance elements, the second resistance elements, and the third resistance elements, and that connect the input terminal and the output terminal according to a bit signal, wherein, according to the bit signal, each switching connection section switchably connects another end of the third resistance element to another end of the first resistance element or to another end of the second resistance element, among the first resistance element, the second resistance element, and the third resistance element corresponding thereto.
Thu, 06 Oct 2016 08:00:00 EDTAccording to an embodiment, a comparator includes a first transistor, a second transistor, an output stage, and a node group. The first transistor is configured to operate when a first voltage applied thereto exceeds a first threshold value, and is disposed in an input stage. The second transistor is configured to operate when a second voltage applied thereto exceeds a second threshold value and is disposed in the input stage. The output stage is configured to perform voltage switching and output according to change in magnitude relationship between the first voltage and the second voltage. The node group is configured to, during a non-operational state in which the first voltage and the second voltage are not compared, vary at least either the first threshold value or the second threshold value.
Thu, 06 Oct 2016 08:00:00 EDTA method of fabricating an electronic device is provided, where the electronic device includes a port, an A/D converter, a memory, and a determination circuit. The determination circuit is configured to determine whether or not there is an abnormality by comparing an A/D converted value as a result of the A/D converter converting a voltage based on a power-supply voltage inputted to the port with a limit value stored in the memory. The method includes a step of inputting a predetermined voltage to the port of the electronic device to be fabricated, and a step of recording an A/D converted value as a result of the A/D converter converting a voltage based on the predetermined voltage inputted to the port as the limit value in the memory.
Thu, 06 Oct 2016 08:00:00 EDTMethods, systems, and apparatuses, including electrical circuits, are described for spread spectrum ADC noise reduction. An analog-to-digital converter may include an analog modulator to modulate an input analog signal according to a pseudo-noise sequence. An ADC core may convert the modulated analog input signal to a digital signal representation thereof. The digital signal may be demodulated using the pseudo-noise sequence to generate a noise-spread signal with reduced noise spectral density. The analog modulator and digital demodulator may also be configured in an analog-to-digital converter that includes a comparator and successive approximation register (SAR) logic, rather than an ADC core, in a SAR implementation. Multi-lane, interleaved analog-to-digital conversion circuits are also described using the inventive techniques. Analog-to-digital converters including DC offset components and methods performed according to the inventive techniques are also described.
Thu, 06 Oct 2016 08:00:00 EDTA semiconductor device according to an aspect of the invention relates to an AD converter that converts a signal level of an analog signal into a digital value by using a comparator, and determines an amount of adjustment of an offset voltage of the comparator based on an offset determination result of the comparator obtained immediately after a least significant bit (LSB) of a digital value output as a conversion result is converted.
Thu, 29 Sep 2016 08:00:00 EDTA method of lossless data compression includes receiving a set of parallel data strings; determining compression hash values for each of the parallel data strings; determining bit matches among portions of each of the parallel data strings based, at least in part, on the compression hash values; selecting among literals and the bit matches for each of the parallel data strings; and applying Huffman encoding to the selected literals or the selected bit matches.
Thu, 29 Sep 2016 08:00:00 EDTDetailed herein are embodiments of systems, methods, and apparatuses for decompression using hardware and software. For example, in embodiment a hardware apparatus comprises an input buffer to store incoming data from a compressed stream, a selector to select at least one byte stored in the input buffer, a decoder to decode the selected at least one byte and determine if the decoded at least one byte is a literal or a symbol, an overlap condition, a size of a record from the decoded stream, a length value of the data to be retrieved from the decoded stream, and an offset value for the decoded data, and a token format converter to convert the decoded data and data from source and destination offset base registers into a fixed-length token.
Thu, 29 Sep 2016 08:00:00 EDTA high-order delta-sigma modulator is realized with amplifying/integrating circuits each having a small circuit scale, to thereby provide a small-size and low-power consumption delta-sigma modulator having a high precision. The delta-sigma modulator including the amplifying/integrating circuits connected in series in a plurality of stages has a delta-sigma modulator configuration in which one of adjacent amplifying/integrating circuits includes a delay integrating circuit and another thereof includes a non-delay integrating circuit. In an actual circuit, one amplifying circuit is operated in a time division manner to be shared between the adjacent amplifying/integrating circuits. The circuit scale is reduced in this way.
Thu, 29 Sep 2016 08:00:00 EDTA digital-to-analog converter circuit including a plurality of digital-to-analog converter cells is provided. A first digital-to-analog converter cell of the plurality of digital-to-analog converter cells includes a cell control module configured to provide alternatingly a first voltage and a second voltage to a first electrode of a capacitive element of the first digital-to-analog converter cell based on a digital input signal during a predefined time interval. A second digital-to-analog converter cell of the plurality of digital-to-analog converter cells includes a cell control module configured to provide a third voltage to a first electrode of a capacitive element of the second digital-to-analog converter cell during the predefined time interval. The first voltage is higher than an upper threshold voltage corresponding to a first digital threshold level of the digital input signal and the second voltage is lower than a lower threshold voltage corresponding to a second digital threshold level of the digital input signal. The third voltage is constantly between the upper threshold voltage and the lower threshold voltage.
Thu, 29 Sep 2016 08:00:00 EDTAn apparatus for providing oscillator signals includes a first digital-to-time converter module configured to generate a first oscillator signal based on a first adapted input signal, a second digital-to-time converter module configured to generate a second oscillator signal; and a first processing module configured to generate the first adapted input signal of the first digital-to-time converter module by adding noise to a first input signal.
Thu, 29 Sep 2016 08:00:00 EDTAn analog-digital converter has an optical input stage configured to convert an analog input signal (S(t)) into a phase-modulated optical signal and to supply it to a hybrid coupler having a plurality of output waveguides, each being connected to at least one photodiode. The photodiodes are each connected to the input of an associated analog-digital converter via which an analog electrical input signal is convertible into a digital output signal. An output stage is configured to form the digital data stream at the output from the digital output signals of the analog-digital converter, and the output stage may be configured to select the output signal of the analog-digital converter which lies within a predefinable range of the amplitude and has a predefinable slope and/or is larger than a predefinable adjacent output signal.
Thu, 22 Sep 2016 08:00:00 EDTA comparator may include: a first comparison unit suitable for generating a comparison voltage by performing a comparison operation between a pixel signal and a ramp signal; a time point detection unit suitable for detecting specific timing points of the comparison operation in response to the comparison voltage and a reference voltage, and generating a detection signal corresponding to the specific timing points; a period determination unit suitable for determining an additional supply period in response to the detection signal and a period determination control signal; and an additional current supply unit suitable for supplying an additional current to the first comparison unit during the additional supply period.
Thu, 22 Sep 2016 08:00:00 EDTAccording to one embodiment, a first AD converter converts a first voltage into a first digital signal. A voltage/time conversion circuit acquires a residual corresponding to a difference between the first voltage and a result of having converted the first digital signal into an analog signal and converts the residual into a time signal according to a voltage in a first capacitor. A time/voltage conversion circuit converts the time signal into a voltage signal according to a voltage in a second capacitor. A second AD converter converts the voltage signal into a second digital signal. A digital processing circuit outputs a third digital signal to adjust a current value of first or the second current sources based on the second digital signal.
Thu, 15 Sep 2016 08:00:00 EDTSystem and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.
Thu, 15 Sep 2016 08:00:00 EDTCircuits, methods, and media for providing calibrated delta-sigma modulators are provided. In some embodiments, circuits for a delta-sigma modulator are provided, the circuits comprising: an analog-to-digital converter that produces an output having multiple bits; a digital-to-analog converter having an input having multiple bits; a switch coupled between the output the input that can be used to configure connections between the bits of the output and the bits of the input; a hardware processor that: for multiple iterations, sets a configuration of the switch, samples the bits of the output to produce sample values for each bit of the bits of the output, and calculates an average of the sample values for each of the bits of the output values; computes weights for each of the bits of the output values; and calculates weighted output values for every value of the outputs.
Thu, 15 Sep 2016 08:00:00 EDTProvided is a loop filter for a data converter in a wireless communication system that improves both an anti-aliasing filtering characteristic and a power consumption characteristic, the loop filter including first and third resistors sequentially connected to an input end, fourth and second resistors sequentially connected to between an inverting output end and ground, a first capacitor connected to between another end of the first resistor and one end of the fourth resistor, a second capacitor connected to between the one end of the fourth resistor and the output end, a third capacitor connected to between another end of the third resistor and the output end, and an operational amplifier, wherein an inverting end of the operational amplifier is connected to the other end of the first resistor and a non-inverting end of the operational amplifier is connected to ground to output an operational amplifier response to the output end.
Thu, 15 Sep 2016 08:00:00 EDTProvided are a semiconductor device and a System on Chip (SoC). The semiconductor device includes a reference capacitor that receives a reference voltage from a reference voltage generator, a first successive approximation register analog-to-digital converter (SAR ADC), for converting a first analog signal into a first digital signal, using a first sampling capacitor that has a first capacitance and is connected to the reference capacitor through a first switching element, and a second sampling capacitor that has a second capacitance that is less than that of the first sampling capacitor, connected to the reference capacitor through a second switching element, a second SAR ADC, for converting a second analog signal into a second digital signal, using a third sampling capacitor that has a third capacitance, connected to the reference capacitor through a third switching element, and a fourth sampling capacitor that has a fourth capacitance that is less than that of the third sampling capacitance connected to the reference capacitor through a fourth switching element, and a controller configured to connect the first switching element and the third switching element to the reference capacitor at different times.
Thu, 15 Sep 2016 08:00:00 EDTA preamplifier may include: a common active load suitable for providing output impedance; an output polarity changing unit suitable for changing an output polarity of output nodes; a multi-differential input stage suitable for receiving an input voltage, a coarse ramping voltage, a fine ramping voltage and a common mode voltage, and sampling the common mode voltage and the coarse ramping voltage for amplification operations; and a coupling blocking unit suitable for blocking a coupling between the output nodes and input nodes that are included in the multi-differential input stage.
Thu, 15 Sep 2016 08:00:00 EDTAging effects on devices fabricated using deep nanometer complementary metal-oxide semiconductor (CMOS) processes can cause circuits to exhibit an undesirable mismatch buildup over time. To address the aging effects, the connections to an array of M differential circuits are controlled to limit and systematically minimize or reverse the aging effects. In one embodiment, the controlling permutation sequence is selected to stress the array of M differential circuits under opposite stress conditions during at least two different time periods. Imposing opposite stress conditions, preferably substantially equal opposite stress conditions, can reverse the direction of a mismatch buildup and limit the mismatch buildup over time within acceptable limits. The controlling permutation sequence can be applied to an array of comparators of an analog-to-digital converter, or an array of differential amplifiers of a folding analog-to-digital converter.
Thu, 15 Sep 2016 08:00:00 EDTA comparator includes a common mode voltage sampling unit suitable for sampling a common mode voltage based on a sampling control signal; a coarse ramping voltage sampling unit suitable for sampling a coarse ramping voltage based on the sampling control signal; a preamplifier suitable for amplifying a difference between an input voltage and the sampled coarse ramping voltage to output a coarse conversion result, and amplifying a difference between a fine ramping voltage and the sampled common mode voltage to output a fine conversion result; and a signal processing unit suitable for generating the sampling control signal based on the coarse conversion result, and generating a comparison signal based on the coarse conversion result and the fine conversion result.
Thu, 08 Sep 2016 08:00:00 EDTData compression using a combination of content independent data compression and content dependent data compression. In one aspect, a system for compressing data comprises: a processor, and a plurality of data compression encoders wherein at least one data encoder utilizes asymmetric data compression. The processor is configured to determine one or more parameters, attributes, or values of the data within at least a portion of a data block containing either video or audio data, to select one or more data compression encoders from the plurality of data compression encoders based upon the determined one or more parameters, attributes, or values of the data and a throughput of a communications channel, and to perform data compression with the selected one or more data compression encoders on at least the portion of the data block.
Thu, 08 Sep 2016 08:00:00 EDTA method and an apparatus for splitting a switched capacitor integrator of a delta-sigma modulator are provided. The apparatus configures a first integrator and a second integrator to be coupled in parallel to each other, switches between a first mode and a second mode, enables the first integrator to operate on an input signal to generate an output signal in the first mode, and enables the first integrator and the second integrator to cooperatively operate on the input signal in the second mode, wherein in the second mode, the apparatus generates a first output via the first integrator, generates a second output via the second integrator, and converges the first output with the second output to generate the output signal.
Thu, 08 Sep 2016 08:00:00 EDTA D/A converter is configured to output tri-level potentials from an output terminal. A high potential terminal and the output terminal are connected through a p-type MOS transistor. An intermediate potential terminal and the output terminal are connected through p-type and n-type MOS transistors, which are connected in series and have low threshold voltages. A low potential terminal and the output terminal are connected through an n-type MOS transistor. The p-type MOS transistor and the n-type MOS transistor connected to the intermediate potential terminal have a positive voltage and a negative voltage between gate-source paths in off-states, respectively, and a substrate bias effect and hence remain in the off-state stably.
Thu, 08 Sep 2016 08:00:00 EDTSystems and methods are disclosed that may be implemented to provide keycap lighting to a spring loaded mechanical key switch assembly using a light conductive structure, such as a light pipe, and without requiring a chassis housing of the mechanical key switch assembly to include a dedicated power-consuming light source mounted to or otherwise positioned at the location of the individual key switch assembly chassis housing. Additionally, the disclosed systems and methods may be implemented to use one or more common power-consuming light source/s to simultaneously provide key cap lighting to multiple such spring loaded mechanical key switch assemblies, for example, by feeding light to each key cap though a common light spreader and through an individual non-power consuming light pipe provided for each key switch assembly.
Thu, 01 Sep 2016 08:00:00 EDTExamples of determining compression techniques to apply to documents are disclosed. In one example implementation according to aspects of the present disclosure, a method may include analyzing, by the computing system, at least a subset of a plurality of documents received by the computing system to determine document characteristics relating to the at least the subset of the plurality of documents. The method may also include determining, by the computing system, which of a plurality of compression techniques to apply to the plurality of documents based on the determined document characteristics.
Thu, 01 Sep 2016 08:00:00 EDTAn electrical circuit includes a signal processing chain and a controller. The signal processing chain includes an integrator configured to integrate an input signal over an integration time. The controller is connected to a signal output of the signal processing chain to receive and evaluate an output signal of the signal processing chain. The controller is further configured to adapt the integration time based on the output signal.