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SIGNALLING OF CHECKSUM FOR 802.11 MAC HEADERS

Thu, 06 Apr 2017 08:00:00 EDT

Methods, systems, and apparatuses (including, but not limited to portable devices and modem chips) for generating an error-check on the header of a medium access control (MAC) protocol data unit (PDU) (MPDU). This error-check is then inserted, at least in part, in the MAC header and/or the PHY layer PDU (PPDU) which will contain the MPDU. A separate indicator can be used to indicate whether any particular MAC frame has an error-check for its MAC header. Upon reception, the header of the MAC frame is processed and checked against the error-check inserted on the transmission side in order to determine whether the MAC header has an error.



METHOD FOR ENCODING DATA IN BURSTS

Thu, 06 Apr 2017 08:00:00 EDT

A process of encoding information data in a sequence of bursts ( . . . , Bi-2, Bi-1 Bi, Bi+1, . . . ), each burst comprising a block of information symbols and a block of redundancy symbols. The block of redundancy symbols (R,) of the current burst (B,) of the sequence is generated by calculating a sum of a series of coding values relating to a series of bursts (Bi-2, Bi-1), each coding value of the series of coding values being obtained by a respective coding function applied to the block of information symbols of the corresponding burst of the series of bursts.



METHOD AND APPARATUS FOR PERFORMING ENCODING USING BLOCK CODE HAVING INPUT/OUTPUT OF VARIABLE LENGTH

Thu, 06 Apr 2017 08:00:00 EDT

There are provided an encoding method and an encoder performing an encoding by an operation of generating a first output message by encoding an input message based on a first block code, an operation of generating a second output message by encoding some of the input message based on a second block code, and an operation of concatenating the first output message and the second output message.



TESTING STORAGE DEVICE POWER CIRCUITRY

Thu, 06 Apr 2017 08:00:00 EDT

The present invention extends to methods, systems, and computer program products for testing storage device power circuitry. A storage device controller includes an embedded test program. The storage device controller executes the test program in response to receiving a test command In one aspect, the test program issues a plurality of different command patterns to test shared power circuitry of storage device components (e.g., shared by an array of NAND flash memory devices). The test program identifies a command pattern that causes a greatest total current draw. In another aspect, the test program issues a specified command pattern (possibly repeatedly) to shared power circuitry to determine if the shared power circuitry fails.



METHOD AND APPARATUS FOR IMPROVING YIELD FOR NON-VOLATILE MEMORY

Thu, 06 Apr 2017 08:00:00 EDT

A method, apparatus and computer program product are provided in order to test word line failure of a non-volatile memory device. An example of the method includes performing a failure screening of the non-volatile memory device, wherein the non-volatile memory device comprises one or more word lines; identifying a point of failure located between a first word line and a second word line; and marking the first word line and the second word line as a single word line in response to identifying the point of failure between the first word line and the second word line.



STORAGE DEVICE AND A METHOD FOR DEFECT SCANNING OF THE SAME

Thu, 06 Apr 2017 08:00:00 EDT

A defect scan method is carried out to detect a defective portion in a storage medium of a storage device, the storage medium including multiple storage regions including a first storage region and a second storage region. The defect scan method includes scanning a part of the storage regions of the storage medium to detect a defective portion therein, before the storage device is connected to a host, a scanned storage region including the first storage region and a non-scanned storage region including the second storage region, mapping logical addresses to physical addresses of a non-defective portion of the first storage region, scanning the second storage region to detect a defective portion therein, after the storage device is connected to the host, and mapping logical addresses to physical addresses of a non-defective portion of the second storage region.



SYNCHRONOUS INPUT/OUTPUT USING A LOW LATENCY STORAGE CONTROLLER CONNECTION

Thu, 06 Apr 2017 08:00:00 EDT

Aspects include transmitting a synchronous I/O command to a persistent storage control unit (SCU in response to a synchronous I/O request from an operating system (OS). A unit of work in the OS corresponding to the synchronous I/O request remains active at least until the synchronous I/O request is completed. Based on an operation code of the synchronous I/O command specifying a read operation and in response to detecting that the persistent SCU has stored one or more read data records in a memory located on the processor, the firmware indicates to the OS that the synchronous I/O request is completed. Based on the operation code specifying a write operation and in response to detecting an indication from the persistent SCU that write data has been written or indicating that an error has occurred, indicating to the OS that the synchronous I/O request is completed.



System, Method, and Apparatus for Improving Throughput of Consecutive Transactional Memory Regions

Thu, 06 Apr 2017 08:00:00 EDT

Systems, apparatuses, and methods for improving TM throughput using a TM region indicator (or color) are described. Through the use of TM region indicators younger TM regions can have their instructions retired while waiting for older TM regions to commit.



METHOD FOR MONITORING SERVER, MONITORING DEVICE AND MONITORING SYSTEM

Thu, 06 Apr 2017 08:00:00 EDT

A method for monitoring a server, a monitoring device and a monitoring system are provided. The method includes: setting a system event to be monitored from the server; setting a trigger recording mode and a predetermined recording amount for recording system information of the server; capturing the system information related to the system event from a baseboard management controller (BMC) managing the server into a storage circuit according to the trigger recording mode and the predetermined recording amount; and displaying the system information stored in the storage circuit on an user interface.



SYNCHRONOUS INPUT/OUTPUT DIAGNOSTIC CONTROLS

Thu, 06 Apr 2017 08:00:00 EDT

Aspects include communicating synchronous input/output (I/O) commands between a system and a recipient. The system executes on a processor coupled to a memory so as to issue, to the recipient, a synchronous I/O command with a diagnostic operation code, where the synchronous I/O command causes a gathering of diagnostic information by the recipient. Further, the system receives, from the recipient, status information including a diagnostic information identifier, the status information being in accordance with the diagnostic information.



Data Recovery In A Distributed Storage System

Thu, 06 Apr 2017 08:00:00 EDT

A system, method, and machine-readable storage medium for recovering data in a distributed storage system are provided. In some embodiments, the method includes identifying a failing storage device of a first storage node having an inaccessible data segment. When it is determined that the inaccessible data segment cannot be recovered using a first data protection scheme, a first chunk of data associated with the inaccessible data segment is identified and a group associated with the first chunk of data is identified. A second chunk of data associated with the group is selectively retrieved from a second storage node such that data associated with an accessible data segment of the first storage node is not retrieved. The inaccessible data segment is recovered by recovering the first chunk of data using a second data protection scheme and the second chunk of data.



ENHANCED CONSOLE ASSISTED RECOVERY FOR A COORDINATED TIMING NETWORK

Thu, 06 Apr 2017 08:00:00 EDT

An enhanced console assisted recovery capability provides an efficient technique for communicating the failure of a primary time server to the backup time server in order to provide fast failure recovery of a synchronized timing network with the intent of avoiding a complete network outage. The primary time server efficiently notifies the backup time server that the primary time server is about to become unavailable. The backup time server can then begin an immediate takeover of time serving to the synchronized network.



TRANSACTION LOG LAYOUT FOR EFFICIENT RECLAMATION AND RECOVERY

Thu, 06 Apr 2017 08:00:00 EDT

A layout of a transaction log enables efficient logging of metadata into entries of the log, as well as efficient reclamation and recovery of the log entries by a volume layer of a storage input/output (I/O) stack executing on one or more nodes of a cluster. The transaction log is illustratively a two stage, append-only logging structure, wherein the first level is non-volatile random access memory (NVRAM) embodied as a NVlog and the second stage is disk, e.g., solid state drive (SSD). During crash recovery, the log entries are examined for consistency and scanned to identify those entries that have completed and those that are active, which require replay. The log entries are walked from oldest to newest (using sequence numbers) searching for the highest sequence number. Partially complete log entries (e.g., log entries in-progress when a crash occurs) may be discarded for failing a checksum (e.g., a CRC error). Old value/new value logs may be used to implement roll-forward or roll-back semantics to replay the log entries and fix any on-disk data structures, first from NVRAM and then from on-disk logs.



DECLUSTERED RAID ARRAY HAVING REDUNDANT DOMAINS

Thu, 06 Apr 2017 08:00:00 EDT

Embodiments of the present invention disclose a method, computer program product, and system for managing a RAID array of data storage devices. The declustered RAID array is configured to tolerate a predetermined number of failing data storage devices. The declustered RAID array of data storage devices is split into a plurality of regions, each of the plurality of regions is divided into a plurality of sets, and each of the sets of the plurality of sets utilizes a different combination of the data storage devices. The declustered RAID array provisions a plurality of LUNs from respective sets of each of the plurality of regions, and in response to a failure of one or more of the plurality of data storage devices, up to the predetermined number of failing data storage devices, the RAID array rebuilds at least one copy of each of the plurality of virtual LUNs.



OPERATING METHOD OF MEMORY SYSTEM

Thu, 06 Apr 2017 08:00:00 EDT

A decoding method includes: a first step of receiving data; and a second step of obtaining total number of error-corrected bits of the received data during a predetermined total decoding operation.



DATA STORAGE DEVICE WITH A MEMORY DIE THAT INCLUDES AN INTERLEAVER

Thu, 06 Apr 2017 08:00:00 EDT

A data storage device includes a set of latches, read/write circuitry, a memory, and an interleaver. The set of latches is configured to receive data. The read/write circuitry is coupled to the set of latches. The memory is coupled to the read/write circuitry. The interleaver is configured to interleave the data and to cause the read/write circuitry to program the interleaved data to the memory. The set of latches, the read/write circuitry, the memory, and the interleaver are integrated within a common die.



DATA STORAGE DEVICE AND OPERATING METHOD THEREOF

Thu, 06 Apr 2017 08:00:00 EDT

A data storage device includes a controller; and a nonvolatile memory device comprising a memory region including a plurality of memory cells, the nonvolatile memory device being suitable for acquiring first data by applying a first read voltage to the plurality of memory cells and acquiring second data by applying a plurality of second read voltages to the plurality of memory cells, according to control of the controller, wherein the controller is suitable for performing an error correction operation for the first data, based on the second data, and wherein the plurality of second read voltages have nonlinear variation rates with respect to the first read voltage.



SYSTEM AND METHOD FOR EARLY PACKET HEADER VERIFICATION

Thu, 06 Apr 2017 08:00:00 EDT

A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.



ERROR DETECTION AND RECOVERY FOR SYNCHRONOUS INPUT/OUTPUT OPERATIONS

Thu, 06 Apr 2017 08:00:00 EDT

Aspects include receiving, at an operating system (OS) executing on a server, a notification that an error was detected during execution of a synchronous I/O operation issued by the OS to a persistent storage control unit (SCU). The notification is received from firmware executing on the server and it includes a command response block that includes error condition information about the error. The method can also include selecting, by the OS, a recovery operation for the synchronous I/O operation. The selecting is based on the error condition information about the error in the command response block. The selected recovery option is performed by the OS.



ERROR DETECTION AND RECOVERY FOR SYNCHRONOUS INPUT/OUTPUT OPERATIONS

Thu, 06 Apr 2017 08:00:00 EDT

Aspects include receiving, at an operating system (OS) executing on a server, a notification that an error was detected during execution of a synchronous I/O operation issued by the OS to a persistent storage control unit (SCU). The notification is received from firmware executing on the server and it includes a command response block that includes error condition information about the error. The method can also include selecting, by the OS, a recovery operation for the synchronous I/O operation. The selecting is based on the error condition information about the error in the command response block. The selected recovery option is performed by the OS.



Collecting and Transmitting Diagnostics Information from Problematic Devices

Thu, 06 Apr 2017 08:00:00 EDT

A system, method, and computer-readable medium are disclosed for collecting and transmitting diagnostics information via a diagnostic information operation. The diagnostic information operation begins with a system periodically writing diagnostic information such as diagnostic errors and warnings to non-volatile local storage contained within the system. Upon detection of a failure, the user activates an NFC-enabled device (such as a mobile device) and positions the NFC-enabled device within NFC range of the failed system. The failed system then communicates the diagnostic information stored within the non-volatile local storage to NFC-enabled device.



DETECTION METHOD AND INFORMATION PROCESSING DEVICE

Thu, 06 Apr 2017 08:00:00 EDT

A method includes generating a plurality of pieces of correlation information based on correlations between changes in each item in each of different pairs of items in a plurality of items per unit period of time in a time series, each item relating to at least one of an operation, a performance, or a load in a computer system, each of the plurality of pieces of correlation information being generated for the plurality of items in one unit period of time in the time series, clustering the plurality of pieces of correlation information into a plurality of clusters, each cluster representing a state of the computer system and including a subset of the plurality of pieces of correlation information meeting a threshold for similarity, generating transition probabilities between each pair of the plurality of clusters, and determining an anomaly in the computer system based on the transition probability.



SYNCHRONOUS INPUT/OUTPUT DIAGNOSTIC CONTROLS

Thu, 06 Apr 2017 08:00:00 EDT

Aspects include communicating synchronous input/output (I/O) commands between a system and a recipient. The system executes on a processor coupled to a memory so as to issue, to the recipient, a synchronous I/O command with a diagnostic operation code, where the synchronous I/O command causes a gathering of diagnostic information by the recipient. Further, the system receives, from the recipient, status information including a diagnostic information identifier, the status information being in accordance with the diagnostic information.



Automated Ticketing Analytics

Thu, 06 Apr 2017 08:00:00 EDT

A computer-implemented method, system, and/or computer program product utilizes Automated Ticketing (AT) Analytics to create a recommendation file of routines and to automatically create a work ticket in response to a message. One or more processors identify messages related to a Logical Partition (LPAR) for automated ticketing. The messages identify an operational anomaly in the LPAR used by a computer system, and are based on sensor readings from hardware sensors and software programs within the computer system. The identified messages identify which messages are to be auto ticketed as a work ticket for the computer system. In response to updates to rules for automated ticketing being initiated, the processor(s) identify trends using an automated message analysis and an automation routine identification to automatically trigger a generation of the work ticket. The processors(s) automatically create and execute the work ticket to correct a new operational anomaly in the LPAR.



SYSTEM COMPONENT FAILURE DIAGNOSIS

Thu, 06 Apr 2017 08:00:00 EDT

System component failure diagnosis is provided. In response to determining that a number of component failure cases corresponding to a complex system stored in a historical diagnosis database is less than a pre-defined threshold number of component failure cases, a system component failure root cause is predicted using a rule-based reasoning method. In response to determining that the number of component failure cases corresponding to the complex system is greater than or equal to the pre-defined threshold number of component failure cases, the system component failure root cause is predicted using the rule-based reasoning method and a machine learning method. The diagnosis accuracy of the system component failure root cause predicted by the rule-based reasoning method and the machine learning method is calculated using a cross-validation method. The performance of the rule-based reasoning method and the machine learning method is evaluated using a statistical process control method.



ESTIMATING AN ERROR RATE ASSOCIATED WITH MEMORY

Thu, 06 Apr 2017 08:00:00 EDT

The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.



SCAN CHAIN LATCH DESIGN THAT IMPROVES TESTABILITY OF INTEGRATED CIRCUITS

Thu, 06 Apr 2017 08:00:00 EDT

A scan chain latch circuit, a method of operating a latch circuit in a scan chain, and a computer-readable medium having stored thereon a data structure defining a scan chain latch circuit for instantiation on a semiconductor die are disclosed. In an embodiment, the scan chain latch circuit comprises a first latch for holding one data value, a second latch for holding another data value, and a multiplexor. The one data value is applied to a first data input of the multiplexor and the another data value is applied to a second data input of the multiplexor. An alternating clock signal is applied to a select input of the multiplexor to control the output of the multiplexor, wherein the output of the multiplexor toggles between the two data values held in the two latches at a defined frequency.



LBIST DEBUG CONTROLLER

Thu, 06 Apr 2017 08:00:00 EDT

An integrated circuit (IC) includes a logic built-in self-test (LBIST) system that includes scan chains. The scan chains receive a clock signal and test pattern signals, and generate scan out signals. A debug controller receives the scan out signals and shifts a set of the scan out signals to a joint test action group (JTAG) controller. The debug controller also maintains a dynamic count indicative of the number of debug shift operations performed, and compares the dynamic count with a final count. If the dynamic count is less than the final count, the debug controller performs a second debug shift operation, which facilitates determination of a fault location in the IC.