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RATE MATCHING METHOD AND APPARATUS FOR POLAR CODES, AND WIRELESS COMMUNICATION DEVICE

Thu, 25 Aug 2016 08:00:00 EDT

A rate matching method for Polar codes includes: with respect to Polar codes output by an encoder, determining a plurality of types of punching position sets to be selected, punching positions indicated by any two punching position sets being not completely identical to each other; for each type of punching position set, determining the sum of error probabilities of all bit channels for transmitting information bits of the Polar codes when the punching position set is applied, the sum of the error probabilities being called the upper limit of frame error ratios corresponding to the punching position set; and from the plurality of types of punching position sets to be selected, selecting a punching position set corresponding to the minimum upper limit of the frame error ratios as a selected punching position set, and according to p punching positions indicated in the selected punching position set, conducting rate matching.



METHOD AND SYSTEM FOR PROVIDING SCRAMBLED CODED MULTIPLE ACCESS (SCMA)

Thu, 25 Aug 2016 08:00:00 EDT

A multiple access scheme is described. A first bit stream is scrambled from a first terminal according to a first scrambling signature. A second bit stream is scrambled from a second terminal according to a second scrambling signature, wherein the first bit stream and the second bit stream are encoded using a low rate code. The first scrambling signature and the second scrambling signature are assigned, respectively, to the first terminal and the second terminal to provide a multiple access scheme.



SYSTEM AND METHOD FOR SIGNALING CONTROL INFORMATION IN A MOBILE COMMUNICATION NETWORK

Thu, 25 Aug 2016 08:00:00 EDT

A method of decoding encoded information communicated over a radio channel includes receiving a vector of encoded information transmitted by a wireless terminal. The encoded information includes an encoded representation of unencoded information bits that have been encoded using a first order Reed-Muller code. The method also includes generating a vector of transform values by performing a Hadamard Transform on the received vector and identifying a subset of the transform values based on scheduling information associated with the wireless terminal. Additionally, the method includes selecting, from the subset of transform values, one of the transform values based on a magnitude of the selected transform value and determining an estimate of the unencoded information bits based on a bit sequence associated with the selected transform value. In accordance with another embodiment of the present disclosure, an apparatus is operable to implement this method



TRANSMITTER AND METHOD FOR GENERATING ADDITIONAL PARITY THEREOF

Thu, 25 Aug 2016 08:00:00 EDT

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to perform by group-wise interleaving a plurality of bit groups configuring the parity bits based on a group-wise interleaving pattern comprising a first pattern and a second pattern; a puncturer configured to puncture some of the parity-permutated parity bits; and an additional parity generator configured to select at least some of the punctured parity bits to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern.



TRANSMITTER AND REPETITION METHOD THEREOF

Thu, 25 Aug 2016 08:00:00 EDT

A transmitter is provided. The transmitter includes: a low density parity check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits; a repeater configured to select at least a part of bits constituting the LDPC codeword and add the selected bits after the input bits; and a puncturer configured to puncture at least a part of the parity bits.



SCHEME TO AVOID MISCORRECTION FOR TURBO PRODUCT CODES

Thu, 25 Aug 2016 08:00:00 EDT

A method includes identifying a stuck error pattern including failing constituent codes and decoding the stuck error pattern by conducting possible flipping patterns for the failing constituent codes, obtaining a number of successfully decoded codewords after conducting the possible flipping patterns, and selecting the most probable code word from the number of successfully decoded codewords.



TRANSMITTER AND METHOD FOR GENERATING ADDITIONAL PARITY THEREOF

Thu, 25 Aug 2016 08:00:00 EDT

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to perform parity-permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups configuring the interleaved parity bits based on a group-wise interleaving pattern including a first pattern and a second pattern; a puncturer configured to puncture some of the parity-permutated parity bits; and an additional parity generator configured to select at least some of the punctured parity bits to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern, wherein the first pattern determines parity bits to remain after the puncturing and then to be transmitted in the current frame.



TRANSMITTER AND METHOD FOR GENERATING ADDITIONAL PARITY THEREOF

Thu, 25 Aug 2016 08:00:00 EDT

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to interleave the parity bits and group-wise interleave a plurality of parity bit groups configuring the interleaved parity bits based on a group-wise interleaving pattern including a first pattern and a second pattern to perform parity permutation; a puncturer configured to puncture at least some of the group-wise interleaved parity bit groups; and an additional parity generator configured to select at least some of the punctured parity bit groups to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern.



TRANSMITTER AND METHOD FOR GENERATING ADDITIONAL PARITY THEREOF

Thu, 25 Aug 2016 08:00:00 EDT

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to perform parity-permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups configuring the interleaved parity bits based on a group-wise interleaving pattern including a first pattern and a second pattern; a puncturer configured to puncture some of the parity-permutated parity bits; and an additional parity generator configured to select at least some of the punctured parity bits to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern, wherein the first pattern determines parity bits to remain after the puncturing and then to be transmitted in the current frame.



TRANSMITTING METHOD AND TRANSMITTING APPARATUS

Thu, 25 Aug 2016 08:00:00 EDT

A low-density parity check convolution code (LDPC-CC) is made, and a signal sequence is sent after being subjected to an error-correcting encodement using the low-density parity check convolution code. In this case, a low-density parity check code of a time-variant period (3g) is created by linear operations of first to 3g-th (letter g designates a positive integer) parity check polynomials and input data.



TRANSMITTER AND REPETITION METHOD THEREOF

Thu, 25 Aug 2016 08:00:00 EDT

A transmitter is provided. The transmitter includes: a low density parity check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits; a repeater configured to select at least a part of bits constituting the LDPC codeword and add the selected bits after the input bits; and a puncturer configured to puncture at least a part of the parity bits.



DATA READING METHOD, MEMORY CONTROLLING CIRCUIT UNIT AND MEMORY STORAGE DEVICE

Thu, 25 Aug 2016 08:00:00 EDT

A data reading method is provided. The data reading method includes receiving a read command from a host system; sending a first read command sequence to obtain a first data string from memory cells of a rewritable non-volatile memory module; performing a decoding procedure on the first data string to generate a decoded first data string; and, if there is an error bit in the decoded first data string, sending a second read command sequence to obtain a second data string from the memory cells, performing a logical operation on the decoded first data string and the second data string to obtain an adjusting data string, adjusting the decoded first data string according to the adjusting data string to obtain an adjusted first data string, and using a data string obtained after re-performing the decoding procedure on the adjusted first data string as the decoded first data string.



SELECTIVE TRANSLATION LOOKASIDE BUFFER SEARCH AND PAGE FAULT

Thu, 25 Aug 2016 08:00:00 EDT

A translation lookaside buffer (TLB) stores translation entries. The translation entries include a virtual address, a physical address and a memory local/not-local flag. When a processor is in a low power/local memory mode a virtual address is received. A matching translation entry has a local/not-local flag. Upon the local/not-local flag indicating the physical address of the matching translation entry being outside the local memory, an out-of-access-range memory access exception is generated.



SERVICE IMPLEMENTATION BASED DEBUGGER FOR SERVICE ORIENTED ARCHITECTURE PROJECTS

Thu, 25 Aug 2016 08:00:00 EDT

A meta-debugger receives a first debugging command from a debugger client to set a breakpoint in a first service in a first language and sets the breakpoint in a first native debugger. After receiving a service message invoking the first service, the breakpoint is triggered and the meta-debugger provides to the debugger client a first graphical representation of the first native debugger. The meta-debugger receives a second debugging command from the debugger client, converts the second debugging command into a third debugging command to provide to the first native debugger. After invoking a second service in a second language, the meta-debugger provides to the debugger client a second graphical representation of the second native debugger. The meta-debugger receives a fourth debugging command from the debugger client, converts the fourth debugging command into a fifth debugging command to provide to the second native debugger.



Mobile Application Performance Measuring System

Thu, 25 Aug 2016 08:00:00 EDT

A quality score for a computer application release is determined using a first number of unique users who have launched the computer application release on user devices and a second number of unique users who have encountered at least once an abnormal termination with the computer application release on user devices. Additionally or optionally, an application quality score can be computed for a computer application based on quality scores of computer application releases that represent different versions of the computer application. Additionally or optionally, a weighted application quality score can be computed for a computer application by further taking into consideration the average application quality score and popularity of a plurality of computer applications.



LIGHTWEIGHT FUNCTIONAL TESTING

Thu, 25 Aug 2016 08:00:00 EDT

The present invention relates to a method performing a method for functional testing of a data collection system and at least one non-transitory computer-readable memory containing computer readable instructions for implementing this method. The method includes periodically sending by the message simulator to the data collection system running in production environment, batches of sets of messages, where the messages mimic normal client messages. Each message contains a batch identification common to the messages within the specific batch and a unique message counter value. The batch of messages received by the data collection system is checked in the verification service to verify whether the data collection systems operates correctly.



DYNAMICALLY ADJUSTING POWER DISTURBANCE HOLD UP TIMES

Thu, 25 Aug 2016 08:00:00 EDT

Power line disturbance hold up times are dynamically adjusted based on battery capacity of a plurality of batteries in a plurality of racks by determining which one of the plurality of racks has a fewest number of remaining batteries of the plurality of batteries having the battery capacity. A determination of an amount of the power line disturbance the one of the plurality of racks, having the fewest number of remaining batteries of the plurality of batteries with the battery capacity, is able to support.



MANAGING NETWORK FAILURE USING BACK-UP NETWORKS

Thu, 25 Aug 2016 08:00:00 EDT

A method for managing network failure identifying a plurality of hypervisors, each of the plurality of hypervisors being associated with a plurality of networks, and identifying a first network of the plurality of networks, wherein a first network role is assigned to the first network. The method further includes determining whether the plurality of hypervisors satisfies an unavailability condition, and, in response to determining that the plurality of hypervisors satisfies the unavailability condition, re-assigning the first network role of the first network to a back-up network.



ACQUIRING DIAGNOSTIC DATA SELECTIVELY

Thu, 25 Aug 2016 08:00:00 EDT

One or more processors execute one or more software commands that are capable of command failure on one or more computing devices. One or more processors detect one or more failed commands as a result of executing the one or more software commands. One or more processors determine whether the one or more failed commands are a first type of command failures that result from a first type of software commands. One or more processors reissue the one or more failed commands that are determined to be the first type of software commands at least once while at least one diagnostic program is executing. One or more processors capture diagnostic data for the one or more failed commands that are determined to be the first type of software commands.



Fault Tolerant Distributed Computation

Thu, 25 Aug 2016 08:00:00 EDT

The present information processing apparatus executes fault-tolerant distributed computing through a network and the information processing apparatus comprises: a finish initiator that creates a finish state on a home node; an activity creator that instructs to create at least one activity on a remote node; an activity launcher that allows to store in a resilient store a value indicating that at least one live activity is present on the remote node; an activity closer that decreases the number in the local memory when the living activity is completed and resets the value in the resilient store to indicate that no live activity is present on the remote node; and a finish closer that closes the finish state when the value stored in the resilient store indicates an absence of remote nodes having at least one live activity.



ACCELERATED RECOVERY AFTER A DATA DISASTER

Thu, 25 Aug 2016 08:00:00 EDT

According to embodiments of the present invention, a metadata file is transferred from the first system to the second system and a database on the second system is initialized based on the metadata file. An image, including information of the first system to be restored, is transferred from the first system to the second system, and restoration of the information to the second system based on the image is initiated. Prior to completion of the restoration, one or more log files indicating actions performed on the first system relating to the information to be restored is transferred from the first system to the initialized database on the second system. In response to completion of the restoration, the actions of the log files are performed to synchronize the restored data on the second system with the first system.



CONTROL APPARATUS, CONTROL METHOD AND RECORDING MEDIUM STORING CONTROL PROGRAM

Thu, 25 Aug 2016 08:00:00 EDT

A control apparatus according to an exemplary aspect of the present invention includes: circuitry configured to: receive a notification including information about an error in backing up to a first storage apparatus; perform failure analysis to detect an error in the backing up on a basis of the notification, and determine whether or not the error is caused by failure of the first storage apparatus; and instruct, when the error is caused by the failure of the first storage apparatus, an information processing apparatus performing the backing up to perform backing up to a second storage apparatus capable of communicating with the information processing apparatus to the second storage apparatus.



ACCELERATED RECOVERY AFTER A DATA DISASTER

Thu, 25 Aug 2016 08:00:00 EDT

According to embodiments of the present invention, a metadata file is transferred from the first system to the second system and a database on the second system is initialized based on the metadata file. An image, including information of the first system to be restored, is transferred from the first system to the second system, and restoration of the information to the second system based on the image is initiated. Prior to completion of the restoration, one or more log files indicating actions performed on the first system relating to the information to be restored is transferred from the first system to the initialized database on the second system. In response to completion of the restoration, the actions of the log files are performed to synchronize the restored data on the second system with the first system.



USER PROMPTED VOLUME RECOVERY

Thu, 25 Aug 2016 08:00:00 EDT

A method of recovering from a data storage error includes determining that a data storage error has occurred. The method further includes, upon receiving direction from the user to recover from the data storage error, evaluating a page map relating a logical storage architecture with a physical storage architecture. The method also includes revising the page map based on the evaluating. The data storage error may be one or more of a (i) a missing page and (ii) a duplicate page.



PERFORMING MEMORY DATA SCRUBBING OPERATIONS IN PROCESSOR-BASED MEMORY IN RESPONSE TO PERIODIC MEMORY CONTROLLER WAKE-UP PERIODS

Thu, 25 Aug 2016 08:00:00 EDT

Aspects of the disclosure involve memory data scrubber circuits configured to perform memory data scrubbing operations in a processor-based memory to provide data error correction in response to periodic memory controller wake-up periods. Memory data scrubbing is performed to correct errors in data words stored in memory. Memory data scrubbing is initiated in the memory to conserve power in response to periodic memory controller wake-up periods during processor idle periods. Further, in certain aspects disclosed herein, the memory data scrubber circuit is provided as a separate system outside of the memory controller in the memory system. In this manner, power consumption can be further reduced, because the memory data scrubber circuit can continue with memory data scrubbing operations in the memory independent of the memory controller operation, and after the memory controller access commands issued during the wake-up period are completed and the memory controller is powered-down.



RAID ARRAY SYSTEMS AND OPERATIONS USING MAPPING INFORMATION

Thu, 25 Aug 2016 08:00:00 EDT

An apparatus may include a redundant array of independent disks (RAID) array including a plurality of solid state drives (SSDs). The apparatus may further include a RAID array controller coupled to the plurality of SSDs. The RAID array controller may be configured to determine whether one or more logical block addresses (LBAs) of a stripe of the RAID array are unmapped. The one or more LBAs may be associated with one or more SSDs of the plurality of SSDs. The RAID array controller may be configured to determine data corresponding to the stripe based on the determination of whether the one or more LBAs are unmapped. RAID operations (such has Rebuild, Exposed Mode Read, and/or Parity Resync operations) may be optimized based on the knowledge of which LBAs are mapped and unmapped.



VIRTUAL CHUNK SERVICE BASED DATA RECOVERY IN A DISTRIBUTED DATA STORAGE SYSTEM

Thu, 25 Aug 2016 08:00:00 EDT

Technology is disclosed for storing data in a distributed storage system using a virtual chunk service (VCS). In the VCS based storage technique, a storage node (“node”) is split into multiple VCSs and each of the VCSs can be assigned a unique ID in the distributed storage. A set of VCSs from a set of nodes form a storage group, which also can be assigned a unique ID in the distributed storage. When a data object is received for storage, a storage group is identified for the data object, the data object is encoded to generate multiple fragments and each fragment is stored in a VCS of the identified storage group. The data recovery process is made more efficient by using metadata, e.g., VCS to storage node mapping, storage group to VCS mapping, VCS to objects mapping, which eliminates resource intensive read and write operations during recovery.



METHODS FOR POLICY-BASED HIERARCHICAL DATA PROTECTION AND DEVICES THEREOF

Thu, 25 Aug 2016 08:00:00 EDT

A method, non-transitory computer readable medium, and storage management computing device that obtains an information lifecycle management (ILM) policy. A data protection scheme to be applied at a storage node computing device level is determined and a plurality of storage node computing devices are identified based on an application of the ILM policy to metadata received from one of the storage node computing devices and associated with an object ingested by the one of the storage node computing devices. The one of the storage node computing devices is instructed to generate one or more copies of the object or fragments of the object according to the data protection scheme and to distribute the object copies or one of the object fragments to one or more other of the storage node computing devices to be stored by at least the one or more other storage node computing devices on one or more disk storage devices.



MEMORY CIRCUIT INCORPORATING ERROR DETECTION AND CORRECTION (EDAC), METHOD OF OPERATION, AND SYSTEM

Thu, 25 Aug 2016 08:00:00 EDT

An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry.



Flash Channel with Selective Decoder Likelihood Dampening

Thu, 25 Aug 2016 08:00:00 EDT

An apparatus for reading a flash memory includes a read controller operable to read the flash memory to yield read patterns, a likelihood generator operable to map the read patterns to likelihood values, a decoder operable to decode the likelihood values, a data state storage operable to retrieve the likelihood values for which decoding failed, and a selective dampening controller operable to select at least one dampening candidate from among the likelihood values for which decoding failed, to dampen the likelihood values of the at least one dampening candidate to yield dampened likelihood values, and to provide the dampened likelihood values to the decoder for decoding.



CONTROLLER, SEMICONDUCTOR MEMORY SYSTEM AND OPERATING METHOD THEREOF

Thu, 25 Aug 2016 08:00:00 EDT

An operating method of a controller that includes: when a first ECC decoding on data read from a semiconductor memory device according to a hard read voltage fails, generating one or more quantization intervals based on the number of unsatisfied syndrome check (USC), which is a result of the first ECC decoding; and performing a second ECC decoding on the data by generating soft read data according to soft read voltages determined by the hard read voltage and the quantization intervals.



METHOD AND APPARATUS FOR CONFIGURING A MEMORY DEVICE

Thu, 25 Aug 2016 08:00:00 EDT

Apparatus and methods implemented therein use an ECC procedure to verify and correct errors in data corresponding to pre-programmed configuration data. Verification and correction is performed in a memory system comprising a non-volatile memory (NVM) and a read only memory (ROM). The NVM comprises a plurality of memory pages. On detecting a power-on reset (POR) command at the memory system, a determination is made whether the memory system has previously received the POR command from a host. When it is determined that the memory system has not previously received the POR command from the host, pre-programmed configuration data is read from the ROM and the memory system is initialized using the pre-programmed configuration data. An error correction code (ECC) is generated for the pre-programmed configuration data and the pre-programmed configuration data including the ECC is store in one of the plurality of pages of the NVM memory.



STORAGE CONTROL APPARATUS

Thu, 25 Aug 2016 08:00:00 EDT

Each transfer route includes an FE I/F out of a plurality of FE I/Fs, a BE I/F out of a plurality of BE I/Fs, at least one memory out of one or more memories, and at least one processor out of one or more processors. I/O target data is transferred via a target transfer route including an FE I/F that has received an I/O request out of a plurality of transfer routes. A processor in the target transfer route generates routing information representing a physical device included in the target transfer route, and transmits a transfer indication including the routing information to at least one of the FE I/F and BE I/F in the target transfer route. In response to the transfer indication, at least one of the FE I/F and BE I/F in the target transfer route adds, to the I/O target data, a guarantee code.



ERROR CORRECTION FOR NON-VOLATILE MEMORY

Thu, 25 Aug 2016 08:00:00 EDT

Techniques for encoding data for non-volatile memory storage systems are disclosed. In one particular embodiment, the techniques may be realized as a method including determining whether the memory includes a defective memory cell, receiving a message to be written to the memory, sub-dividing the message into a plurality of sub-messages, generating a first error correction code for the sub-messages, the first error correction code being a first type, generating a plurality of second error correction codes for the sub-messages, the second error correction codes being a second type different from the first type, generating a combined message comprising the sub-messages, the first error correction code, and the plurality of second error correction codes, and writing the combined message to the memory, at least a portion of the combined message being written to the defective memory cell.



PREEMPTIVE RELOCATION OF FAILING DATA

Thu, 25 Aug 2016 08:00:00 EDT

According to one embodiment, a method for preemptively migrating a failing extent includes receiving information of one or more failure conditions associated with an extent stored in a first storage portion of a first storage tier; predicting a failure of the extent based on the information; selecting a second storage portion located in one of a plurality of storage tiers; and migrating the extent to the selected second storage portion.



SYSTEM AND METHOD FOR RECOVERING FROM A CONFIGURATION ERROR

Thu, 25 Aug 2016 08:00:00 EDT

A system and method for recovering from a configuration error are disclosed. A Basic Input Output System (BIOS) configures a memory associated with a node of an information handling system and enables a progress monitoring process during configuration of the memory. The memory is disabled if the BIOS determines that a configuration error occurred and a memory reference code associated with the memory is modified in order to prevent a reset of the information handling system.



SYSTEMS AND METHODS FOR ERROR HANDLING

Thu, 25 Aug 2016 08:00:00 EDT

Systems and methods for performing error handling in ERP systems are disclosed. In one implementation, the method comprises receiving processed jobs data from at least one of the ERP systems. Further, the method comprises analyzing the processed jobs data to determine error data associated with one or more errors occurred while processing jobs in the at least one of the ERP systems. Further, the method comprises executing at least one corrective action to rectify the one or more errors based on the error data. Further, the method comprises tracking processing of the jobs in the at least one of the ERP system upon executing the at least one corrective action. Further, the method comprises performing one or more trigger actions to improve performance of the jobs based on the tracking.



DETECTION AND CORRECTION OF FAULT INDUCED DELAYED VOLTAGE RECOVERY

Thu, 25 Aug 2016 08:00:00 EDT

Disclosed herein are methods for detecting and correcting a fault induced delayed voltage recovery event in an electric power transmission and distribution system. In some embodiments, a fault detection subsystem may receive an indication of a fault in the electric power transmission and distribution system. The system may also include a load analysis subsystem to analyze a plurality of loads supplied by the electric power system and to generate an estimated response of the loads. A fault analysis subsystem may analyze a plurality of factors relating to the fault and to determine a probability of the fault generating a fault induced delayed voltage recovery event. A control system may then implement a control strategy within a control window following the fault based on the probability of the fault generating a fault induced delayed voltage recovery event and the estimated response of the at least one load.



METHODS, MEDIA AND SYSTEMS FOR DETECTING ANOMALOUS PROGRAM EXECUTIONS

Thu, 25 Aug 2016 08:00:00 EDT

Methods, media, and systems for detecting anomalous program executions are provided. In some embodiments, methods for detecting anomalous program executions are provided, comprising: executing at least a part of a program in an emulator; comparing a function call made in the emulator to a model of function calls for the at least a part of the program; and identifying the function call as anomalous based on the comparison. In some embodiments, methods for detecting anomalous program executions are provided, comprising: modifying a program to include indicators of program-level function calls being made during execution of the program; comparing at least one of the indicators of program-level function calls made in the emulator to a model of function calls for the at least a part of the program; and identifying a function call corresponding to the at least one of the indicators as anomalous based on the comparison.



MICRO CONTROLLER UNIT INCLUDING AN ERROR INDICATOR MODULE

Thu, 25 Aug 2016 08:00:00 EDT

A micro controller unit including an error indicator hardware module, the error indicator module being arranged to respond to event signals representative of internal and external fault and error events perturbing the micro controller unit function by registering in non-volatile memory a record of the nature of each of the events, wherein the record of the events is inaccessible to alteration.



CREATING ENVIRONMENTAL SNAPSHOTS OF STORAGE DEVICE FAILURE EVENTS

Thu, 25 Aug 2016 08:00:00 EDT

A storage device failure in a computer storage system can be analyzed by the storage system by examining relevant information about the storage device and its environment. Information about the storage device is collected in real-time and stored; this is an on-going process such that some information is continuously available. The information can include information relating to the storage device, such as input/output related information, and information relating to a storage shelf where the storage device is located, such as a status of adjacent storage devices on the shelf. All of the relevant information is analyzed to determine a reason for the storage device failure. Optionally, additional information may be collected and analyzed by the storage system to help determine the reason for the storage device failure. The analysis and supporting information can be stored in a log and/or presented to a storage system administrator to view.



AUTOMATIC TROUBLESHOOTING

Thu, 25 Aug 2016 08:00:00 EDT

A method for automatically detecting and diagnosing problems in computer system functioning includes determining changed objects from computer system monitoring data, calculating temporal correlations from errors and changes sequences for each changed object, identifying and ranking suspicious computer system behavior patterns from the temporal correlations, and outputting said ranked suspicious computer system behavior patterns.



ANALYZING THE AVAILABILITY OF A SYSTEM

Thu, 25 Aug 2016 08:00:00 EDT

An apparatus and method for analyzing availability of a system including subsystems each having at least one failure mode with a corresponding failure effect on the system are provided. The apparatus includes a degraded mode tree generation unit configured to automatically generate a degraded mode tree. The degraded mode tree includes at least one degraded mode element representing a degraded system state of the system that deviates from a normal operation state of the system based on a predetermined generic system meta model stored in a database including Failure Mode and Effects Analysis elements representing subsystems, failure modes, failure effects, and diagnostic measures. The apparatus also includes a processor configured to evaluate the generated degraded mode tree for calculation of the availability of the system.



STORAGE SYSTEM AND METHOD FOR CONTROLLING SAME

Thu, 25 Aug 2016 08:00:00 EDT

Provided is a storage system which is connected to a host computer and whereby data is read and written. The storage system comprises: a storage device which stores the data; and a storage controller wherein an error is detected by one of a plurality of first sections which are sections upon a transfer path of the data with respect to the storage device in a full check mode, an error is detected by one of second sections which are fewer than the first sections in a regular mode, and a switch is made to the full check mode when the error is detected in the regular mode.



FAILURE PREDICTION SYSTEM OF CONTROLLER

Thu, 25 Aug 2016 08:00:00 EDT

From an error information containing a content of a correctable error that has occurred in a controller of a failure prediction system and an ID of the controller and manufacturing information of a machine to which the controller is attached, a failure of a controller belonging to a group of controllers in which such an error as indicated in the error information has not occurred yet is predicted.



ACQUIRING DIAGNOSTIC DATA SELECTIVELY

Thu, 25 Aug 2016 08:00:00 EDT

One or more processors execute one or more software commands that are capable of command failure on one or more computing devices. One or more processors detect one or more failed commands as a result of executing the one or more software commands. One or more processors determine whether the one or more failed commands are a first type of command failures that result from a first type of software commands. One or more processors reissue the one or more failed commands that are determined to be the first type of software commands at least once while at least one diagnostic program is executing. One or more processors capture diagnostic data for the one or more failed commands that are determined to be the first type of software commands.



USING HARDWARE TRANSACTIONAL MEMORY FOR IMPLEMENTATION OF QUEUE OPERATIONS

Thu, 25 Aug 2016 08:00:00 EDT

Using hardware transactional memory (HTM) for queue operations includes invoking a first operation for a concurrent linked queue of an interpretive program using a Just-In-Time (JIT) compiler of a virtual machine, wherein the first operation does not use HTM, determining whether a data processing system executing the virtual machine supports HTM, and responsive to determining that the data processing system does support HTM, detecting, using a processor and within the first operation, a call to a second operation that is that is configured, in byte code, to return an indication of a failed hardware transaction. Responsive to detecting the second operation, a machine code implementation of the first operation that includes a machine code implementation of the second operation is generated. The machine code implementation of the second operation is an implementation of the first operation that does use HTM.



DEDUPLICATION OF PARITY DATA IN SSD BASED RAID SYSTEMS

Thu, 25 Aug 2016 08:00:00 EDT

The present disclosure describes various techniques related to maintaining parity data in a redundant array of independent disks (RAID).



DYNAMIC DESIGN PARTITIONING FOR DIAGNOSIS

Thu, 25 Aug 2016 08:00:00 EDT

Aspects of the invention relate to techniques for fault diagnosis based on dynamic circuit design partitioning. According to various implementations of the invention, a sub-circuit is extracted from a circuit design based on failure information of one or more integrated circuit devices. The extraction process may comprise combining fan-in cones of failing observation points included in the failure information. The extraction process may further comprise adding fan-in cones of one or more passing observation points to the combined fan-in cones of the failing observation points. Clock information of test patterns and/or layout information of the circuit design may be extracted and used in the sub-circuit extraction process. The extracted sub-circuit may then be used for diagnosing the one or more integrated circuit devices.



APPARATUS FOR DETECTING BUGS IN LOGIC-BASED PROCESSING DEVICES

Thu, 25 Aug 2016 08:00:00 EDT

An apparatus for detecting bugs in a logic-based processing device during post-silicon validation is disclosed. The apparatus includes a test bench and a Proactive Load and Check (PLC) hardware checker inserted within an uncore component of the logic-based processing device. The test bench includes a processor for converting an original test program to a modified test program for validating the functionalities of the logic-based processing device during post-silicon validation. The PLC hardware checker includes a controller, an address generator, a data register and a comparator.