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FAULT DETECTION FOR SYSTEMS IMPLEMENTING A BLOCK CIPHER

Thu, 27 Oct 2016 08:00:00 EDT

A fault detection method for an encryption/decryption system based on a block cipher comprises the steps of subjecting a state array (CST) to multiple rounds, each round comprising a same series of sequential operations transforming the state array; storing the state of a reference operation (ShiftRows) of a current round as a checkpoint state (CHK); storing the state of the reference operation in the next round as an intermediate state; applying one round of reciprocal operations to the intermediate state, starting from the reciprocal of the reference operation (InvShiftRows); and comparing the result state of said one round of reciprocal operations with the checkpoint state.



Self-Stabilizing Distributed Symmetric-Fault Tolerant Synchronization Protocol

Thu, 27 Oct 2016 08:00:00 EDT

A network system includes at least one node configured to exchange messages through a set of communication links. Each node includes a synchronizer, a set of monitors in communication with the synchronizer, a physical oscillator and a state timer clock and a local timer clock, each clock being driven by the physical oscillator and having a variable clock value that locally tracks passage of clock time for the node. The network system is configured to execute a synchronization process when a specified condition occurs. Upon receiving a Sync message, each of the nodes is configured to store an incoming Sync message, increment a local timer clock value, or ignore the Sync message based on a local timer clock value associated with an incoming Sync message.



APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS

Thu, 27 Oct 2016 08:00:00 EDT

The present invention provides a method of transmitting broadcast signals. The method includes, formatting, by an input formatting block, input streams into plural PLPs (Physical Layer Pipes); encoding, by an encoder, data in the plural PLPs; processing, by a framing and interleaving block, the encoded data in the plural PLPs to output at least one signal frame; and waveform modulating, by a waveform generation block, data in the at least one signal frame and transmitting, by the waveform generation block, broadcast signals having the waveform modulated data.



DIGITAL TELEVISION TRANSMITTING SYSTEM AND RECEIVING SYSTEM AND METHOD OF PROCESSING BROADCASTING DATA

Thu, 27 Oct 2016 08:00:00 EDT

A method and transmitting system for processing data are discussed. The method according to an embodiment includes randomizing enhanced data; first encoding the randomized enhanced data to add first parity data for error correction, thereby forming a frame; dividing data of the frame into a plurality of groups, wherein the plurality of groups have a same size; first interleaving data of each group; second interleaving the first-interleaved data; encoding signaling information at a code rate; and transmitting a broadcast signal including the second-interleaved enhanced data and the encoded signaling information. Second encoding on the randomized enhanced data is selectively performed, wherein, when the second encoding is performed, second parity data for error detection are added to the randomized enhanced data. The signaling information includes transmission parameters to indicate whether the second encoding is performed.



TRANSMISSION METHOD, RECEPTION METHOD, TRANSMITTER, AND RECEIVER

Thu, 27 Oct 2016 08:00:00 EDT

In a transmission method according to one aspect of the present disclosure, a encoder performs error correction coding on an information bit string to generate a code word. A mapper modulates a first bit string in which the number of bits is the predetermined integral multiple of (X+Y) in the code word using a first scheme, the first scheme being a set of a modulation scheme in which an X-bit bit string is mapped to generate a first complex signal and a modulation scheme in which a Y-bit bit string is mapped to generate a second complex signal, and modulates a second bit string in which the first bit string is removed from the code word using a second scheme different from the first scheme.



APPARATUSES AND METHODS FOR PIPELINING MEMORY OPERATIONS WITH ERROR CORRECTION CODING

Thu, 27 Oct 2016 08:00:00 EDT

Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.



ITERATIVE DECODING DEVICE, ITERATIVE SIGNAL DETECTION DEVICE AND INFORMATION UPDATE METHOD FOR THE SAME

Thu, 27 Oct 2016 08:00:00 EDT

An iterative decoding device applied for a SISO (soft input soft output) system is disclosed, which comprises an operational control unit, a first decoder, and a second decoder. The operational control unit is operative to receive an encoded signal and divide the encoded signal into at least one frame. The first decoder is operative to receive each of the at least one frame and derive a renewed intrinsic information by a first iteration operation. The second decoder is operative to derive soft-information by a second iteration operation based on the renewed intrinsic information, and then transmit the soft-information back to the first decoder for the iteration operation of the next renewed intrinsic information. The operational control unit makes the at least one frame to be calculated respectively by the first decoder and the second decoder, thereby improving the efficiency and error ratio of a receiver.



TURBO PRODUCT CODED MODULATION

Thu, 27 Oct 2016 08:00:00 EDT

An optical transmission technique includes receiving data for transmission over the optical communication network, applying a three-dimensional (3D) error correction code to the data using three component codes, resulting in error correction coded signal, modulating the error correction coded signal using a quadrature amplitude modulation (QAM) scheme and processing and transmitting the modulated signal over the optical communication medium.



DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

Thu, 27 Oct 2016 08:00:00 EDT

The present technology relates to a data processing device and a data processing method that make it possible to ensure good communication quality in a data transmission using LDPC codes. In group-wise interleave, an LDPC code whose code length is 16200 bits and code rate is 6/15, 7/15, 8/15, or 9/15 is interleaved in a 360-bit group unit. In group-wise deinterleave, a sequence of the LDPC code after group-wise interleave obtained from data transmitted from a transmitting device to the original sequence. The present technology can be applied, for example, to data transmission or the like using the LDPC codes.



ERROR CORRECTION CODE (ECC) SELECTION USING PROBABILITY DENSITY FUNCTIONS OF ERROR CORRECTION CAPABILITY IN STORAGE CONTROLLERS WITH MULTIPLE ERROR CORRECTION CODES

Thu, 27 Oct 2016 08:00:00 EDT

A method of characterizing a distribution of a maximum number of errors that first cause uncorrectable error correction code failure for hard low density parity check codes includes selecting a low density parity check code, generating encoded data with the low density parity check code and writing the encoded data to a number of memory blocks, reading the encoded data from the number of memory blocks and determining any pages having a first uncorrectable error correction code failure, determining a number of raw bit errors for each page having a first uncorrectable error correction code failure, incrementing an error count value corresponding to each of the numbers of raw bit errors determined, and repeating the generating, reading, determining, and incrementing steps for a predetermined range of values of a predetermined reliability statistic of the memory blocks.



CRC CALCULATION METHOD, AND APPARATUS

Thu, 27 Oct 2016 08:00:00 EDT

A CRC calculation method and apparatus are provided. According to technical solutions provided in embodiments of the present invention, a binary sequence of a first pulse includes the first packet and the second packet. The number of bits in the first packet is unequal to the number of bits in the second packet. The first packet is distributed to a first CRC calculation circuit. The second packet is distributed to a second CRC calculation circuit. CRC of the first packet is obtained by calculation by using the first CRC calculation circuit. CRC of the second packet is obtained by using the second CRC calculation circuit. If the foregoing technical solutions are applied to the foregoing application scenario of flexible Ethernet, CRC of packets with different lengths and from different transmitters may be separately calculated. Therefore, the foregoing technical solutions may be better applied to the scenario of flexible Ethernet.



METHOD AND APPARATUS FOR IDENTIFYING ERRONEOUS DATA IN AT LEAST ONE MEMORY ELEMENT

Thu, 27 Oct 2016 08:00:00 EDT

A method for identifying erroneous data in at least one memory element, particularly a register, that includes at least one flip-flop that is intended to allow reliable detection of soft errors. To this end, writing of data to the at least one memory element involves at least one write security bit being produced from these data and stored in an associated security memory element, wherein at least one output security bit is computed from the data continuously in the same way as for writing and is compared with the corresponding write security bit.



SYSTEM AND METHOD OF MEMORY MANAGEMENT

Thu, 27 Oct 2016 08:00:00 EDT

Embodiments of system and methods for managing memory cells are disclosed, where a memory priority map is generated based on at least one testing procedure, and memory cells of a memory device are allocated to at least one application executed in a computing system by the memory priority map and defined allocating regulations. Further, whenever a fresh memory testing procedure is executed, the memory priority map is updated.



SELF-SERVE DIAGNOSTIC TOOLS FOR NETWORK SERVICES

Thu, 27 Oct 2016 08:00:00 EDT

A network device receives a collection of technical steps for implementing a type of service campaign. The technical steps include application programming interface (API) level calls to a service provider network. The network device associates the technical steps with particular customer software, receives validation criteria for each of the technical steps, generates a diagnostic map of the technical steps for the particular customer software, and conducts, based on the diagnostic map, a test of the API level calls for the particular customer software to obtain test results. The network device receives a customer deployment record of changes occurring during software deployments for the service campaign for the particular customer software and receives a provider record of service provider changes to network level software that impact the service campaign for the particular customer software. The network device correlates the test results with the customer deployment record and the provider record.



SYSTEMS AND METHODS TO IDENTIFY AND CLASSIFY PERFORMANCE BOTTLENECKS IN CLOUD BASED APPLICATIONS

Thu, 27 Oct 2016 08:00:00 EDT

Described herein are systems and methods of identifying and classifying performance bottlenecks for web applications. Such systems and methods use classification and analysis of performance testing data and data instrumentation via arithmetic and/or machine learning. Data is integrated from different sources including system data, historical and real time sources. Performance variations are analyzed as load changes and the impact of these variations on different sectors of the Application stack are analyzed. Bottlenecks are identified and classified based on the sector in the software stack and recommendations for optimization of an Application under Test are presented to address the bottlenecks are presented.



TRIPLE SOFTWARE REDUNDANCY FAULT TOLERANT FRAMEWORK ARCHITECTURE

Thu, 27 Oct 2016 08:00:00 EDT

A computer implemented method of detecting a fault in a system comprises the steps of executing at least three virtual machines, each virtual machine executing a same application software, in separated and isolated memory segments and in a dedicated core of a multi-core processor; the virtual machines being synchronized and concurrently executed by a common hypervisor; wherein non-faulty virtual machines provide an identical output message within a predefined time-interval; detecting a fault in an output of a virtual machine, the fault corresponding to a different output message of the faulty virtual machine. Developments include a distributed vote mechanism, pull/push mechanisms, association of output vote messages with a safety extension comprising identification information, virtual machine recovery using data context.



DETECTING CAUSES OF PERFORMANCE REGRESSION TO ADJUST DATA SYSTEMS

Thu, 27 Oct 2016 08:00:00 EDT

At least one application in a computing environment is executed and one or more performance metrics of the application are measured. The measured performance metrics are analyzed and an operational performance regression is detected. The detected operational performance regression is correlated with one or more recorded changes and the correlated changes are identified as a cause of the operational performance regression. The elements of the computing environment are alerted in accordance with the identified changes to adjust operational performance.



DEBUGGING NON-DETERMINISTIC EMBEDDED SYSTEMS

Thu, 27 Oct 2016 08:00:00 EDT

An embedded device includes a processor executing instructions from module(s) in a code memory. The instructions specify: reading data from two non-deterministic registers (NDRs) of different types, compressing the data using respective, different compression algorithms, and storing the compressed data in a nonvolatile medium. A method of enabling debug tracing in a computer program product (CPP) includes locating instructions in the CPP that read NDRs, determining types of the NDRs, and adding instruction(s) to the CPP to compress the values read using compression algorithms corresponding to the respective NDR types. An emulator in a computer-readable medium receives emulation-target instructions (ETIs) and compressed NDR data, and emulates an execution sequence of the ETIs by determining NDR-reading instructions, determining a type of the NDR read by each, decompressing a portion of the NDR data using a type-specific decompressor, and updating emulated-machine state based on the decompressed portion.



Processor with Debug Pipeline

Thu, 27 Oct 2016 08:00:00 EDT

A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.



DISPERSED MULTI-MEDIA CONTENT FOR A CENTRALIZED DIGITAL VIDEO STORAGE SYSTEM

Thu, 27 Oct 2016 08:00:00 EDT

A method begins with a dispersed storage network (DSN) processing module receiving content retrieval message from one or more requesters. The method continues by determining DRM policies and read operational parameters. The method continues by retrieving a set of encoded data slices from DSN memory, the set of encoded data slices including unique subsets of the set of encoded data slices with each of the unique subsets assigned to one or more of the requesters based at least in part on the determined read operational parameters. The method continues by sending the set of encoded data slices to the requesters. The requestors select their assigned subset of the received set of encoded data slices and decode to produce the content.



MANAGEMENT AND UTILIZATION OF FAULT DOMAINS IN DISTRIBUTED CACHE SYSTEMS

Thu, 27 Oct 2016 08:00:00 EDT

Fault domains are defined which reflect, either physically or virtually, the topology of a networked computing environment. These defined fault domains are then used to control where cached data is replicated when running in a write back cache mode. Unlike known replication approaches, the present approach replicates such data according to a user's defined data policy and based on the defined fault domains thereby avoiding the user having to keep track of changes in computing system configurations or update their data policy when virtual machines migrate from one host computing system to another.



MANAGEMENT SYSTEM OF SERVER SYSTEM INCLUDING A PLURALITY OF SERVERS

Thu, 27 Oct 2016 08:00:00 EDT

For each of N active servers (N being an integer equal to or larger than 2), a management system performs, on at least one of M standby servers (M being an integer equal to or larger than 2), a full test for determining whether a failover is executable by performing a failover from the active server to the standby server, and performs, on at least one of the standby servers that is different from the standby server on which the full test is performed, a simplified test for determining whether the failover is executable without performing the failover from the active server to the standby server, the number of standby servers on which the simplified test is performed being larger than the number of standby servers on which the full test is performed.



Managing a Computing System Crash

Thu, 27 Oct 2016 08:00:00 EDT

A method, system and a computer program product for managing a computing system crash. Memory of the computing system is separated into at least two classifications, referred to herein as a dumpable area and a non-dumpable area. Upon detection of an operating system crash in the computing system, an operating system module prevents a dumping operation of the memory, including preventing access to the dumpable memory area, and divides the non-dumpable area into a new dumpable area and a new non-dumpable area. At such time as the operating system is rebooted, the dumping operation is initiated and completed in the dumpable area, and resumed operations use the non-dumpable area.



Managing a Computing System Crash

Thu, 27 Oct 2016 08:00:00 EDT

A system and a computer program product for managing a computing system crash. Memory of the computing system is separated into at least two classifications, referred to herein as a dumpable area and a non-dumpable area. Upon detection of an operating system crash in the computing system, an operating system module prevents a dumping operation of the memory, including preventing access to the dumpable memory area, and divides the non-dumpable area into a new dumpable area and a new non-dumpable area. At such time as the operating system is rebooted, the dumping operation is initiated and completed in the dumpable area, and resumed operations use the non-dumpable area.



Systems and Methods for Constructing Composable Persistent Data Structures

Thu, 27 Oct 2016 08:00:00 EDT

A technique referred to as “data structure chronicles” is described that may be used to build strictly failure resilient persistent concurrent data structures. A “chronicle” maintains a persistent history of operations invoked on a persistent data structure that can be replayed to recover the current consistent state of the data structure after a failure. The chronicle technique may also enable composability of data structure operations with the enclosing application. In addition, the chronicle technique is non-blocking, a desirable progress condition for concurrent data structures. A lock free, non-blocking chronicle stack algorithm is described that may outperform a lock-based implementation in the presence of high contention. In addition, a lock free, non-blocking chronicle queue algorithm is described.



RESILIENCY FRAGMENT TIERING

Thu, 27 Oct 2016 08:00:00 EDT

Technology is disclosed for a data storage architecture for providing enhanced storage resiliency for a data object. The data storage architecture can be implemented in a single-tier configuration and/or a multi-tier configuration. In the single-tier configuration, a data object is encoded, e.g., based on an erasure coding method, to generate many data fragments, which are stored across many storage devices. In the multi-tier configuration, a data object is encoded, e.g., based on an erasure coding method, to generate many data segments, which are sent to one or more tiers of storage nodes and at least one latent storage. Each of the storage nodes further encodes the data segment to generate many data fragments representing the data segment, which are stored across many storage devices associated with the storage node. The I/O operations for rebuilding the data in case of device failures is spread across many storage devices, which minimizes the wear of a given storage device.



PREFERRED STATE ENCODING IN NON-VOLATILE MEMORIES

Thu, 27 Oct 2016 08:00:00 EDT

The invention pertains to non-volatile memory devices, and more particularly to advantageously encoding data in non-volatile devices in a flexible manner by both NVM manufacturers and NVM users. Multiple methods of preferred state encoding (PSE) and/or error correction code (ECC) encoding may be used in different pages or blocks in the same NVM device for different purposes which may be dependent on the nature of the data to be stored.



ERROR CORRECTION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME

Thu, 27 Oct 2016 08:00:00 EDT

An error correction circuit includes: a failure detection unit suitable for detecting failed data among a plurality of data; a data output control unit suitable for selectively outputting test data corresponding to a predetermined amount of data excluding the failed data; and an error correction unit suitable for performing a unit ECC operation on the test data.



DATA ACCESSING METHOD, MEMORY CONTROLLING CIRCUIT UNIT AND MEMORY STORAGE APPARATUS

Thu, 27 Oct 2016 08:00:00 EDT

A data accessing method for a memory storage apparatus is provided. The method includes using a first check code circuit to generate a first check code corresponding to a first data stream and generating a first data set based on the first data stream and the first check code. The method also includes using a second check code circuit to obtain the first data stream and the first check code from the first data set and check the first data stream according to the first check code. The method still includes using a third check code circuit to generate a second check code according to the checked first data stream and generating a data frame based on the checked first data stream and the second check code and thereby programming the data frame into a physical programming unit.



ADVANCED BITWISE OPERATIONS AND APPARATUS IN A MULTI-LEVEL SYSTEM WITH NONVOLATILE MEMORY

Thu, 27 Oct 2016 08:00:00 EDT

A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read operations relating to the memory, can be changed on a codeword to codeword basis based on input parameters. The code efficiency can change based on changing any one of the input parameters including bit density that is stored by the memory. Storing and reading fractional bit densities is described.



SOFT ERROR DETECTION IN A MEMORY SYSTEM

Thu, 27 Oct 2016 08:00:00 EDT

In a memory having a memory array, a method includes reading read data from the memory array, and detecting a first bit error in the read data. The method further includes checking all bitcells in a radial search region about the first bit error. The radial search region is defined by a search radius which indicates a number of concentric rings of bitcells physically surrounding the first bit error in the memory array.



Reliable Map-Reduce Communications in a Decentralized, Self-Organizing Communication Orbit of a Distributed Network

Thu, 27 Oct 2016 08:00:00 EDT

Method and system for providing message communications with failure detection and recovery are disclosed. At a respective node of a non-static collection of nodes forming a linear communication orbit: the node identifies, from among the non-static collection of nodes, a set of forward contacts distributed in a forward direction along the linear communication orbit; the node monitors a propagation state of a first query that has departed from the respective node to travel in the forward direction along the linear communication orbit; and upon detecting a propagation failure of the first query based on the monitoring, the node sends the first query directly to a first forward contact among the set of forward contacts to initiate a failure recovery process within at least part of a segment of the linear communication orbit between the respective node and the first forward contact of the respective node.



Method and Apparatus for Repairing Dynamic Link Library File

Thu, 27 Oct 2016 08:00:00 EDT

A method for repairing a dynamic link library (DLL) file includes: reading an import section in an executable file; determining, according to DLL file information recorded in the import section and a pre-established correspondence between a DLL file and a save path, that a DLL file is lost; and notifying, when an instruction for running the executable file is received, that the DLL file is lost, and calling an installation package of the DLL file to repair the DLL file. The apparatus includes: a reading module, a determining module and a repairing module.



SET-BASED BUGS DISCOVERY SYSTEM VIA SQL QUERY

Thu, 27 Oct 2016 08:00:00 EDT

A system for bug discovery using event reports comprises an interface and a processor. The interface is configured to receive symptom data extracted from event reports from a user system. The symptom data is stored in a symptom database. The symptom data comprises one or more symptoms each with a corresponding symptom occurrence time. The processor is configured to compose one or more SQL queries using one or more bug definitions and determine an existence of one or more bugs of the user system based at least in part on a result of querying the symptom database using the one or more SQL queries.



IDENTIFYING SOLUTIONS TO APPLICATION EXECUTION PROBLEMS IN DISTRIBUTED COMPUTING ENVIRONMENTS

Thu, 27 Oct 2016 08:00:00 EDT

An expert system extracts events associated with executing an application from log files generated by various topological resources in a distributed computing environment. The events are plotted as plot points on a time series graph. Patterns are identified in the plot points that are associated with application problems, along with the computing environment configurations both before the problem and after the problem was resolved. The difference in the configurations represents a corrective action for the application problem, and the expert system links the corrective action to the pattern. When a pattern repeats in conjunction with another application problem, the corrective action is identified as a possible solution to the new problem. A confidence level associated with the pattern/corrective action may be increased when a user accepts the corrective action and may be decreased when a user rejects the corrective action.



TRACKING INCOMPLETE TRANSACTIONS IN CORRELATION WITH APPLICATION ERRORS

Thu, 27 Oct 2016 08:00:00 EDT

Various methods and systems for tracking incomplete purchases in correlation with application performance, such as application errors or crashes, are provided. In this regard, aspects of the invention facilitate monitoring transaction and application error events and analyzing data associated therewith to identify data indicating an impact of incomplete purchases in relation to an error(s) such that application performance can be improved. In various implementations, application data associated with an application installed on a mobile device is received. The application data is used to determine that an error that occurred in association with the application installed on the mobile device correlates with an incomplete monetary transaction initiated via the application. Based on the error correlating with the incomplete monetary transaction, a transaction attribute associated with the error is determined.



AUTOMATIC TARGETED SYSTEM SUSPENSION BASED UPON DOWNSTREAM SYSTEM FAILURE DETECTION

Thu, 27 Oct 2016 08:00:00 EDT

Techniques described herein relate to automatic system suspension based upon downstream system failure in service-oriented architecture (SOA) applications. A system management module of a SOA system may be configured to detect a problem with a downstream service provider involved with a SOA application, and in response, automatically suspend particular processing within the application to prevent requests that may end up at the downstream service provider from entering the SOA application. The system management module may implement a circuit breaker module that maintains a circuit breaker structure specific to a downstream endpoint leading to a downstream service provider. Upon a triggering of a circuit breaker for a downstream endpoint, one or more upstream service providers are identified as associated with faulted traffic causing the triggering, and the system management module can automatically cause further traffic from these upstream service providers to be suspended.



METHOD FOR CONTINUOUS OPERATION OF CONTROLLER FUNCTIONALITY DURING TRANSIENT FRAME OVERRUN

Thu, 27 Oct 2016 08:00:00 EDT

A method of adaptively reconfiguring controller functions during a frame overrun. A frame overrun condition is detected. A respective task from a plurality of tasks is identified as a largest contributor to the frame overrun. A mode associated with the identified task is identified to correct the frame overrun. Functions are reallocated within the identified task to one or more other tasks until the frame overrun condition is corrected. Respective functions reallocated are identified as a function of the identified mode.



DOUBLE WRITING MAP TABLE ENTRIES IN A DATA STORAGE SYSTEM TO GUARD AGAINST SILENT CORRUPTION

Thu, 27 Oct 2016 08:00:00 EDT

A method for writing data in a data storage device includes: writing data to a physical memory location in a non-volatile memory; writing, for a first time, to a location in a volatile memory corresponding to a logical address of the data, a physical address of the physical memory location of the non-volatile memory containing the data; and writing, for a second time, to the location in the volatile memory corresponding to the logical address of the data, the address of the physical memory location of the non-volatile memory containing the data. The physical address of the physical memory location is written with appended error detection code information, and the error detection code information is determined based on the logical address of the data.



POWER OVER ETHERNET MANAGEMENT DEVICES AND CONNECTION BETWEEN ETHERNET DEVICES

Thu, 27 Oct 2016 08:00:00 EDT

In one embodiment, a connection is maintained between a pair of ethernet ports that have circuitry connected in series with the ports and receiving power-over-ethernet (PoE) from one of the ports, by providing a controllable bypass circuit coupled to the pair of ethernet ports in parallel with the circuitry receiving power-over-ethernet, sensing a preselected condition, and opening and closing the bypass circuit in response to the presence or absence of the preselected condition. Power sourcing equipment (PSE) may supply the one of the ports with power over ethernet, and the circuitry may transports data between the pair of ethernet ports. The circuitry may also supply the switch with a control signal in response to the detection of the preselected condition.



PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER COUPLED TO SCI/SCO/PCO

Thu, 27 Oct 2016 08:00:00 EDT

The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.



PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER COUPLED TO SCI/SCO/PCO

Thu, 27 Oct 2016 08:00:00 EDT

The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.



INTERFACE CHIP AND BUILT-IN SELF-TEST METHOD THEREFOR

Thu, 27 Oct 2016 08:00:00 EDT

An interface chip with a built-in self-test mechanism. An electrical physical layer (EPHY) provides a signal to a transmission terminal of the interface chip, and gets a signal from a reception terminal of the interface chip. A digital code generator generates a source code to be scrambled as a scrambled code and then encoded by an encoder and conveyed to the EPHY to be converted into the signal that is provided to the transmission terminal by the EPHY. The EPHY further converts the signal received from the reception terminal into a receiving code to be decoded by a decoder as a decoded code and then descrambled by the descrambler as a restored code. When the transmission terminal is coupled back to the interface chip via the reception terminal, the code checker checks whether the restored code matches the source code.



SCAN TOPOLOGY DISCOVERY IN TARGET SYSTEMS

Thu, 27 Oct 2016 08:00:00 EDT

Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.



DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS

Thu, 27 Oct 2016 08:00:00 EDT

An integrated circuit has controller circuitry having coupled to a test clock and a test mode select inputs, and having state a register clock state output, a register capture state output, and a register update state output. Register circuitry has a test data in lead input, control inputs coupled to the state outputs of the controller circuitry, and a control output. Connection circuitry has a control input connected to the control output of the register circuitry and selectively couples one of a first serial data output of first scan circuitry and a second serial data output of second scan circuitry to a test data out lead. Selection circuitry has an input connected to the serial data input lead, an input connected to a test pattern source lead, a control input coupled to the scan circuitry control output leads, and an output connected to the scan input lead.



Serial Wire Debug Bridge

Thu, 27 Oct 2016 08:00:00 EDT

An integrated circuit (IC) having a bridge for interfacing a debugger and method of operating the same is provided. In one embodiment, an IC includes a debug control circuit and a debug interface block (DIB) implemented thereon. The DIB is coupled to the debug control circuit. The IC also includes an interface for a debugger and a number of interfaces for external circuits, each of the interfaces being coupled to the debug control circuit. The debug control circuit may function as a bridge for coupling an external debugger to the DIB and to external circuits coupled to the IC through corresponding ones of the interfaces. The debug control circuit may establish a connection between the debugger and one of the external circuits. Communications between the debugger and the external circuit may be conducted while bypassing the DIB.



Techniques for Transmitting Video Content to a Wirelessly Docked Device Having a Display

Thu, 20 Oct 2016 08:00:00 EDT

Examples are disclosed for transmitting video content. In some examples, cyclic redundancy check (CRC) values may be added to video content for video frames to be presented or displayed in a given region of a display. Results of CRC functions for consecutive video frames that use the added CRC values may be compared to determine whether the video content for the consecutive video frames is static video content. Video content for at least one of the consecutive video frames may be withheld from being transmitted if the video content for the consecutive video frames is characterized as static video content. Multiple CRC values or different CRC values may be added to further determine whether video content for the consecutive video frames or for subsequent consecutive video frames is also characterized as static video content. Other examples are described and claimed.



POLAR CODE PROCESSING METHOD AND SYSTEM, AND WIRELESS COMMUNICATIONS APPARATUS

Thu, 20 Oct 2016 08:00:00 EDT

A polar code processing method and system, and a wireless communications apparatus are provided, where the method includes: acquiring at least two periodic puncturing patterns and combining the at least two periodic puncturing patterns in a predetermined manner to obtain at least two hybrid puncturing patterns; selecting, from the at least two hybrid puncturing patterns, one with a lowest frame error rate as an optimal puncturing pattern; and performing rate matching on polar polar-coded bits according to the optimal puncturing pattern, and using the rate-matched bits as to-be-transmitted bits. A frame error rate may be reduced and HARQ performance of a polar code may be enhanced.



SYSTEMS, METHODS, APPARATUS, AND COMPUTER PROGRAM PRODUCTS FOR PROVIDING FORWARD ERROR CORRECTION WITH LOW LATENCY

Thu, 20 Oct 2016 08:00:00 EDT

Systems, methods, apparatus and computer program products for providing forward error correction with low latency to live streams in networks are provided, including outputting source data at a rate less than the rate of a source stream, building a buffer, FEC decoding the source data; and outputting the packets at a rate equal to the rate of the source stream.



STAIRCASE FORWARD ERROR CORRECTION CODING

Thu, 20 Oct 2016 08:00:00 EDT

In staircase forward error correction coding, a stream of data symbols are mapped to data symbol positions in a sequence of two-dimensional symbol blocks Bi, a positive integer. Each of the symbol blocks has data symbol positions and coding symbol positions. Coding symbols for the coding symbol positions in each symbol block Bi in the sequence are computed. The coding symbols are computed such that, for each symbol block Bi that has a preceding symbol block Bi−1 and a subsequent symbol block Bi+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block Bi−1, concatenated with the data symbols and the coding symbols along the other dimension in the symbol Bi, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol Bi, concatenated with the data symbols and the coding symbols along the other dimension in the subsequent symbol block Bi+1, form a codeword of the FEC component code. Thus, each row in [Bi−1T Bi] and each column in [BiBi+1T], for example, is a valid codeword.