Thu, 03 Nov 2016 08:00:00 EDTA hybrid automatic repeat request method includes receiving a packet sent by a transmit end; checking N data sub-blocks included in the packet, and generating feedback information according to a check result, where the feedback information includes N check characters corresponding to the N data sub-blocks, and the check character is an acknowledgment character ACK or a negative acknowledgment character NACK; and returning the feedback information to the transmit end. In technical solutions of the present disclosure, feedback information that includes N check characters corresponding to N data sub-blocks of a packet is used and the feedback information is returned to a transmit end, so that a data sub-block can be selected, according to the negative acknowledgment character NACK, to perform retransmission. Therefore, the transmit end can adaptively retransmit a data sub-block having an error, thereby improving resource utilization and reducing a transmission delay.
Thu, 03 Nov 2016 08:00:00 EDTA system is enabled to perform error checking and other HARQ processes at a remote radio unit device in cloud RAN systems that have a large front haul latency. The remote radio unit device performs error checking on transmissions received from a mobile device and sends an acknowledgement (ACK) or negative acknowledgement (NACK) to the mobile device based on whether errors are found.
Thu, 03 Nov 2016 08:00:00 EDTA method and device for performing forward error (FEC) correction avoidance based upon predicted block code reliability in a communications device is provided. An avoidance unit comprising a metric computation unit and a decision unit generates a reliability metric based upon a received code block. The reliability metric is compared to a reliability threshold, and the forward error correction decoder in the communications device is disabled if the metric is below or equal to the threshold.
Thu, 03 Nov 2016 08:00:00 EDTAn FEC coder in a transmission device according to an exemplary embodiment of the present disclosure performs BCH coding and LDPC coding based on whether a code length of the LDPC coding is a 16 k mode or a 64 k mode. A mapper performs mapping in an I-Q coordinate to perform conversion into an FEC block, and outputs pieces of mapping data (cells). The mapper defines different non-uniform mapping patterns with respect to different code lengths even an identical coding rate is used by the FEC coder. This configuration improves a shaping gain for different error correction code lengths in a transmission technology in which modulation of the non-uniform mapping pattern is used.
Thu, 03 Nov 2016 08:00:00 EDTVarious embodiments enable “bundled FEC protection,” in which a single repair flow may be used to provide recovery protection for a plurality of individual source RTP streams. The embodiment techniques may utilize novel FEC source payload and repair payload definitions that enable a single repair flow to be defined for multiple RTP flows. For example, as FEC FRAME Raptor code options do not currently address the case of bundled protection of multiple media types over multiple real-time transport protocol (RTP) synchronization sources (SSRC's), RTP stream header extensions may be utilized to allow a single FEC RTP stream to be configured to provide redundancy for a plurality of source RTP streams, regardless of their content type (e.g., audio or video). Based on such extensions, the embodiment techniques allow for protection of multiple source RTP streams that each has a unique sequence number space.
Thu, 03 Nov 2016 08:00:00 EDTMethods, apparatuses, and computer program products for transporting data from a sender to a receiver with low delay for interactive real-time media applications are described.
Thu, 03 Nov 2016 08:00:00 EDTDynamic forward error correction (FEC) setting is discussed in which the network determines a FEC percentage for each video segment of a video streaming service, based on consideration of the transfer length of the video segment and the allocated bandwidth. When the transfer length and allocated bandwidth reflect transmission of less than peak bandwidth, the network will determine a higher FEC percentage that uses the otherwise wasted bandwidth to transmit additional redundancy symbols. The additional redundancy symbols increase the error recovery rate when collisions occur between streaming video reception and page monitoring occasions of other networks in multi-network, multi-subscriber identification module (SIM) mobile devices. A network entity may then transmit the dynamic FEC percentage for each video segment in the file description table (FDT) associated with the video streaming service.
Thu, 03 Nov 2016 08:00:00 EDTA high-efficiency wireless local-area network (HEW) device including transceiver circuitry and processing circuitry is disclosed. The transceiver circuitry and processing circuitry may be configured to encode or decode a packet using a low-density parity check (LDPC) code four times longer than a legacy LDPC code and in accordance with a channel code, and to transmit or receive the packet. The LDPC code may be four times longer than the legacy LDPC code. The LDPC may be 7776 bits and the legacy LDPC code may be 1944 bits. The packet may be transmitted or received in accordance with 1024 QAM. The channel code may be 1/2, 2/3, 3/4, or 5/6. The LDPC subcarrier mapping may have an increased distance between sub-carriers compared with a legacy Institute of Electrical and Electronic Engineers 802.11 standard.
Thu, 03 Nov 2016 08:00:00 EDTA non-volatile memory system may include a tracking module that tracks logic values of bits to be stored in memory elements identified as unreliable. A record of the logic values may be generated. During decoding of the data, a log likelihood ratio module may use the record to assign log likelihood ratio values for the decoding.
Thu, 03 Nov 2016 08:00:00 EDTFor some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.
Thu, 03 Nov 2016 08:00:00 EDTA DTV transmitting system includes an encoder, a randomizer, a block processor, a group formatter, a deinterleaver, and a packet formatter. The encoder codes enhanced data for error correction, permutes the coded data, and further codes the permuted data for error detection. The randomizer randomizes the coded enhanced data, and the block processor codes the randomized data at an effective coding rate of 1/H. The group formatter forms a group of enhanced data having data regions, and inserts the coded enhanced data into at least one of the data regions. The deinterleaver deinterleaves the group of enhanced data, and the packet formatter formats the deinterleaved data into corresponding data bytes.
Thu, 03 Nov 2016 08:00:00 EDTThe present invention provides a method of transmitting broadcast signals. The method includes, formatting, by an input formatting block, input streams into plural PLPs (Physical Layer Pipes); encoding, by an encoder, data in the plural PLPs; processing, by a framing and interleaving block, the encoded data in the plural PLPs to output at least one signal frame; and waveform modulating, by a waveform generation block, data in the at least one signal frame and transmitting, by the waveform generation block, broadcast signals having the waveform modulated data.
Thu, 03 Nov 2016 08:00:00 EDTA parallel test device and method are disclosed, which relates to a technology for performing a multi-bit parallel test by compressing data. The parallel test device includes: a pad unit through which data input/output (I/O) operations are achieved; a plurality of input buffers configured to activate write data received from the pad unit in response to a buffer enable signal, and output the write data to a global input/output (GIO) line; a plurality of output drivers configured to activate read data received from the global I/O (GIO) line in response to a strobe delay signal, and output the read data to the pad unit; and a test controller configured to activate the buffer enable signal and the strobe delay signal during a test mode in a manner that the read data received from the plurality of output drivers is applied to the plurality of input buffers such that the read data is operated as the write data.
Thu, 03 Nov 2016 08:00:00 EDTA memory test data generating circuit and method for generating a plurality of sets of test data is provided. The plurality of sets of test data is provided to a memory via a plurality of channels by a memory controller and is for testing the memory. The memory test data generating circuit includes: a plurality of counters, generating a plurality of counter values; and a data repetition and combination unit, generating the plurality of sets of test data according to the plurality of counter values, a bit width between the memory test data generating circuit and the memory controller, and a bit width between the memory controller and the memory. The test data of each channel is an identical and periodical data series.
Thu, 03 Nov 2016 08:00:00 EDTA method for testing a software application is provided. The method may comprise associating a plurality of controls on a software application screen with testing actions to be performed on the controls, thereby creating a plurality of test steps, and generating a test component. The method may include analyzing a plurality of testing actions on a software application screen to learn characteristics of the testing actions and automatically assigning one or more parameters to one or more of the plurality of test steps based on a library that matches parameters to the names of testing actions. A parameter may comprise a reference to a column in a test data spreadsheet, which is separate from the test component and the library, the column in the test data spreadsheet comprising a plurality of different rows of test data to be utilized in conjunction with an associated control.
Thu, 03 Nov 2016 08:00:00 EDTA method for monitoring the operation of a component includes receiving a stream of data samples, wherein each data sample represents a value of a physical parameter of the component, identifying local extrema of the stream of data samples, storing information relating to each local extremum in a respective position of a fixed size buffer, and upon the presence of a cycle formed between two matching endpoints represented by two local maxima or two local minima: i) deleting at least one of the local extrema corresponding to the endpoints of the cycle from the buffer, and ii) storing information related to the cycle in a memory such that the information stored in the memory represents the operation of the component. When the buffer is full such that each position of the buffer contains information relating to a unique local extrema, the method further includes the steps of i) deleting the information relating to the oldest local extrema from the buffer, ii) calculating a pseudo cycle formed between two endpoints of which one endpoint is represented by the deleted oldest local extrema, and iii) storing information related to the calculated pseudo cycle in the memory.
Thu, 03 Nov 2016 08:00:00 EDTEmbodiments of the present invention utilize a dual buffer size threshold system for raising interrupts that allows DUT testing systems to perform real-time buffer memory allocation procedures in an on demand basis. Using dual interrupt threshold systems in the manner described by embodiments of the present invention, DUT testing systems can reduce the need to decide on a single buffer size threshold when testing a set of DUTs that separately provide different amounts of fail data relative to each other. As such, embodiments of the present invention can minimize the overhead processing spent on interrupt handling while also reducing the amount wait time needed for the data processing module to process fail data for each DUT. Thus, embodiments of the present invention can increase the use of tester resources more efficiently while decrease the amount of time a tester system spends collecting and/or analyzing fail data for a set of DUTs during a testing session.
Thu, 03 Nov 2016 08:00:00 EDTProvided are a computer program product, system, and method for a computer program product, system, and method for determining an availability score based on available resources of different resource types in a distributed computing environment of storage servers to determine whether to perform a failure operation for one of the storage servers. A health status monitor program deployed in the storage servers performs: maintaining information indicating availability of a plurality of storage server resources for a plurality of resource types; calculating an availability score as a function of a number of available resources of the resource types; and transmitting information on the availability score to a management program. The management program uses the transmitted information to determine whether to migrate services from the storage server from which the availability score is received to at least one of the other storage servers in the distributed computing environment.
Thu, 03 Nov 2016 08:00:00 EDTA system for monitoring a virtual machine executed on a host. The system includes a processor that receives an indication that a failure caused a storage device to be inaccessible to the virtual machine, the inaccessible storage device impacting an ability of the virtual machine to provide service, and applies a remedy to restore access to the storage device based on a type of the failure.
Thu, 03 Nov 2016 08:00:00 EDTA distributed delivery network for capacity enhancement of a communication link shared by multiple communication devices for network access service. The distributed delivery network may include one or more distributed storage devices, some of which may include at least one rotating disk storage device, a network interface, and one or more environmental sensors. Each distributed storage device may monitor data from the environmental sensor(s) and transition between an active state where messages are stored in or retrieved from the storage device, and a standby state where access is suppressed. The distributed storage devices may self-organize control operations for the distributed delivery network including message storage and retrieval and redundancy of messages, which may be determined by frequency of requests for the messages.
Thu, 03 Nov 2016 08:00:00 EDTIn a computer apparatus (100), an output management unit (200) determines for each data processing system configured with an OS (160), an application (170), and a management unit (180), depending on the state of the each processing system, whether or not a communication between each data processing system and a device is permitted. Further, the output management unit (200) controls for each data processing system the communication between each data processing system and the device in accordance with a determination result.
Thu, 03 Nov 2016 08:00:00 EDTSystems and methods for providing failover control in a control system are provided. For instance, a data stream from a plurality of computing nodes in a computing system can be monitored. A first subset of computing nodes can be selected based on the data streams. Control grant signals can be generated for each computing node of the first subset. An output to one or more computing nodes of the first subset can be activated based at least in part on a number of control grant signals generated for each computing node of the first subset. Control authority can then be granted to the one or more computing nodes of the first subset.
Thu, 03 Nov 2016 08:00:00 EDTTechniques are described for identifying unhealthy nodes in a multi-node system. One or more parameters of each node is monitored, then compared with the values for the same parameter running on other nodes in the multi-node system. Based on the comparison, a determination is made whether a node is healthy. If the multi-node system comprises one or more nodes with differing capabilities, an adjustment is performed to account for the differing capabilities of each respective node. Further provided are methods of taking remedial action upon a determination that a node is unhealthy. A tuner is used to modify values of health parameters until the node is performing similarly to its peers.
Thu, 03 Nov 2016 08:00:00 EDTAn information processing system includes first to third information processing apparatuses. The first information processing apparatus has a first memory with a cache region and outputs a first power failure signal on detecting a power failure. The second information processing apparatus includes a second memory with a mirror cache region that stores mirror data for the cache region and outputs a second power failure signal on detecting a power failure. The third information processing apparatus monitors the first and second information processing apparatuses and, when both apparatuses have stopped operating, determines whether there is a power failure at the first and second information processing apparatuses based on the first and second power failure signals. When there is no power failure at either apparatus, the first and second information processing apparatuses are restarted in a state where data of the first and second memories is held.
Thu, 03 Nov 2016 08:00:00 EDTA computer-implemented method for recovering data and concurrently rebuilding indexes for the recovered data in a database for a system configured to store fewer than all indexes in backup files may include copying data from one or more database files and storing the copied data to one or more backup files. A recovery manager executing on a processor may read the copied data from the one or more backup files and write the copied data to the one or more database files, wherein the data is recovered to the one or more database files. In response to the reading, an index manager executing on the processor may initiate a rebuilding of one or more indexes for the copied data at substantially the same time as the reading of the copied data.
Thu, 03 Nov 2016 08:00:00 EDTAn electronic device includes an application subsystem and a platform subsystem. The application subsystem includes one or more first independent processes that provide a user with different functions of the electronic device, a first process monitoring circuit that detects a handling-required state of the first independent process, and a system state managing circuit that reboots the first independent process in which the handling-required state has occurred. The first process monitoring circuit that has detected the handling-required state transmits an error notification to the system state managing circuit. The system state managing circuit that has received the error notification reboots the first independent process in the handling-required state.
Thu, 03 Nov 2016 08:00:00 EDTA modulation method has a high encoding rate for generating a pattern having a lower limit for the number of successive pixels in a spatial light modulator. An information recording device includes: an encoding unit that performs error correction encoding of input data; an interleaving unit that switches the output sequence of the error correction encoding unit; and an modulation unit that performs RLL modulation of the output of the interleaving unit on the basis of an RLL modulation trellis. A corresponding information reproducing device includes: a demodulation unit that uses a posteriori probability decoding based on the RLL modulation trellis, to perform RLL demodulation for reproducing recorded information; a deinterleaving unit that reverses the sequence switching; and a decoding unit that performs error correction code decoding using a posteriori probability decoding on the basis of the error correction encoding on the output of the deinterleaving unit.
Thu, 03 Nov 2016 08:00:00 EDTAn error protection key generation method and system are provided, the method being used to generate a key for use in computing an error protection code for an input data value according to a chosen error protection scheme. The method comprises inputting a plurality of desired data value sizes, and then applying a key generation algorithm to generate a key for use in computing the error protection code for a maximum data value size amongst the plurality of data value sizes. The key generation algorithm is arranged so that it generates the key so as to comprise a plurality of sub-keys, where each sub-key is associated with one of the input data value sizes, and where each sub-key conforms to a key requirement of the error protection scheme. As a result, a generic key is produced containing a plurality of sub-keys, where each sub-key is associated with a particular desired data value size, and can be extracted and used independently given that each sub-key conforms to the error protection scheme requirements. This provides significant benefits in the design and verification of error protection circuits using such keys.
Thu, 03 Nov 2016 08:00:00 EDTA method begins by a computing device of a dispersed storage network (DSN) encoding digital content into a plurality of sets of encoded data slices and generating at least one set of write commands, where a write command includes an indication of a number of copies of an encoded data slice to be stored. The method continues by a set of storage units of the DSN storing the plurality of sets of encoded data slices, where a storage unit stores the number of copies of the encoded data slice in accordance with the write command. The method continues by the set of storage units receiving a plurality of retrieval requests from a plurality of requesting computing devices regarding the digital content and fulfilling the plurality of retrieval requests utilizing various combinations of copies of encoded data slices of the plurality of sets of encoded data slices.
Thu, 03 Nov 2016 08:00:00 EDTA memory device controller includes an error correction processor and a compression processor. The error correction processor is configured to obtain error location information for page data received from a source memory block over a memory channel. The compression processor is configured to compress the obtained error location information, and to output the compressed error location information to a target memory block without the page data over the same memory channel.
Thu, 03 Nov 2016 08:00:00 EDTA paging scheme for a Solid State Drive (SSD) error correction mechanism that exchanges portions of a parity component, such as a page, between SRAM and less expensive DRAM, which stores the remainder of a context of pages. A parity operation applies an XOR function to corresponding memory positions in the pages of the context. Dedicated error correction (parity) SRAM need only enough memory for portions of memory, typically a cache line of a page, upon which the parity operation (XOR) is operating. The remaining portions in the context are swapped, or paged out, by cache logic such that the entire context is iteratively processed (XORed) by the parity operation.
Thu, 03 Nov 2016 08:00:00 EDTA post-encryption checksum is generated for a file to be stored on a remote storage location. It can be generated before sending the encrypted file to the remote storage system. A post-write checksum can be received from the remote storage system. The post-write checksum is generated after the encrypted file is written there. A comparison of the two checksums indicates whether the file has been correctly written to the remote storage system.
Thu, 03 Nov 2016 08:00:00 EDTIn some examples, fault of a code in an electronic device is detected. In response to detecting the fault, an update code is retrieved using a network stack from a network site over a network to update the code that has experienced the fault, during a state of the electronic device prior to completion of a boot procedure of the electronic device.
Thu, 03 Nov 2016 08:00:00 EDTA method for diagnosing an information processing device includes issuing a first interrupt that is an interrupt specific to a CPU, transferring a control from processing of the first interrupt to a second interrupt that starts a dump collection function, and starting a dump collection on the basis of the second interrupt.
Thu, 03 Nov 2016 08:00:00 EDTAn apparatus includes a memory to store objects of a plurality of classes, and a storage device to store plural pieces of dump data acquired at different times from the memory. The apparatus generates object-count information indicating a number of objects belonging to each of a plurality of classes, based on the plural pieces of dump data acquired at different times from a memory storing objects of the plurality of classes. The apparatus determines, for each class, at least a portion of dump data that includes a locally minimum number of objects in time variation of the number of objects of the each class, as first dump data that is candidate for storage, based on the generated object-count information. When reducing a total amount of dump data, the apparatus excludes the first dump data determined for each class from second dump data that is to be deleted.
Thu, 03 Nov 2016 08:00:00 EDTExample methods and apparatus to detect transport faults in media presentation systems are disclosed. An example method includes identifying, by executing an instruction with a processor, a cause leading to sending of a first transport failure alert associated with a media stream, counting, by executing an instruction with the processor, a number of false alerts associated with the cause, and when the number of false alerts associated with the cause satisfies a first threshold, adjusting, by executing an instruction with the processor, a second threshold used to determine whether to generate a second transport failure alert associated with the cause.
Thu, 03 Nov 2016 08:00:00 EDTAn operations management system, including a memory configured to store program instructions and a plurality of analytical models respectively used for detection of anomaly in a plurality of targets, and a processor configured to execute the program instructions including an order controller configured to control an processing order of the detection of anomaly performed by the operation management system to be the same as a descending order of score of anomaly of the plurality of targets, and an analyzer configured to detect, in the processing order, anomaly in each of the plurality of targets.
Thu, 03 Nov 2016 08:00:00 EDTA computing system can include a machine check counter (MCC) including a current value. The current value indicates a system reboot resetting hardware of the computing system. The machine check counter includes a model specific register including a counter indicating the current value, the current value to be incremented upon the system reboot.
Thu, 03 Nov 2016 08:00:00 EDTA method for diagnosing software crashes includes calculating, using vector space modeling, angles between vectors representing stack-traces from reports in a repository on one or more server computer systems, to define similarities in the reports, wherein reports are deemed similar where angles between their respective vectors are less than a threshold value. The method further includes grouping the reports into similar sets using a maximal cliques process and automatically diagnosing, in response to a received software crash, a first stack-trace extracted from a first report of the received software crash, to determine a potential solution to the received software crash.
Thu, 03 Nov 2016 08:00:00 EDTA semiconductor device includes a component and a self-diagnosis device. The self-diagnosis device includes a hardware secure module and a processor. The hardware secure module is configured to store a self-diagnosis policy for the component. The processor is configured to receive a detection signal output from a sensor, to diagnose a state of the component using the detection signal and the self-diagnosis policy stored in the hardware secure module, and to generate a control signal for controlling the state of the component according to the diagnosed state.
Thu, 03 Nov 2016 08:00:00 EDTSystems and methods are disclosed that enable errors to be mapped to data sources during request processing. Source data associated with a request is received by a client application and sent to a request processing application. A mapper module maps the source data from the client application to a standard format to form mapped data that can be processed by the request processing application. In response to an error during the mapping or processing of the request, data elements of the mapped data associated with the error are identified. The mappings are used to identify data elements of the source data associated with the error and generate error information sent back to the client application. The error information is displayed to a user and used by the client application to allow the user to modify the original source data elements associated with the error.
Thu, 03 Nov 2016 08:00:00 EDTA first control apparatus transmits, to a second control apparatus, a first error score based on an error detection situation at the time of accessing a first memory device through the second control apparatus, and transmits, to a third control apparatus, a second error score based on an error detection situation at the time of accessing a second memory device through the third control apparatus. The second control apparatus determines whether the first memory device malfunctions, based on a sum of a third error score based on the error detection situation at the time of accessing the first memory device and the received first error score. The third control apparatus determines whether the second memory device malfunctions, based on a sum of a fourth error score based on the error detection situation at the time of accessing the second memory device and the received second error score.
Thu, 03 Nov 2016 08:00:00 EDTA first control device includes a first storage unit holding a first error count and a first control unit that calculates the first error count, based on a status of an error detected when a storage device is accessed via a second control device, stores the calculated first error count in the first storage unit, and transmits the first error count to the second control device at predetermined timing. The second control device includes a second storage unit holding a second error count and a second control unit that calculates the second error count, based on a status of an error detected when the storage device is accessed, stores the calculated second error count in the second storage unit, and determines whether the storage device has malfunctioned, based on an aggregate value of the first error count received from the first control device and the second error count.
Thu, 03 Nov 2016 08:00:00 EDTAn SSD has a plurality of dies, with each die having a storage capacity. The storage capacity of each die is divided into a primary capacity and a spare capacity. A primary die has a maximum primary capacity, and a sum of the spare capacities of the remaining dies is greater than the maximum primary capacity. Data stored on the SSD is distributed among the primary capacities of the dies. When a failure of a first die is detected, data stored on the failed first die is migrated to the spare capacity of at least one of the remaining dies.
Thu, 03 Nov 2016 08:00:00 EDTA solid state drive (SSD) employing a redundant array of independent disks (RAID) scheme includes a flash memory chip, erasable blocks in the flash memory chip, and a flash controller. The erasable blocks are configured to store flash memory pages. The flash controller is operably coupled to the flash memory chip. The flash controller is also configured to organize certain of the flash memory pages into a RAID line group and to write RAID line group membership information to each of the flash memory pages in the RAID line group.
Thu, 03 Nov 2016 08:00:00 EDTA system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.
Thu, 03 Nov 2016 08:00:00 EDTThe present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device. According to the present disclosure, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug messages to the device and output test/debug messages from the device. The present disclosure advantageously allows a device to be tested and/or debugged without the device having any shared or dedicated test or debug interface terminals.
Thu, 03 Nov 2016 08:00:00 EDTA digital electronic circuit (DCCT) configured for testing in accordance with a Design-for-Test (“DFT”) technique such as a hierarchical, compressed random access scan (“CRAS-N”) DFT technique and, in particular, a segmented, random access scan a (“SRAS”) DFT technique.
Thu, 03 Nov 2016 08:00:00 EDTA simulation verification method for Field Programmable Gate Array (FPGA) function modules and a system thereof. The method includes: generating all test cases by enumerating all parameter characteristics of FPGA function modules; generating, according to an input type and input parameter characteristics of an FPGA function module under test, a simulation test bench matching configuration of the corresponding FPGA function module under test; and randomly generating, by the simulation test bench, a test stimulus and a corresponding expected output according to the input parameter characteristics of the FPGA function module under test, comparing the expected output with an actual output obtained after the test stimulus is applied to the test case corresponding to the FPGA function module under test, and outputting a test report of the FPGA function module under test according to a comparison result.
Thu, 03 Nov 2016 08:00:00 EDTDisclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.
Thu, 03 Nov 2016 08:00:00 EDTAn electronic device having a functional portion and a test portion. The test portion includes a boundary scan register formed by a plurality of test cells arranged in the body according to a register sequence, where first test cells are configured to form a serial-to-parallel converter and second test cells are configured to form a parallel-to-serial converter. The test cells are each coupled to a respective data access pin of the device and to a respective input/output point of the functional part and have a first test input and a test output. The boundary scan register defines two test half-paths formed, respectively, by the first test cells and by the second test cells. The first test cells are directly coupled according to a first sub-sequence, and the second test cells are directly coupled according to a second sub-sequence.
Thu, 03 Nov 2016 08:00:00 EDTIn certain embodiments, an integrated circuit has scan-test circuitry that performs scan testing on circuitry under scan test (OUST) within the IC, where the scan-test circuitry is susceptible to a defect. In order to enable the defect to be corrected after it occurs, the scan-test circuitry includes a set of programmable circuitry connected to provide a signal to other circuitry (e.g., a scan chain) within the scan-test circuitry, where the set of programmable circuitry includes one or more configurable memory cells connected to control the programming of the set of programmable circuitry. The memory cell(s) can be configured to program the set of programmable circuitry to enable the scan testing to be performed without modification. The memory cell(s) can also be configured to program the set of programmable circuitry to modify the scan testing to correct the defect in the scan-test circuitry.
Thu, 03 Nov 2016 08:00:00 EDTA probeless parallel test system for an integrated circuit (IC) includes an IC chip, a wireless power receiving module and a Build-In Self-Test (BIST) circuit. The wireless power receiving module is electrically connected to the IC chip. The BIST circuit is electrically connected to the wireless power receiving module and the IC chip. The wireless power receiving module, the BIST circuit and the IC chip are all formed on a wafer. The wireless power receiving module is used to provide electric power to the BIST circuit and the IC chip. When receiving the electric power, the IC chip executes a functional operation, and transmits an operation result to the BIST circuit for testing.