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SPREADING LOAD FOR HIGHLY POPULAR CONTENT WITH ASYNCHRONOUS COUNTED WRITES

Thu, 23 Feb 2017 08:00:00 EST

A method for execution by one or more processing modules of one or more computing devices of a dispersed storage network (DSN), the method begins by receiving a store data object request from the user device. The method continues by initiating storage of N instances of the received data object in the storage set. The method continues by issuing a status response to the user device when detecting that M instances have been successfully stored and sending an instance i of the data to the user device when receiving a read instance i of the data object request from the user device.



METHOD, SYSTEM AND APPARATUS FOR MONITORING ERROR CORRECTION DATA IN MEDIA SESSIONS

Thu, 23 Feb 2017 08:00:00 EST

A method, system and apparatus for monitoring error correction data are provided. The method comprises receiving an authorization request defining a media session between an AF server and a mobile device from the AF server. The authorization request contains a media packet flow identifier and a corresponding forward error correction (FEC) packet flow identifier. The method includes deploying policy rules for the media session to a gateway server, the policy rules including the media packet flow identifier and the FEC packet flow identifier; receiving periodic reports from the gateway server, the reports including packet counts for each of the media packet flow and the FEC packet flow; determining whether bandwidth consumed by the FEC packet flow exceeds a predetermined threshold; and when the determination is affirmative, sending an action request to the AF server.



ALLOCATION OF CLOUD COMPUTING RESOURCES

Thu, 23 Feb 2017 08:00:00 EST

The invention concerns a method, arrangement (26), computer program and a computer program product for allocating physical cloud computing resources (12, 16, 18) to processes, where at least some of the cloud computing resources (12, 16, 18) have different ages, said cloud computing resources (12, 16, 18) having individual primary failure probabilities, each being based on an age dependent failure probability function of the cloud computing resource. The receives requests for performing computational tasks for a number of processes, where the processes have different process priorities, investigates the availability of the cloud computing resources for performing the tasks of the requests, and assigns the available cloud computing resources to the based on the process priorities, where processes with the highest process priorities are assigned to the cloud computing resources (12, 16, 18) having the lowest primary failure probabilities.



TECHNIQUES FOR ERROR HANDLING IN PARALLEL SPLITTING OF STORAGE COMMANDS

Thu, 23 Feb 2017 08:00:00 EST

Various embodiments are generally directed to techniques for handling errors affecting the at least partially parallel performance of data access commands between nodes of a storage cluster system. An apparatus may include a processor component of a first node, an access component to perform a command received from a client device via a network to alter client device data stored in a first storage device coupled to the first node, a replication component to transmit a replica of the command to a second node via the network to enable performance of the replica by the second node at least partially in parallel, an error component to retry transmission of the replica based on a failure indicated by the second node and a status component to select a status indication to transmit to the client device based on the indication of failure and results of retrial of transmission of the replica.



METHOD OF EXCHANGING DATA PACKAGES BETWEEN FIRST AND SECOND PORTABLE COMMUNICATION DEVICES

Thu, 23 Feb 2017 08:00:00 EST

The present disclosure relates to a method of exchanging data packages between first and second portable communication devices over a bi-directional wireless communication channel. The method includes generating, by the first portable communication device, a first data package belonging to a first packet category comprising audio data or to a second packet category without audio data and transmitting the first data package from the first portable communication device to the second portable communication device through the wireless communication channel. Where an acknowledgement indicator of the second data package is unset or the second data package is absent, the first portable communication device retransmits the first data package from the first to the second portable communication device for at the most N times if the first data package belongs to the first packet category; N being a positive integer between 1 and 4.



APPARATUS FOR FREE-SPACE OPTICAL COMMUNICATIONS AT HIGH DATA RATES

Thu, 23 Feb 2017 08:00:00 EST

Systems and methods for optical communication through air or space are disclosed. A method includes encoding one or more data frames with a data-link layer forward error correction (FEC) code to produce a plurality of encoded data frames and transmitting the plurality of encoded data frames from a transmitter (TX) to a receiver (RX) at least partially through air or space using a plurality of optical beams. The RX identifies a corrupted encoded data frame and reconstructs the corrupted encoded data frame using a data-link layer FEC decoder operating over a plurality of non-corrupted encoded data frames.



Low-Delay Packet Erasure Coding

Thu, 23 Feb 2017 08:00:00 EST

Provided is a method for correcting errors in a data transmission network, comprising: transmitting a plurality of uncoded information packets across a network path; transmitting a plurality of coded packets for recovering information packets lost in transmission across said network path, the coded packets being temporally interspersed among said uncoded information packets, wherein the coded packets are encoded based on information packets transmitted prior to a previously transmitted coded packet; and determining the interspersion of the coded packets according to a packet loss rate.



CODING SCHEMES INCLUDING ALTERNATIVE CODINGS FOR A SINGLE CODE CONSTRUCT

Thu, 23 Feb 2017 08:00:00 EST

A coding scheme for coding “code constructs” (for example, alphanumeric characters) into “bit sequences,” where at least one of the code constructs is assigned at least two different bit sequences (that is, a first bit sequence and a second bit sequence). This is sometimes referred to herein as “alternative codings for a single code construct.” In some embodiments, at least one of the alternative codings includes bits that can be used for error detection and/or correction. In some embodiments, the code scheme will be similar to a pre-existing code scheme that does not have alternative codings for a single code construct so that the alternative-codings coding scheme is back compatible with data encoded under the pre-existing coding scheme.



Bi-Directional Parity Bit Generator Circuit

Thu, 23 Feb 2017 08:00:00 EST

A parity bit generator module is disclosed that operates in a first direction or a second direction. In the first direction, the parity bit generator module generates parity bits for a first input datastream having information bits and combines these parity bits with the information bits of the input datastream to provide a first output datastream. Otherwise in a second direction, the parity bit generator module separates information bits from a second input datastream and generates parity bits from the information bits of the second input datastream to provide a second output datastream having the parity bits. In various exemplary embodiments, the bi-directional parity bit generator is implemented as part of an encoding/decoding module and/or an error-correcting code (ECC) data storage device.



CODED MODULATION ARCHITECTURE USING SPARSE REGRESSION CODES

Thu, 23 Feb 2017 08:00:00 EST

A communication system is configured to use coded modulation architecture using sparse regression codes. A transmitter includes a plurality of antenna and processing circuitry configured to: divide a data signal into a plurality of layers, allocate power individually to each of the plurality layers, encode a subset of the plurality of layers, the subset comprising a number of layers less than the whole, and interleave the subset of the plurality of layers. A receiver includes a plurality of antenna and processing circuitry configured to divide a received data signal into a plurality of layers and perform layer-by-layer decoding on the received data and control signals.



MODULATOR AND MODULATION METHOD USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING 3/15 CODE RATE

Thu, 23 Feb 2017 08:00:00 EST

A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 3/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.



LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 3/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

Thu, 23 Feb 2017 08:00:00 EST

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).



READ VOLTAGE OFFSET

Thu, 23 Feb 2017 08:00:00 EST

Apparatuses, methods, and data structures that can be utilized to provide a read voltage offset are described. One or more apparatuses can include a memory device and a controller coupled to the memory device and configured to: access a data structure comprising write temperature data corresponding to a number of data segments stored in the memory device; read a particular data segment using a read voltage offset determined based on: the write temperature data from the data structure and corresponding to the particular data segment; and read temperature data corresponding to the particular data segment.



METHOD AND MEMORY CONTROLLER

Thu, 23 Feb 2017 08:00:00 EST

A method includes setting a first logical value in a control resistor provided in a variable delay control circuit that is included in a memory controller, detecting a first stuck-at fault of a second logical value that is a value except for the first logical value, the first stuck-at fault having occurred in one of a plurality of control lines, in accordance with a result of a comparison between a logical value output from the memory controller and an expected value of the logical value, setting the second logical value in the memory controller, and detecting a second stuck-at fault of the first logical value, the second stuck-at fault having occurred in one of the plurality of control lines, in accordance with a result of a comparison between a logical value output from the memory controller and an expected value of the logical value.



TEST DEVICES AND TEST SYSTEMS

Thu, 23 Feb 2017 08:00:00 EST

A test device includes a data driver and a controller. The controller is configured to generate a test code by dividing a test sequence in a unit of n-bits. The data driver is configured to receive the generated test code and output one of input voltages to a device under test as a test signal based on the generated test code. A storage device stores a test sequence.



MULTI-CHANNEL TESTING

Thu, 23 Feb 2017 08:00:00 EST

Apparatus and methods can include an interface chip that can include a test channel to couple to a memory tester, a memory channel controller to couple with a plurality of memory arrays via a plurality of memory channels, and a test circuit coupled between the test channel and the channel controller, the test circuit to provide first and second test clock information to the memory channel controller. In certain examples, the test circuit can operate to receive multiple commands and to propagate the multiple commands to groups of memory channels substantially simultaneously in order to test cross-channel interference using the multi-channel memory. Additional apparatus and methods are disclosed.



TO-BE-STUBBED TARGET DETERMINING APPARATUS, TO-BE-STUBBED TARGET DETERMINING METHOD AND NON-TRANSITORY RECORDING MEDIUM STORING TO-BE-STUBBED TARGET DETERMINING PROGRAM

Thu, 23 Feb 2017 08:00:00 EST

A to-be-stubbed target determining apparatus includes: a processor that executes a determining program; and a memory that stores the determining program; wherein according to determining program, the processor: extracts relational information that represents a relation between a program under test and one or more functions which are called from the program under test; and determines, according to the relational information, from among the one or mode functions, a function that returns a user-defined type of instance accessed in the program under test and a function that returns a value used as a condition of a conditional branch in the program under test, as a first function excluded from functions to be stubbed.



TEST MACHINE MANAGEMENT

Thu, 23 Feb 2017 08:00:00 EST

A method includes distributing the plurality of test cases to any available test agents, wherein each test case out of the plurality of test cases does not have any associated preconditions. The method receives event information for a first test case out of the plurality of test cases from a first test agent. Responsive to determining the event information for the first test case includes a satisfied condition for a second test case, the method determines whether the satisfied condition for the second test case relates to a global variable or local variable. The method handles the second test case, wherein handling the second test case includes distributing the second test case to the first test agent subsequent to the first test agent becoming available if the satisfied condition relates to the local variable.



EVALUATING USER EXPERIENCE

Thu, 23 Feb 2017 08:00:00 EST

Evaluating user experience for an application includes collecting, for each of a plurality of sessions of the application, a list of user event data items experienced during that session. The list of user event data items includes any of a device utilization quantifier, user action-response time pairs, and an application fault indicator. For each session, a value is assigned to each collected user event data item, and a session score is derived based on those assigned values. A user experience score is derived based upon a plurality of the derived session scores. The user experience score is reported.



TRACING OF EXCEPTION HANDLING EVENTS

Thu, 23 Feb 2017 08:00:00 EST

An apparatus comprises trace circuitry to output exception trace data indicating exception handling events detected during monitoring of processing activity of processing circuitry. A configuration element maintains exception trace configuration data for controlling the output of the exception trace data via the trace circuitry. When output of exception trace data is enabled, the trace circuitry selects, in dependence on the exception trace configuration data, how much of the exception trace data to output.



Tracing Interconnect Circuitry

Thu, 23 Feb 2017 08:00:00 EST

A method of tracing transactions on an integrated circuit chip. The method comprises, for each transaction: extracting the transaction from interconnect circuitry of the integrated circuit chip, the transaction comprising an address signal and a data signal; applying a filtering condition to the address signal; only if the address signal does not fail the filtering condition, storing the address signal in an address trace buffer; storing the data signal in a data trace buffer; applying a triggering condition to the stored transaction; and outputting the stored transaction if the stored transaction matches the triggering condition.



INTEGRATING SYSTEM DYNAMICS MODELLING INTO INFORMATION SYSTEM QUALITY MEASUREMENT IN DETERMINING QUALITY OF AN INFORMATION SYSTEM

Thu, 23 Feb 2017 08:00:00 EST

A method, apparatus and system for updating a causal loop diagram of quality meters for an information system, including retrieving the causal loop diagram of the quality meters for the information system, the diagram comprising at least a first quality meter, and a second quality meter and an interaction between them with its strength. The invention further includes receiving online measurement data for the first quality meter; receiving online measurement data for the second quality meter; processing the received online measurement data by statistical analysis to determine a measured interaction with its strength between the first quality meter and the second quality meter; comparing the measured interaction with its strength to the retrieved interaction with its strength; and updating the retrieved interaction in the causal loop diagram of quality meters for an information system, if the measured interaction with its strength is different to the retrieved interaction with its strength.



MANAGING A SHARED POOL OF CONFIGURABLE COMPUTING RESOURCES WHICH USES A SET OF DYNAMICALLY-ASSIGNED RESOURCES

Thu, 23 Feb 2017 08:00:00 EST

Disclosed aspects manage a shared pool of configurable computing resources. A set of resource assignment data is established. The set of resource assignment data indicates a first host of the shared pool of configurable computing resources includes a set of dynamically-assigned resources. An error event with respect to the first host is detected. In response to detecting the error event with respect to the first host, a determination is made to perform a resource action based on the set of resource assignment data. The resource action, which is related to the set of dynamically-assigned resources, is performed.



COMPLIANCE TESTING THROUGH SANDBOX ENVIRONMENTS

Thu, 23 Feb 2017 08:00:00 EST

A compliance user or auditor is enabled to inject failures into a sandbox environment which maybe similar to a production service. The sandbox environment, may be monitored by the same automation that watches compliance controls in the production service. As the user injects compliance failures into the sandbox, they may detect the appropriate alerts fire in the monitoring system, thereby gaining trust that the monitoring works as it should. A rich report resulting from the test activities may allow the user or auditor to see how a failure of a compliance control leads to the expected monitoring alert.



TEST MACHINE MANAGEMENT

Thu, 23 Feb 2017 08:00:00 EST

A computer program product includes creating a test suite, wherein the test suite includes a plurality of test cases for execution on a plurality of test agents. The method distributes a first portion of test cases to any available test agents, wherein each test case out of the first portion of test cases does not have any associated preconditions. The receives test results and event information for a first test case out of the first portion of test cases from a first test agent. Responsive to determining the event information for the first test case includes a satisfied condition for a second test case with one or more associated preconditions, the method determines whether the satisfied condition for the second test case relates to a global variable or local variable.



IDENTIFYING FAILURE MECHANISMS BASED ON A POPULATION OF SCAN DIAGNOSTIC REPORTS

Thu, 23 Feb 2017 08:00:00 EST

Systems and techniques for identifying failure mechanisms based on a population of scan diagnostic reports is described. Given a population of scan diagnostic reports, a mixed membership model can be used for computing a topic distribution for each portion of each scan diagnostic report and a feature distribution for each topic. The failure mechanisms can be identified based on the topic distributions for the portions of the scan diagnostic reports and the feature distributions for the topics.



Assisted Coherent Shared Memory

Thu, 23 Feb 2017 08:00:00 EST

An apparatus for coherent shared memory across multiple clusters is described herein. The apparatus includes a fabric memory controller and one or more nodes. The fabric memory controller manages access to a shared memory region of each node such that each shared memory region is accessible using load store semantics, even in response to failure of the node. The apparatus also includes a global memory, wherein each shared memory region is mapped to the global memory by the fabric memory controller.



FAST WRITE MECHANISM FOR EMULATED ELECTRICALLY ERASABLE (EEE) SYSTEM

Thu, 23 Feb 2017 08:00:00 EST

A method of operating an emulated electrically erasable (EEE) memory system includes entering a quick write mode for a predetermined amount of time, upon detection of imminent power loss of the EEE memory system. A first write request is received immediately subsequent to entering the quick write mode, where the first write request includes a first address of an emulated memory of the EEE memory system and associated first data to be written at the first address. A first new record is created in non-volatile memory of the EEE memory system during the quick write mode, where the first new record includes the first address, the associated first data, and a blank record status identifier. The first new record is updated to have a quick record status ID, in response to a determination that record data of the first new record passes verification.



COMPUTE ARCHITECTURE IN A MEMORY DEVICE OF DISTRIBUTED COMPUTING SYSTEM

Thu, 23 Feb 2017 08:00:00 EST

A method performed by a processing module embedded in a solid state memory device begins by receiving at least one partial task related to a group of slices of contiguous data, and slices of the group of slices of contiguous data to produce received slices. The received slices are random access stored in the solid state memory device, and the processing module decides whether to execute the at least one partial task. In response to a positive determination, a portion of the received slices are random access retrieved, and the at least one partial task is executed using the portion of the received slices to generate a partial result. The partial result is random access stored in the solid state memory device; and the processing module facilitates dispersed storage of the partial result in a distributed storage task network (DSTN).



Simultaneous Multi-Processor Apparatus Applicable to Acheiving Exascale Performance for Algorithms and Program Systems

Thu, 23 Feb 2017 08:00:00 EST

Apparatus adapted for exascale computers are disclosed. The apparatus includes, but is not limited to at least one of: a system, data processor chip (DPC), Landing module (LM), chips including LM, anticipator chips, simultaneous multi-processor (SMP) cores, SMP channel (SMPC) cores, channels, bundles of channels, printed circuit boards (PCB) including bundles, floating point adders, accumulation managers, QUAD Link Anticipating Memory (QUADLAM), communication networks extended by coupling links of QUADLAM, log 2 calculators, exp2 calculators, log ALU, Non-Linear Accelerator (NLA), and stairways. Methods of algorithm and program development, verification and debugging are also disclosed. Collectively, embodiments of these elements disclose a class of supercomputers that obsolete Amdahl's Law, providing cabinets of petaflop performance and systems that may meet or exceed an exaflop of performance for Block LU Decomposition (Linpack).



TRANSACTIONAL DISTRIBUTED LIFECYCLE MANAGEMENT OF DIVERSE APPLICATION DATA STRUCTURES

Thu, 23 Feb 2017 08:00:00 EST

A state manager provides transactional distributed lifecycle management of a group of different application-level state providers, namely, differently structured application program data structures. The state providers are atomic with respect to one another. The state provider is replicated to one or more secondary nodes of a distributed network. The state providers are persistent despite one or more node operational failures. State provider lifecycle operations include creation of a transactional distributed state provider as a member of a group of different application-level state providers which include differently structured application program data structures, deletion of a previously created transactional distributed state provider, and/or enumeration of any previously created transactional distributed state providers. A given state provider may be read or written by one or more applications. Implementation restrictions and other avoidance conditions are satisfied in particular cases.



SYSTEM AND METHOD FOR SUPPORTING TRANSACTION AFFINITY BASED REQUEST HANDLING IN A MIDDLEWARE ENVIRONMENT

Thu, 23 Feb 2017 08:00:00 EST

A system and method can support transaction processing in a middleware environment. A processor, such as a remote method invocation stub in the middleware environment, can be associated with a transaction, wherein the transaction is from a first cluster. Then, the processor can handle a transactional request that is associated with the transaction, wherein the transactional request is to be sent to the first cluster. Furthermore, the processor can route the transactional request to a said cluster member in the first cluster, which is an existing participant of the transaction.



METHOD AND SYSTEM FOR PERFORMING AUTOMATIC SYSTEM RECOVERY

Thu, 23 Feb 2017 08:00:00 EST

A method for performing automatic system recovery is implemented by a server including a control chipset and a baseboard management controller (BMC). In the method, when a current image file is corrupted, a recovery engine generates an indicator of a version of the current image file and transmits the indicator to the BMC. The BMC then transmits a request for a backup image file to an external electronic device. After the BMC receives file link information of a disk image file from the electronic device, the BMC accesses the electronic device to download the disk image file, and mounts the disk image file as a virtual disk on the BMC. Afterward, the recovery engine replaces the current image file with the disk image file from the virtual disk.



NUMERICAL CONTROLLER

Thu, 23 Feb 2017 08:00:00 EST

If a numerical controller detects abnormality of data when data stored in a volatile memory is read out in backup of the data stored in the volatile memory to an external memory, the numerical controller compares an address of an abnormal data, which is detected, with an address stored in a non-volatile memory. When it is determined that the abnormal data which is detected is data of an invalid area, the numerical controller continues the backup processing.



DETERMINING SLICES USED IN A RECONSTRUCTION

Thu, 23 Feb 2017 08:00:00 EST

A method for a dispersed storage network (DSN) begins by receiving a read data object request from for a data object stored as a plurality of sets of encoded data slices in a set of storage units. The method continues by selecting a read threshold number of encoded data slices for retrieval. The method continues by issuing read slice requests to at least some of the storage units of the storage set to recover the selected read threshold number of encoded data slices. The method continues by receiving read slice responses from at least some of the storage units and selecting a decode threshold number of encoded data slices. The method continues by decoding the selected decode threshold number of encoded data slices to reproduce the data and generating audit information based on the selected slices for retrieval, the received slice, and the selected slices for decoding.



Distributed Erasure Coded Virtual File System

Thu, 23 Feb 2017 08:00:00 EST

A plurality of computing devices are communicatively coupled to each other via a network, and each of the plurality of computing devices comprises one or more of a plurality of storage devices. A plurality of failure resilient address spaces are distributed across the plurality of storage devices such that each of the plurality of failure resilient address spaces spans a plurality of the storage devices. Each one of the plurality of failure resilient address spaces is organized into a plurality of stripes. Each one or more stripes of the plurality of stripes is part of a respective one of a plurality of forward error correction (FEC) protection domains. Each of the plurality of stripes may comprise a plurality of storage blocks. Each block of a particular one of the plurality of stripes may reside on a different one of the plurality of storage devices.



PROCESSOR-IN-MEMORY-AND-STORAGE ARCHITECTURE

Thu, 23 Feb 2017 08:00:00 EST

A method and apparatus for performing reliable general-purpose computing. Each sub-core of a plurality of sub-cores of a processor core processes a same instruction at a same time. A code analyzer receives a plurality of residues that represents a code word corresponding to the same instruction and an indication of whether the code word is a memory address code or a data code from the plurality of sub-cores. The code analyzer determines whether the plurality of residues are consistent or inconsistent. The code analyzer and the plurality of sub-cores perform a set of operations based on whether the code word is a memory address code or a data code and a determination of whether the plurality of residues are consistent or inconsistent.



MEMORY REPAIR METHOD AND APPARATUS BASED ON ERROR CODE TRACKING

Thu, 23 Feb 2017 08:00:00 EST

A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.



FLASH MEMORY CODEWORD ARCHITECTURES

Thu, 23 Feb 2017 08:00:00 EST

A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.



DETECTING STORAGE ERRORS IN A DISPERSED STORAGE NETWORK

Thu, 23 Feb 2017 08:00:00 EST

A method includes determining a root cause for a rebuilding request of an encoded data slice of a set of encoded data slices, where the rebuilding request includes a slice name of the encoded data slice corresponding to a slice error. The method further includes establishing a pricing level as a user pricing level when the root cause is a user-centric root cause, and establishing the pricing level as a non-user pricing level when the root cause is a non-user-centric root cause. The method further includes facilitating the rebuilding of the encoded data slice, and generating billing information for the rebuilding based on the pricing level.



USING REASON CODES TO DETERMINE HOW TO HANDLE MEMORY DEVICE ERROR CONDITIONS

Thu, 23 Feb 2017 08:00:00 EST

A method for dispersed storage network (DSN) begins by detecting a memory error associated with a memory device of a storage unit. The method continues by identifying an error descriptor code based on the detected memory error. The method continues by determining whether to perform an intermediate action based on the error descriptor code. The method continues, when not performing the intermediate action, by issuing memory status information to the DSTN managing unit. The method continues, when performing the intermediate action, by performing the intermediate action to produce an action result. The method continues by determining whether the memory device is to remain in service based on one or more of the action result and the error descriptor code and, when the memory device is not to remain in service, issuing further status information to the DSTN managing unit to indicate the failed status indicator.



MANAGEMENT APPARATUS, COMPUTER AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM HAVING MANAGEMENT PROGRAM RECORDED THEREIN

Thu, 23 Feb 2017 08:00:00 EST

Erroneous detection of a communication failure accompanying an OS shutdown is prevented by including a communication failure detector configured to detect a communication failure concerning a data communication path, a software monitor configured to detect an abnormally stopped state of management software when the communication failure is detected, and a failure manager configured to confirm a power state of a computer, after waiting for a time period taken to shut down the computer from the detection of the communication failure in a case where the abnormally stopped state of the management software is detected, and cancel, when the computer is confirmed to be in a power-off state, the communication failure detected.



MEMORY DEVICE AND OPERATING METHOD THEREOF

Thu, 23 Feb 2017 08:00:00 EST

A memory device may include: a plurality of memory cells; at least one address storage unit; a fail detection unit suitable for comparing first and second read data that are read from at least one memory cell selected among the plurality of memory cells to detect a fail, and storing an address of the selected memory cell in the address storage unit when the fail is detected; and a refresh control unit suitable for refreshing the memory cell corresponding to the address stored in the address storage unit at a higher frequency than the other memory cells.



MEMORY SYSTEM

Thu, 23 Feb 2017 08:00:00 EST

A memory system may include a memory module including a plurality of memory devices suitable for storing a data word containing multi-bit data, and a memory controller suitable for controlling a write operation and a read operation of the memory module and distributing and mapping the data word to the plurality of memory devices, wherein as a memory device has a higher error occurrence count among the memory devices, the controller maps higher-significant bits of the multi-bit data to the memory device.



Electrical Hub Including Current Sensor

Thu, 23 Feb 2017 08:00:00 EST

A method and system provides current, from an electrical hub, to a device. The method and system further receives, at the electrical hub, an indication that the device is in a first configuration state of a plurality of configuration states. An example includes detecting, at the electrical hub, a detected current value of the current sent to the device. Processes include determining, at the electrical hub, whether to generate an error indication based on a comparison of the detected current value and a first reference value or range of values associated with the first configuration state.



AGGRESSIVE SEARCHING FOR MISSING DATA IN A DSN MEMORY THAT HAS HAD MIGRATIONS

Thu, 23 Feb 2017 08:00:00 EST

A method a dispersed storage network (DSN) begins by detecting a missing encoded data slice storage error associated with a current revision of a storage resource mapping, where storage resources of the DSN are selected for storage of encoded data slices in accordance with a distributed agreement protocol function on an identifier of the encoded data slices utilizing the current revision of the storage resource mapping. The method continues by accessing, for one or more previous revisions, a storage resource mapping history to identify a next oldest revision of the storage resource mapping. The method continues by determining, for a location cycle, whether the missing encoded data slice is available from a previous storage resource in accordance with the identified next oldest revision of the storage resource mapping and when locating the data within the previous storage resource, facilitating migration of the missing encoded data slice.



METHOD FOR PREDICTING A FAULT IN A CABIN TEMPERATURE CONTROL SYSTEM OF AN AIRCRAFT

Thu, 23 Feb 2017 08:00:00 EST

A method of predicting a fault in a cabin temperature control system of an air-conditioning system of an aircraft is disclosed. The method includes transmitting data related to a temperature, pressure, valve position, or actuator position of the cabin temperature control system, comparing the transmitted data to a reference value, and predicting a fault in the cabin temperature control system based on the comparing.



STORING AND RETRIEVING MUTABLE OBJECTS

Thu, 23 Feb 2017 08:00:00 EST

A method for execution by one or more processing modules of one or more computing devices of a dispersed storage network (DSN), the method begins by identifying a data object to access within a DSN. The method continues by identifying a vault ID based on the data object. The method continues by obtaining an object ID based on the data object. The method continues by selecting at least one generation ID based on generation status. The method continues, for each generation ID, by generating at least one set of slice names using the vault ID, the generation ID, and the object ID. The method continues, for each set of slice names, by generating a set of slice access requests that includes the set of slice names and accessing the DSN utilizing the set of slice access requests.



OPTIMAL STORAGE AND WORKLOAD PLACEMENT, AND ENSURING HIGH RESILIENCY IN GEO-DISTRIBUTED CLUSTER SYSTEMS

Thu, 23 Feb 2017 08:00:00 EST

Technologies for cluster systems that are natively geo-site-aware. Such a cluster system makes use of this awareness to determine the subsets of nodes located at various geo-sites at physical configuration, to optimize workload placement based on the geo-sites, to make failover and failback decisions based on the geo-sites, and to assign voting and prune nodes for quorum management based on the geo-sites. Such capabilities result in cluster systems that are more resilient and more efficient in terms of resource usage than cluster systems without such native geo-site awareness.



SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST

Thu, 23 Feb 2017 08:00:00 EST

Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.