Thu, 03 Nov 2016 08:00:00 EDTA semiconductor memory device according to an embodiment includes a memory cell array and a control circuit. The memory cell array includes: a plurality of first conductive layers that are stacked; a memory layer provided on a side surface of the plurality of the first conductive layers; and a second conductive layer that contacts the side surface of the plurality of the first conductive layers via the memory layer. A thickness of the first conductive layer disposed at the first position is larger than a thickness of the first conductive layer disposed at the second position. The control circuit is configured to apply a first voltage to a selected first conductive layer. The control circuit changes a value of the first voltage based on a position of the selected first conductive layer.
Thu, 03 Nov 2016 08:00:00 EDTA semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.
Thu, 03 Nov 2016 08:00:00 EDTA method of storing one or more bits of information comprising: forming a magnetic bubble; and storing a said bit of information encoded in a typology of a domain wall of said magnetic bubble. Preferably a bit is encoded using a symmetric topological state of the domain wall and a topological state including at least one winding rotation of a magnetisation vector of the domain wall. Preferably the magnetic bubble is confined in an island of magnetic material, preferably of maximum dimension less than 1 μm.
Thu, 03 Nov 2016 08:00:00 EDTA non-volatile memory system may include a mechanism for analyzing and measuring/predicting data loss without reading data in memory cells of the non-volatile memory. The system may include a data management module that utilizes charge loss measurements of a reference charge device that is independent of the memory cells that are configured to store data. The measured charge loss may be correlated with a predetermined data loss profile for the non-volatile memory that corresponds with charge loss on the reference charge device. The method may include charging the reference charge device when the non-volatile memory system is being powered down and making the charge loss measurement, and estimating data loss, when the non-volatile memory system is later powered up. The non-volatile memory cells may be refreshed when the estimated data loss is above a predetermined threshold.
Thu, 03 Nov 2016 08:00:00 EDTAccording to one embodiment, a semiconductor memory device includes a plurality of stacked first chips and a second chip. The second chip outputs a first signal to the first chips. The first chip outputs status information at timing based on the received first signal. The first chip shifts the received first signal and outputs the shifted first signal to the first chip of a next stage in synchronization with the first clock signal. The second chip receives a plurality of status information output in a serial manner from the first chips.
Thu, 03 Nov 2016 08:00:00 EDTAccording to one embodiment, a semiconductor storage device includes a memory cell array and a controller. The memory cell array includes a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell. The controller writes data having n values (n is natural numbers of 2 or more to k or less) in the second memory cell and simultaneously writes the fourth memory cell, after writing the data having the n values in the first memory cell. When reading the data from the first memory cell, the controller reads data of the first memory cell and the third memory cell which is selected simultaneously with the first memory cell and, changes a read voltage of the first memory cell based on the data read from the third memory cell.
Thu, 03 Nov 2016 08:00:00 EDTAccording to one embodiment, there is provided a semiconductor storage device including a memory cell array and a control circuit. The memory cell array has multiple memory cells connected to word lines and bit lines. The control circuit sets a value of a control voltage used to control voltages on the bit lines at a first value and, if receiving a first command including a change request to change the control voltage and including a to-be-changed-to second value, changes the value of the control voltage used to control the voltages on the bit lines from the first value to the second value, according to the change request.
Thu, 03 Nov 2016 08:00:00 EDTThe method of operating a non-volatile memory device includes dumping data stored in input latches of a page buffer to other latches of the page buffer to receive second data to be written to a second cell group of a memory cell array from outside the non-volatile memory device during writing of first data to a first cell group of the memory cell array. In the method, receiving of the second data may be finished before the writing of the first data is finished.
Thu, 03 Nov 2016 08:00:00 EDTIn a non-volatile memories formed according to a NAND type of architecture, one or more of the end word lines on the source end, drain end, or both are set aside as dummy word lines that are not used to store user data. In addition to the host data, a memory system typically also stores metadata, or information about the user data, how it is stored and the memory system itself. Techniques are presented for using the dummy word lines of the memory blocks to hold this metadata. This arrangement allows for the metadata of a memory block to be known in real time, without reducing the storage capacity of the memory system.
Thu, 03 Nov 2016 08:00:00 EDTA three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy word line of different word line configuration disposed between a string select line and an upper most main word line.
Thu, 03 Nov 2016 08:00:00 EDTA computing device includes a memory array built of several sections having memory cells arranged in rows and column, at least one cell in each column of the memory array being connected to a bit line; and at least one multiplexer to connect a bit line in a first column of a first section to a bit line in a second column in a second section different from the first section, where the second column is not continuous with the first column ; and a decoder to activate at least two word lines of the first section and a word line connected to a cell in the second column in the second section to write a bit line voltage associated with a result of a logical operation performed on the first column into the cell in the second column.
Thu, 03 Nov 2016 08:00:00 EDTCPUs are not effective for search processing for information on a memory. Content-addressable memories (CAMs) are effective for information searches, but it is difficult to build a large-capacity memory usable for big data using the CAMs. A large-capacity memory may be turned into an active memory having an information search capability comparable to that of a content-addressable memory (CAM) by incorporating an extremely small, single-bit-based parallel logical operation unit into a common memory. With this memory, a super fast in-memory database capable of fully parallel searches may be realized.
Thu, 03 Nov 2016 08:00:00 EDTA memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.
Thu, 03 Nov 2016 08:00:00 EDTA forming method includes: applying a first pulse voltage to a second electrode to a variable-resistance nonvolatile memory element in first state; and executing at least once a sequence that includes determining whether the variable-resistance nonvolatile memory element is in a second state, and continuously applying a second pulse voltage followed by a third pulse voltage to the variable-resistance nonvolatile memory element when the variable-resistance nonvolatile memory element is determined not to be in the second state.
Thu, 03 Nov 2016 08:00:00 EDTA semiconductor memory device includes a memory cell array having first wires, a second wire, and memory cells connected to the first and second wires, and a control circuit that can apply writing voltages to the second wire. One of the memory cells connected to the selected second wire and a selected first wire is a selected memory cell. One of the memory cells connected to the selected second wire and an unselected first wire is a semi-selected memory cell. When writing data into the selected memory cell, the control circuit selects one from the writing voltages and applies the one writing voltage to a third wire connected to the selected second wire. The control circuit selects the one writing voltage, based on a first current flowing through the second wire when each of the memory cells connected to the selected second wire are set as semi-selected memory cells.
Thu, 03 Nov 2016 08:00:00 EDTA bipolar resistive switching device including an electrically conductive bottom electrode, a stack of transition metal oxides layers, a number of transition metal oxide layers being equal or greater than 2, the stack including: at least one MOx layer, at least one oxygen gettering layer NOy, wherein the resistive switching device further includes an electrically conductive top electrode.
Thu, 03 Nov 2016 08:00:00 EDTAn embodiment of the invention provides a sensing device. The sensing device includes a controller, a Resistive random memory sensor, an access circuit and a comparator circuit. The access circuit accesses the Resistive random memory sensor. The comparator circuit is coupled to the controller and the access circuit. The controller writes a predetermined data to the Resistive random memory sensor via the access circuit. After a predetermined condition, the access circuit reads a first data from the Resistive random memory sensor. The comparator circuit compares the first data with the predetermined data and transmits a comparison result to the controller. The controller determines whether an abnormal condition occurs based on the comparison result.
Thu, 03 Nov 2016 08:00:00 EDTThere is provided a method of detecting offset in a sense amplifier of an sRAM memory unit. The method comprises using a sense amplifier of the SRAM memory unit to implement a read of a first data value stored in a memory cell of the SRAM memory unit, and measuring a first time for the sense amplifier to read the first data value. The method further comprises using the sense amplifier to implement a read of a second data value stored in a memory cell of the SRAM memory unit, and measuring a second time for the sense amplifier to read the second data value. The method then comprises calculating a difference between the first time and the second time, and determining whether an offset adjustment should be applied to the sense amplifier in dependence upon the difference between the first time and the second time.
Thu, 03 Nov 2016 08:00:00 EDTA memory device includes a first inverter, a second inverter cross-coupled with the first inverter, an accessing unit, and a switching unit. The accessing unit is configured to discharge an output of the first inverter and charge an output of the second inverter according to signals provided by a first word line and a second word line. The switching unit is configured to disconnect a power from the first inverter and the second inverter according to a signal provided by the first word line.
Thu, 03 Nov 2016 08:00:00 EDTA system-on-chip and an electronic device including the system-on-chip are provided. The system-on-chip includes a power switch, a logic block, a memory device, and a buffer. The power switch is coupled between a first power supply line and a virtual power supply line, and turns on in response to a switch control signal. The logic block is coupled between the virtual power supply line and a ground line. The memory device is coupled between a second power supply line and the ground line. The buffer is coupled between the second power supply line and the ground line, and generates the switch control signal based on a sleep signal.
Thu, 03 Nov 2016 08:00:00 EDTA memory device capable of optimizing a refresh cycle is provided. The memory device includes a monitor circuit capable of generating a signal serving as a trigger for a refresh operation. The monitor circuit includes a transistor and a capacitor. The monitor circuit has a function of sensing that a potential retained in the capacitor is lower than a reference potential, a function of generating a first signal and a second signal on the basis of the sensing result, and a function of turning on the transistor in response to the second signal and resetting the potential retained in the capacitor to an initialization state. It is possible to start refresh of a memory cell in response to the first signal.
Thu, 03 Nov 2016 08:00:00 EDTA dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.
Thu, 03 Nov 2016 08:00:00 EDTProvided is a memory device having a plurality of memory cells and a refresh circuit. Each of the memory cells is configured to retain multiple data as a potential of a node connected to a gate of a first transistor, one of a source and a drain of a second transistor, and one of electrodes of a capacitor. The refresh circuit is configured to refresh the memory cells. That is, the refresh circuit is configured to determine an interval between refresh operations, estimate a change of the potential of the node due to the leakage of the charge, and provide a refresh potential to the memory cells, where the refresh potential is a sum of the potential read from the node and the potential lost due to the charge leakage.
Thu, 03 Nov 2016 08:00:00 EDTNon-volatile flip-flops (NVFFs) based circuitries and schemes that incorporate magnetic tunnel junctions (MTJs) are provided to ensure fast data storage and restoration from an intentional or unintentional power outage. The NVFFs based circuitries and schemes also include enhanced scan mode testing capability by exploiting the nonvolatile latch to function as hold latch for delay testing. The NVFFs based circuitries and schemes eliminate additional write drivers, and may operate at an operation frequency of, for example, up to 2 GHz at a supply voltage of 1.1 V and with 0.55 pJ of energy consumption. A near uniform write latency can be achieved through transistor sizing, given write asymmetry of MTJs. NVFFs based circuitries and schemes incorporating data-dependent power gating circuitries can be used to mitigate high static currents generated during retention and back-to-back writing of identical input data.
Thu, 03 Nov 2016 08:00:00 EDTA MRAM cell including a first tunnel barrier layer between a soft ferromagnetic layer having a free magnetization and a first hard ferromagnetic layer having a first storage magnetization. A second tunnel barrier layer is between the soft ferromagnetic layer and a second hard ferromagnetic layer and has a second storage magnetization. The first storage magnetization is freely orientable at a first high predetermined temperature threshold and the second storage magnetization being freely orientable at a second predetermined high temperature threshold. The first high predetermined temperature threshold is higher than the second predetermined high temperature threshold. The MRAM cell can be used as a ternary content addressable memory (TCAM) and store up to three distinct state levels. The MRAM cell has a reduced size and can be made at low cost.
Thu, 03 Nov 2016 08:00:00 EDTThermal-spin-torque (TST) in a magnetic tunnel junction (MTJ) is demonstrated by generating large temperature gradients across ultrathin MgO tunnel barriers, with this TST being significant enough to considerably affect the magnitude of the switching field of the MTJ. The origin of the TST is attributed to an asymmetry of the tunneling conductance across the zero-bias voltage of the MTJ. Through magneto-Seebeck voltage measurements, it is estimated that the charge-current that would be generated due to the temperature gradient would give rise to spin-transfer-torque (STT) that is a thousand times too small to account for the observed changes in switching fields, indicating the presence of large TST.
Thu, 03 Nov 2016 08:00:00 EDTMemory cell, method for operating the memory cell and method of forming the memory cell are disclosed. The memory cell includes a first selector having a first select transistor with a first gate coupled to a first wordline and first and second source/drain (S/D) regions, and a second selector having at least a second select transistor with a second gate coupled to a second wordline and first and second S/D regions. The memory cell includes a first magnetic tunnel junction (MTJ) element coupled between a first bit line and the first S/D region of the first select transistor, and a second MTJ element coupled between a second bit line and the first S/D region of the second select transistor.
Thu, 03 Nov 2016 08:00:00 EDTA magneto-optical device comprising a magnetic unit and an optical unit, an electronic device comprising the magneto-optical device, a method of energy saving using the magneto-optical device, an array comprising the magneto-optical devices, and a method of changing magnetic orientation.
Thu, 03 Nov 2016 08:00:00 EDTA memory device has a burst length “b”, performs “k” core accesses per command, and receives a command, where “b” is an integer of at least 2 and “k” is an integer of at least 2 and at most “b”. The memory device includes a memory cell array comprising a plurality of bank groups, a plurality of bank group control units respectively corresponding to the plurality of bank groups, each of the bank group control units configured to generate a multiplexer control signal for selecting part of data read from a corresponding bank group, and a multiplexer configured to sequentially output data read from the plurality of bank groups according to the multiplexer control signal output from the plurality of bank group control units. Data items comprised in output data of the multiplexer have a same time space.
Thu, 03 Nov 2016 08:00:00 EDTA data storage device includes a nonvolatile memory apparatus including a plurality of pages coupled to a single word line; and a controller suitable for accessing the nonvolatile memory apparatus during one of first and second modes, wherein, the second mode is enabled when the nonvolatile memory apparatus has reached a lifetime limit, and wherein the controller stores the same data in both of a source page and a dummy page during the second mode.
Thu, 03 Nov 2016 08:00:00 EDTA write voltage generation circuit includes: a power supply terminal that receives an external power supply voltage; a boosting circuit that boosts the external power supply voltage to generate a boosted voltage; and a selector that selects either one of the external power supply voltage and the boosted voltage, and outputs the selected voltage as the write voltage. The selector selects the external power supply voltage as the write voltage in a first part of a write period for writing data to a memory cell, and selects the boosted voltage as the write voltage in a latter part of the write period.
Thu, 03 Nov 2016 08:00:00 EDTA semiconductor memory device includes a plurality of memory banks in a first region, a data terminal to which an input data signal is input, the data terminal being in a second region, and an inverting circuit that inverts or non-inverts the input data signal in response to an inversion control signal indicating whether the input data signal has been inverted, wherein at least one inverting circuit is disposed for each of the plurality of memory banks.
Thu, 03 Nov 2016 08:00:00 EDTAn extensible configurable FPGA storage structure and an FPGA device, where the FPGA storage structure includes: a plurality of local storage units, a controller and two clock buffers, where the two clock buffers are separately used for providing different clock signals for two clock input ports of the controller; the controller is used for receiving a write address signal input externally, and driven by the clock signals, generating a plurality of enable signals and write address decoding signals to be output to the plurality of local storage units; and each of the local storage units includes a local memory and a multiplexer used for providing input data for the local memory; and, based on a configuration mode of each local storage unit, generates output data in the corresponding configuration mode according to the enable signals, input write address decoding signals or read address signals, and the input data.