Subscribe: Untitled
http://www.freepatentsonline.com/rssfeed/rssapp365.xml
Added By: Feedage Forager Feedage Grade B rated
Language: English
Tags:
array  bit line  bit  cell  circuit  control  data  device  line  memory cell  memory device  memory  semiconductor  voltage 
Rate this Feed
Rate this feedRate this feedRate this feedRate this feedRate this feed
Rate this feed 1 starRate this feed 2 starRate this feed 3 starRate this feed 4 starRate this feed 5 star

Comments (0)

Feed Details and Statistics Feed Statistics
Preview: Untitled

Untitled





 



NON-VOLATILE MEMORY DEVICE AND NON-VOLATILE MEMORY SYSTEM INCLUDING THE SAME

Thu, 23 Feb 2017 08:00:00 EST

A non-volatile memory device is provided as follows. A substrate has a peripheral circuit. A first semiconductor layer is disposed on the substrate. The first semiconductor layer includes a memory cell region. A first gate structure is disposed on the first semiconductor layer. The first gate structure includes a plurality of first gate electrodes stacked in a perpendicular direction to the first semiconductor layer and a plurality of vertical channel structures penetrating the plurality of first gate electrodes. The first gate structure is arranged in the memory cell region. A second gate structure is disposed on the substrate. The second gate structure includes a plurality of second gate electrodes stacked in the perpendicular direction to the first semiconductor layer. The second gate structure is arranged outside the memory cell region.



OTP MEMORY INCLUDING TEST CELL ARRAY AND METHOD OF TESTING THE SAME

Thu, 23 Feb 2017 08:00:00 EST

In a one-time programmable (OTP) memory and a method of testing the same. The OTP memory includes an OTP cell array comprising OTP cells which are activated by an address received from a source external to the OTP memory and which OTP cells are unprogrammed. A test cell array includes a first test row having unprogrammed first test cells and a second test row having mask-programmed second test cells, and sharing bit lines extending in a column direction with the OTP cell array. The first test cells and second test cells are accessible during testing of the OTP cell array.



SEMICONDUCTOR DEVICE AND DEVICE FOR A SEMICONDUCTOR DEVICE

Thu, 23 Feb 2017 08:00:00 EST

Various embodiments generally relate to a semiconductor device and a device for a semiconductor device, and more particularly, to a technology relating to a margin of a data retention time. The semiconductor device may include a repair detection unit configured to determine whether an inputted address is a repair address and output a repair detection signal. The semiconductor device may include a refresh control unit configured to simultaneously activate two or more word lines in response to a refresh command signal and sequentially activate the two or more word lines according to the repair detection signal.



STORAGE ELEMENT WITH STORAGE AND CLOCK TREE MONITORING CIRCUIT AND METHODS THEREFOR

Thu, 23 Feb 2017 08:00:00 EST

A storage element with monitoring circuit, comprising a previous state information storage element configured to record a previous state of a monitored state information storage element, a state change indication unit having a clock input terminal coupled to the clock signal input interface, a state change indication unit being configured to generate a state change indication signal indicative of whether the monitored state information storage element shall have performed a state change by observing the data at a data input interface and a data output terminal, and a state change confirmation unit configured to generate a storage fault indicator by observing the data output terminal of the monitored state information storage element and the data output of the previous state information storage element and checking whether the result of this observation is in line with the state change indicator.



APPARATUSES AND/OR METHODS FOR OPERATING A MEMORY CELL AS AN ANTI-FUSE

Thu, 23 Feb 2017 08:00:00 EST

Embodiments disclosed herein relate to operating a memory cell as an anti-fuse, such as for use in phase change memory, for example.



Memory System with Small Size Antifuse Circuit Capable of Voltage Boost

Thu, 23 Feb 2017 08:00:00 EST

A memory system includes a control block, an antifuse voltage generator, an array voltage generator, and a memory array. The control block is used to output control signals to the memory array according to a memory control data signal. The antifuse voltage generator is used to output an antifuse control signal to the memory array according to a control signal and a driving voltage. The array voltage generator is used to output a selection signal and a following control signal to the memory array according a control signal. The memory array is coupled to the control block, the antifuse voltage generator, and the array voltage generator and configured to access data according to the first control signal, the antifuse control signal, the selection signal, and the following control signal. The first control signal comprises address information of the memory array.



SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTIVALUED DATA

Thu, 23 Feb 2017 08:00:00 EST

Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.



DISTURB FREE BITCELL AND ARRAY

Thu, 23 Feb 2017 08:00:00 EST

Approaches for a memory including a cell array are provided. The memory includes a first device of the cell array which is connected to a bitline and a node and controlled by a word line, and a second device of the cell array which comprises a third device which is connected to a source line and the node and controlled by the word line and a fourth device which is connected between the word line and the node. In the memory, in response to another word line in the cell array being activated and the word line not being activated to keep the first device in an unprogrammed state, the third device isolates and floats the node such that a voltage level of a gate to source of the first device is clamped down by the fourth device to a voltage level around zero volts.



MEMORY SYSTEM

Thu, 23 Feb 2017 08:00:00 EST

According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.



HIGH VOLTAGE ARCHITECTURE FOR NON-VOLATILE MEMORY

Thu, 23 Feb 2017 08:00:00 EST

A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL).



HIGH VOLTAGE REGULATOR

Thu, 23 Feb 2017 08:00:00 EST

Disclosed herein is a regulator for a non-volatile memory is provided. The regulator comprises an operational amplifier for receiving a reference voltage and a feedback voltage to output a voltage amplifying the difference of the reference voltage and the feedback voltage, the feedback voltage being obtained by dividing an output voltage of the regulator; a first switching unit turning on in response to the amplified voltage; a second switching unit electrically connected between a first node and the first switching unit for protecting the first switching unit from the voltage of the first node; and a third switching unit providing the output voltage of the regulator to a second node in response to a voltage of the first node.



PROGRAM AND READ TRIM SETTING

Thu, 23 Feb 2017 08:00:00 EST

A trim set register for a memory device has a plurality of individual trim settings. Each trim setting has a program trim value, a step-up trim value, and a program pulse width. A trim setting may be assigned to a portion of the memory device based on a program speed of the portion of the memory device.



NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

Thu, 23 Feb 2017 08:00:00 EST

A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.



PROVISION OF HOLDING CURRENT IN NON-VOLATILE RANDOM ACCESS MEMORY

Thu, 23 Feb 2017 08:00:00 EST

Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.



SEMICONDUCTOR STORAGE DEVICE

Thu, 23 Feb 2017 08:00:00 EST

A semiconductor memory solves performance degradation of a memory device caused by performance of memory functions different depending on a position of a memory cell array. In the memory cell array including memory cells in each of which a memory element is electrically connected to one of a source and a drain of a cell transistor, the cell transistor includes at least two types with different current driving capability according to a position in the memory cell array.



SEMICONDUCTOR MEMORY DEVICE

Thu, 23 Feb 2017 08:00:00 EST

Provided is a semiconductor memory device. The semiconductor memory device includes: a memory cell; a sensing circuit connected to the memory cell via a first bit line and a second bit line different from the first bit line, the sensing circuit configured to sense data stored in the memory cell; and a bit line voltage control circuit connected to the memory cell via the first bit line and the second bit line, the bit line voltage control circuit configured to precharge the first bit line to a first voltage that is lower than a supply voltage and to precharge the second bit line to a second voltage that is lower than the supply voltage and is different from the first voltage.



Using Sense Amplifier As A Write Booster In Memory Operating With A Large Dual Rail Voltage Supply Differential

Thu, 23 Feb 2017 08:00:00 EST

A memory includes a memory cell that operates in response to an array supply voltage, and a corresponding pair of bit lines that are pre-charged to a periphery supply voltage prior to each access of the memory cell. A sense amplifier coupled to the bit lines operates in response to the periphery supply voltage. The periphery supply voltage is less than the array supply voltage to enable power savings within the memory. A first pair of transistors is configured to couple the sense amplifier to the bit lines during write accesses to the memory cell, thereby boosting the write voltages applied to the bit lines during a write operation. That is, the first pair of transistors is configured such that the sense amplifier pulls one of the bit lines toward the periphery supply voltage (and the other one of the bit lines toward the ground supply voltage) during write accesses.



DATA AWARE WRITE SCHEME FOR SRAM

Thu, 23 Feb 2017 08:00:00 EST

Approaches for providing write-assist for a Static Random Access Memory (SRAM) array are provided. A circuit includes a control circuit connected to a cell in a SRAM array. The control circuit is configured to: apply a first voltage to a first pull down transistor of the cell during a write operation to the cell; and apply a second voltage, different than the first voltage, to a second pull down transistor of the cell during the write operation.



COMPARISON OPERATIONS IN MEMORY

Thu, 23 Feb 2017 08:00:00 EST

One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array. The comparison operation compares the first value to the second value, and the method can include storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.



SEMICONDUCTOR DEVICE WITH IMPROVED SENSE MARGIN OF SENSE AMPLIFIER

Thu, 23 Feb 2017 08:00:00 EST

Semiconductor devices capable of a sensing margin of a semiconductor device are described. A semiconductor device may include a plurality of mats, a plurality of sensing circuits, a plurality of connecting circuits, and a plurality of mat dividing circuits. The mats are divided into upper regions and lower regions and activated by word lines. The sensing circuits are arranged in regions among the plurality of mats and are configured to sense/amplify data applied from the plurality of mats. The connecting circuits are configured to control connections between the mats and the sensing circuits in correspondence to a plurality of bit line selection signals. The mat dividing circuits are configured to selectively connect bit lines of the upper regions and the lower regions to each other in correspondence to a plurality of mat selection signals.



MEMORY CONTROLLER

Thu, 23 Feb 2017 08:00:00 EST

A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.



MEMORY SYSTEM AND CACHE MEMORY

Thu, 23 Feb 2017 08:00:00 EST

A memory system has a non-volatile memory including a plurality of circuit blocks using different voltages, a power-off switch circuitry that switches whether or not voltage supply to each of the plurality of circuit blocks in the non-volatile memory is cut off, and a power-off controller that controls the switching of the power-off switch circuitry based on at least one of circuit volumes of the plurality of circuit blocks, standby power of the plurality of circuit blocks, and a circuit volume of the power-off switch circuitry.



MEMORY APPARATUSES HAVING GROUND SWITCHES

Thu, 23 Feb 2017 08:00:00 EST

A resistive memory apparatus includes a memory cell array having a plurality of memory cells and a first ground switch. The plurality of memory cells are arranged in a plurality of rows and a plurality of columns, and each memory cell in a first column of the plurality of memory cells is connected between a first bitline and a first source line. The first ground switch is connected in parallel with the first source line, and the first ground switch is configured to selectively provide a first current path from the first bitline to ground through a selected memory cell in the first column of the plurality of memory cells and the first source line, the current path traversing only a portion of the first source line.



PROGRAMMING MEMORY ELEMENTS USING TWO PHASE BOOST

Thu, 23 Feb 2017 08:00:00 EST

Memory devices, such as MRAM devices, are described that comprise memory elements for storing data and configuration logic for programming memory elements using a two phase boost. The memory devices perform the two phase boosting to program anti-parallel data values during a first programming phase and to program parallel data values during a second programming phase that is subsequent to the first programming phase. The voltage boost is provided by a high percentage of memory elements in a memory device by simultaneously transitioning the source line of the memory elements from a reference voltage to a source voltage during the first programming phase to effectively double the activation voltage for gates of transistors in the memory elements to program anti-parallel data values. Methods are also described for programming memory elements using a two phase boost.



MAGNETIC ELEMENT, SKYRMION MEMORY AND ARITHMETIC PROCESSING UNIT

Thu, 23 Feb 2017 08:00:00 EST

To provide a magnetic element that controls generation and annihilation of a skyrmion. A magnetic element is provided, and the magnetic element comprises: a magnetic body that has a spiral magnetic structure in a stable state; a skyrmion control unit that generates skyrmion in the magnetic body by supplying energy to the magnetic body that has the spiral magnetic structure. Also, the magnetic element in which the skyrmion control unit brings the magnetic body into an unstable state by supplying thermal energy pulses to the magnetic body is provided. Furthermore, a skyrmion memory comprising the magnetic element is provided.



MULTIPLE-HOT (MULTI-HOT) BIT DECODING IN A MEMORY SYSTEM FOR ACTIVATING MULTIPLE MEMORY LOCATIONS IN A MEMORY FOR A MEMORY ACCESS OPERATION

Thu, 23 Feb 2017 08:00:00 EST

Multiple-hot (multi-hot) bit decoding in a memory system for activating multiple memory locations in a memory for a memory access operation are disclosed. In one aspect, a multi-hot bit decoding system is provided that includes a memory access control system that includes a decoder. The decoder is configured to decode an address for a memory access operation into a single-hot bit decode word for activating a memory row at the encoded address. To automatically access another memory row(s) for a memory access operation, the memory access control system also includes a mapping circuit configured to provide an additional decode word(s) for activating another memory row(s) based on the address. The decode word and additional decode word(s) are merged to provide a multi-hot bit decode word that is asserted onto a decode wordline such that multiple memory rows are activated for a memory access operation.



NONVOLATILE MEMORY DEVICE FOR PERFORMING DUTY CORRECTION OPERATION, MEMORY SYSTEM, AND OPERATING METHOD THEREOF

Thu, 23 Feb 2017 08:00:00 EST

A nonvolatile memory device suitable for sequentially performing a ZQ calibration operation and a read operation in response to a ZQ calibration enable signal and a read enable signal. The nonvolatile memory device includes a duty ratio control block suitable for receiving the read enable signal, performing a duty correction operation and setting a duty ratio, in a ZQ calibration operation period, and receiving the read enable signal and outputting a duty-corrected clock based on the set duty ratio, in a read operation period; a clock generation block suitable for generating an internal clock signal in response to the duty-corrected clock; and a data output block suitable for outputting data outputted from an internal memory cell region, in synchronization with the internal clock signal.



SEMICONDUCTOR MEMORY SYSTEM, SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE

Thu, 23 Feb 2017 08:00:00 EST

A semiconductor device of the inventive concept includes a timing circuit configured to receive a first timing signal of a first pulse width from an external device and output a second timing signal having a pulse width which is gradually being reduced from a second pulse width longer than the pulse width of the first timing signal, and a data input/output circuit receiving the second timing signal and outputting data to the external device in synchronization with the second timing signal.



SYSTEMS AND METHODS FOR ACOUSTIC WAVE ENABLED DATA STORAGE

Thu, 23 Feb 2017 08:00:00 EST

The present disclosure provides systems and methods for storing, reading, and writing data using particle-based acoustic wave driven shift registers. The shift registers may physically shift particles along rows and/or columns of wells through the interactions of two parallel surfaces. A transducer may generate an acoustic wave to displace one or more of the two parallel surfaces. The particles may be transferred to and/or otherwise constrained by a buffer surface during at least a portion of the acoustic wave, such that the particles may be shifted during one or more cycles of the acoustic wave. In various embodiments, the amplitude of the acoustic wave may correspond to the spacing distance between each of the wells. The wells may be physical and/or potential wells.



SEMICONDUCTOR MEMORY DEVICE WITH INPUT/OUTPUT LINE

Thu, 23 Feb 2017 08:00:00 EST

Various embodiments relate to a semiconductor device. The semiconductor device may include a plurality of mats configured to input and output the data of memory cells through a plurality of mat input/output lines. The semiconductor device may include a plurality of input/output lines coupled to the plurality of mat input/output lines and configured to input and output data. The semiconductor device may include mat control units disposed between the plurality of mats and configured to control the operations of the mats. The plurality of mat input/output lines may be grouped into a plurality of data line groups having the same characteristic, and some of the plurality of data line groups may be disposed to overlap with the mat control units.



SEMICONDUCTOR MEMORY DEVICE, METHOD FOR DESIGNING SEMICONDUCTOR MEMORY DEVICE, AND RECORDING MEDIUM HAVING DESIGNING METHOD RECORDED THEREIN

Thu, 23 Feb 2017 08:00:00 EST

According to one embodiment, a semiconductor memory device includes a core section, a corner area adjacent section, a first circuit block and a second circuit block, and multiple wiring layers. The corner area adjacent section is arranged adjacently to a corner area positioned in a corner of the core section adjacently to the sense amplifier and the row decoder. The multiple wiring layers are provided in each of the first circuit block and the second circuit block, wherein a first wire in one of the multiple wiring layers in the first circuit block is arranged parallel to a second wire included in a wiring layer in the second circuit block which is the same as the wiring layer of the first wire.



ELECTRONIC COMPARISON SYSTEMS

Thu, 16 Feb 2017 08:00:00 EST

An electronic comparison system includes input stages that successively provide bits of code words. One-shots connected to respective stages successively provide a first bit value until receiving a bit having a non-preferred value concurrently with an enable signal, and then provide a second, different bit value. An enable circuit provides the enable signal if at least one of the one-shots is providing the first bit value. A neural network system includes a crossbar with row and column electrodes and resistive memory elements at their intersections. A writing circuit stores weights in the elements. A signal source applies signals to the row electrodes. Comparators compare signals on the column electrodes to corresponding references using domain-wall neurons and store bit values in CMOS latches by comparison with a threshold.



PROTON RESISTIVE MEMORY DEVICES AND METHODS

Thu, 16 Feb 2017 08:00:00 EST

Disclosed herein is a memory device operating based on proton conduction between a source electrode and a drain electrode through a proton-conducting layer. As the memory device operates, protons from the source migrate through the proton-conducting layer and into the drain electrode. The memory device exhibits memory, in the form of changing net conductivity, based on the amount of protons conducted from source to drain. The memory device can be reset by regenerating the source electrode (e.g., through electrical or chemical action). The memory device can be incorporated into an integrated circuit as a memory element. Related methods of using the memory device are also disclosed.



Three-Dimensional One-Time-Programmable Memory Comprising Off-Die Address/Data-Translator

Thu, 16 Feb 2017 08:00:00 EST

The present invention discloses a three-dimensional one-time-programmable memory (3D-OTP) comprising an off-die address/data-translator (A/D-translator). It comprises at least a 3D-array die and at least a peripheral-circuit die. At least an A/D-translator of the 3D-OTP arrays is located on the peripheral-circuit die instead of the 3D-array die. The A/D-translator converts at least an address and/or data between logic and physical spaces.



One-Time Programmable Device with Integrated Heat Sink

Thu, 16 Feb 2017 08:00:00 EST

Junction diodes fabricated in standard CMOS logic processes can be used as program selectors with at least one heat sink or heater to assist programming for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The heat sink can be at least one thin oxide area, extended OTP element area, or other conductors coupled to the OTP element to assist programming. A heater can be at least one high resistance area such as an unsilicided polysilicon, unsilicided active region, contact, via, or combined in serial, or interconnect to generate heat to assist programming. The OTP device has at least one OTP element coupled to at least one diode in a memory cell. The diode can be constructed by P+ and N+ active regions in a CMOS N well, or on an isolated active region as the P and N terminals of the diode. The isolation between P+ and the N+ active regions of the diode in a cell or between cells can be provided by dummy MOS gate, SBL, or STI/LOCOS isolations. The OTP element can be polysilicon, silicided polysilicon, silicide, polymetal, metal, metal alloy, local interconnect, metal-0, thermally isolated active region, CMOS gate, or combination thereof.



NONVOLATILE SEMICONDUCTOR MEMORY

Thu, 16 Feb 2017 08:00:00 EST

A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected wordline, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.



Low Read Data Storage Management

Thu, 16 Feb 2017 08:00:00 EST

Systems and methods disclosed herein are used to efficiently manage low read data. In one aspect, a method includes, in response to detecting occurrence of a first event (e.g., PFail), writing low read data to non-volatile memory of a storage device with a fast SLC programming mode, distinct from a default SLC programming mode. Writing the low read data with the fast SLC programming mode: (i) includes using one or more memory programming parameters distinct from a default set of memory programming parameters used for writing data with the default SLC programming mode and (ii) takes less time per predefined unit of data than writing data with the default SLC programming mode. The method also includes: in response to detecting occurrence of a second event (e.g., host write command), writing data corresponding to the second event with the default SLC programming mode using the default set of memory programming parameters.



NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND ERASE METHOD THEREOF

Thu, 16 Feb 2017 08:00:00 EST

Provided is an erase method for a non-volatile semiconductor memory device to compensate for the change in property of a memory cell, in proportion to the number of data rewrites to the memory cell. The erase method has an erase step to erase charges of a charge accumulation layer by applying an erase voltage to a channel region of a selected memory cell, and a soft-programming step to perform soft-programming to the charges in the accumulation layer by virtue of applying a soft-programming voltage which is smaller than a programming voltage to program the memory cell. The erase voltage is increased step by step when it is applied repeatedly. The soft-programming voltage is decreased step by step when it is applied repeatedly.



Method for Reading Data Stored in a Flash Memory According to a Threshold Voltage Distribution and Memory Controller and System Thereof

Thu, 16 Feb 2017 08:00:00 EST

A method for reading data stored in a flash memory is disclosed. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution.



SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SEMICONDUCTOR DEVICE

Thu, 16 Feb 2017 08:00:00 EST

A semiconductor device includes a memory array having a plurality of complementary cells, each including a first memory element and a second memory element, for holding binary data depending on a difference of threshold voltage therebetween, and a control circuit for initializing the complementary cells. The control circuit performs a first initialization control of reducing the threshold voltage of both the first memory element and the second memory element of the complementary cell and changing the threshold voltage of at least one of the first memory element and the second memory element at an intermediate level lower than a first writing level and higher than an initialization level, a first writing control of changing the threshold voltage of one of the first memory element and the second memory element of the complementary cell at the first writing level, and a second initialization control of changing the threshold voltage of both the first memory element and the second memory element of the complementary cell at the initialization level.



MEMORY DEVICES HAVING SOURCE LINES DIRECTLY COUPLED TO BODY REGIONS AND METHODS

Thu, 16 Feb 2017 08:00:00 EST

Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing.



APPARATUSES AND METHODS FOR EFFICIENT WRITE IN A CROSS-POINT ARRAY

Thu, 16 Feb 2017 08:00:00 EST

A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing sufficient currents and voltages for WRITE and/or READ operations in the memory array. When the de-selection path is used for providing the operation function, highly efficient cross-point implementations can be achieved. The operation function may be accomplished by circuit manipulation of a de-selection supply and/or de-selection elements.



MEMORY DEVICE WITH REDUCED NEIGHBOR MEMORY CELL DISTURBANCE

Thu, 16 Feb 2017 08:00:00 EST

In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes a memory cell, digit line driver, access line driver, clamping element, and control circuit. The memory cell and clamping element can be both coupled to a digit line. The control circuit can be configured to cause the clamping element to clamp the voltage of the digit line for a period of time while the digit line driver is caused to bias the digit line at a voltage level sufficient to enable selection of the memory cell. In addition, the control circuit can be configured to cause the access line driver to bias an access line coupled to memory cell when the voltage of the digit line is at the voltage level sufficient to enable selection of the memory cell.



METHOD, SYSTEM AND DEVICE FOR NON-VOLATILE MEMORY DEVICE OPERATION

Thu, 16 Feb 2017 08:00:00 EST

Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a non-volatile memory device may be placed in any one of multiple memory states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device. For example, a write operation may apply a programming signal across terminals of non-volatile memory device having a particular current and a particular voltage for placing the non-volatile memory device in a particular memory state.



METHOD, SYSTEM AND DEVICE FOR NON-VOLATILE MEMORY DEVICE OPERATION

Thu, 16 Feb 2017 08:00:00 EST

Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a non-volatile memory device may be placed in any one of multiple memory states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device. For example, a write operation may apply a programming signal across terminals of non-volatile memory device having a particular current and a particular voltage for placing the non-volatile memory device in a particular memory state.



CORRELATING PHYSICAL PAGE ADDRESSES FOR SOFT DECISION DECODING

Thu, 16 Feb 2017 08:00:00 EST

A storage device may include a processor and a memory device including a multilevel memory cell. The processor may correlate a first physical page address and a second physical page address, each address being associated with the multilevel memory cell. The processor also may apply a first read operation to the memory cell to determine a value of a first bit associated with the first physical page address. The processor additionally may apply at least a second read operation to the multilevel memory cell to determine a value of a second bit associated with the second physical page address. The processor may determine, based at least in part on the value of the first bit and the value of the second bit, a soft decision value associated with the second bit. The processor may verify the value of the second bit based at least in part on the soft decision value.



MEMORY DEVICE AND A METHOD OF OPERATING THE SAME

Thu, 16 Feb 2017 08:00:00 EST

A method of operating a memory device includes writing cell data having one of at least three states to a memory cell; amplifying a voltage level of a bit line connected to the memory cell; determining that the cell data is in a first state when the voltage level of the bit line sensed at a sensing point is equal to or greater than a first reference voltage; determining that the cell data is in a second state when the voltage level of the bit line sensed at the sensing point is equal to or less than a second reference voltage which has a lower voltage level than the first reference voltage; and determining that the cell data is in a third state when the cell data is not in the first or second states.



DESIGN STRUCTURE FOR REDUCING PRE-CHARGE VOLTAGE FOR STATIC RANDOM-ACCESS MEMORY ARRAYS

Thu, 16 Feb 2017 08:00:00 EST

A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.



DESIGN STRUCTURE FOR REDUCING PRE-CHARGE VOLTAGE FOR STATIC RANDOM-ACCESS MEMORY ARRAYS

Thu, 16 Feb 2017 08:00:00 EST

A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.



SEMICONDUCTOR MEMORY DEVICE MANAGING FLEXIBLE REFRESH SKIP AREA

Thu, 16 Feb 2017 08:00:00 EST

A semiconductor memory device having a flexible refresh skip area includes a memory cell array including a plurality of rows to store data, a row decoder connected to the memory cell array, a refresh area storage unit to store a beginning address and an end address of a memory area that is to be refreshed in which the memory area that is to be refreshed does not include a refresh skip area having a size is selectively and/or adaptively changed, and a refresh control circuit connected to the row decoder and the refresh area storage unit. The refresh control circuit controls a refresh operation for the area that is to be refreshed and not for the refresh skip area.