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MEMORY MODULES

Thu, 27 Oct 2016 08:00:00 EDT

A memory module includes a command/address (CA) register, memory devices, and a module resistor unit mounted on a circuit board. The centrally disposed CA register drive the memory devices one or more internal CA signal(s) to arrangements of memory devices using multiple CA transmission lines, wherein the multiple internal CA transmission lines are commonly terminated in the module resistor unit.



SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

Thu, 27 Oct 2016 08:00:00 EDT

A semiconductor memory device includes a memory cell array having a first group of main blocks, a second group of main blocks and redundancy blocks replacing the first group of main blocks or the second group of main blocks, a repair logic suitable for enabling a replacement signal when one or more of the second group of main blocks are defective, a control logic suitable for generating an address for the second group of main blocks in response to a dedicated command for access to one or more of the second group of main blocks, and an address decoder suitable for selecting one or more of the redundancy blocks based on the address for the second group of main blocks when the replacement signal is enabled.



MEMORY DEVICE AND READING METHOD THEREOF

Thu, 27 Oct 2016 08:00:00 EDT

A memory device includes: a plurality of conductive stacked structures including at least a string select line, a plurality of word lines and at least a ground select line; a plurality of memory cells formed in the conductive stacked structures; a plurality of bit lines, formed on the conductive stacked structures; and at least an odd common source line and at least an even common source line, formed on the conductive stacked structures. The odd common source line is coupled to a plurality of odd bit lines of the bit lines. The even common source line is coupled to a plurality of even bit lines of the bit lines.



SEMICONDUCTOR MEMORY DEVICE

Thu, 27 Oct 2016 08:00:00 EDT

A semiconductor memory device has a memory block including memory strings with first and second selection transistors at opposite ends of the memory strings. A bit line is connected to the first selection transistor of each memory string and a sense amplifier is connected to the bit line. The memory block includes word lines connected to each memory cell transistor in the memory strings. The memory device also includes a controller to control an erase operation that includes applying an erase voltage to the word lines, addressing a first memory string by applying a selection voltage to a gate electrode of first and second selection transistors of the first memory string, then applying an erase verify voltage to the word lines and using the sense amplifier to read data of memory cell transistors in the first memory string, then addressing a second memory string without first discharging the word lines.



ADAPTIVE BLOCK PARAMETERS

Thu, 27 Oct 2016 08:00:00 EDT

Data programmed in a block using a first set of programming parameters is read and a number of memory cells having threshold voltages in an intermediate threshold voltage range that is between ranges assigned to logic states is determined. The number is compared to a threshold number and if the number exceeds the threshold number then subsequent programming uses a second set of programming parameters.



COMMON SOURCE ARCHITECTURE FOR SPLIT GATE MEMORY

Thu, 27 Oct 2016 08:00:00 EDT

A memory system has an array of split gate non-volatile NVM cells that are in program sectors and the program sectors make up one or more erase sectors. The control gate of cells in a program sector are physically connected. A program/erase circuit programs a selected program sector by applying a programming signal to the control gates of the split gate memory cells of the selected program sector while applying a non-programming signal to the control gates of program sectors not selected for programming, that erases an erase sector comprising a plurality of the program sectors by contemporaneously applying an erase voltage to the control gates of the split gate NVM cells of the erase sector, wherein during the applying the programming signal, the program/erase circuit applies a source voltage to the sources of each of the split gate NVM cells of the erase sector.



Method for determining an optimal voltage pulse for programming a flash memory cell

Thu, 27 Oct 2016 08:00:00 EDT

A method for determining an optimal voltage pulse for programming a flash memory cell, the optimal voltage pulse being defined by a voltage ramp from a non-zero initial voltage level during a programming duration, wherein the method takes into account a set of parameters including a programming window target value and a drain current target value of the memory cell.



NATURAL THRESHOLD VOLTAGE COMPACTION WITH DUAL PULSE PROGRAM FOR NON-VOLATILE MEMORY

Thu, 27 Oct 2016 08:00:00 EDT

A control circuit, in communication with non-volatile memory cells, is configured to distinguish and classify the memory cells into the different subsets of memory cells based on programming performance. Based on the classifying, the control circuit applies different programming signals to different subsets of the memory cells being programmed to a common data state.



Non-Volatile Memory With Two Phased Programming

Thu, 27 Oct 2016 08:00:00 EDT

Programming non-volatile memory includes applying a series of programming pulses to the memory cells as part of a coarse/fine programming process. Between programming pulses, memory cells in the coarse phase are verified for a coarse phase verify level for a target data state and memory cells in the fine phase are verified for a fine phase verify level for the target data state, both in response to a single reference voltage applied on a common word line. For a memory cell in the coarse phase that has been verified to have reached the coarse phase verify level, the memory cell will be temporarily inhibited from programming for a next programming pulse and switched to the fine phase. For a memory cell in the fine phase that has been verified to have reached the fine phase verify level, the memory cell will be inhibited from further programming



MEMORY SYSTEM AND OPERATING METHOD THEREOF

Thu, 27 Oct 2016 08:00:00 EDT

A memory system includes: a memory device comprising at least a page; and a controller suitable for setting a seed offset according to a size of a restricted region in the page, randomizing data using the seed offset at each cycle, and storing the randomized data in the page.



HIGH PERFORMANCE DIGITAL TO ANALOG CONVERTER

Thu, 27 Oct 2016 08:00:00 EDT

A digital-to-analog converter (DAC) may include a conversion block providing a first analog value. The DAC may also include an amplification block for receiving the first analog value and providing a second analog value amplified by an amplification factor. The amplification block may include a first input terminal for receiving the first analog value, a second input terminal, and an output terminal for providing the second analog value. The amplification block may also include a first capacitive element and a second capacitive element. The first and second capacitive elements may determine the amplification factor. The amplification block may further include a control unit for recovering a charge at a first terminal of the second capacitive element, and based thereon, the second analog value.



THREE-DIMENSIONAL NONVOLATILE MEMORY AND RELATED READ METHOD DESIGNED TO REDUCE READ DISTURBANCE

Thu, 27 Oct 2016 08:00:00 EDT

A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.



Dual Function Hybrid Memory Cell

Thu, 27 Oct 2016 08:00:00 EDT

A dual function hybrid memory cell is disclosed. In one aspect, the memory cell includes a substrate, a bottom charge-trapping region formed on the substrate, a top charge-trapping region formed on the bottom charge-trapping region, and a gate layer formed on the top charge trapping region. In another aspect, a method for programming a memory cell having a substrate, a bottom charge-trapping layer, a top charge-trapping layer, and a gate layer is disclosed. The method includes biasing a channel region of the substrate, applying a first voltage differential between the gate layer and the channel region, injecting charge into the bottom charge-trapping layer from the channel region based on the first voltage differential. The method also includes applying a second voltage differential between the gate layer and the channel region and injecting charge from the bottom charge-trapping layer into the top charge-trapping layer based on the second voltage differential.



APPARATUS TO REDUCE RETENTION FAILURE IN COMPLEMENTARY RESISTIVE MEMORY

Thu, 27 Oct 2016 08:00:00 EDT

Described is an apparatus which comprises: a complementary resistive memory bit-cell; and a sense amplifier coupled to the complementary resistive memory bit-cell, wherein the sense amplifier includes: a first output node; and a first transistor which is operable to cause a deterministic output on the first output node.



SYSTEM FOR WRITING DATA IN A MEMORY

Thu, 27 Oct 2016 08:00:00 EDT

A system including: a first memory including several portions of one or more pages each, said memory including first and second ports that can simultaneously access, for reading and writing respectively, two distinct pages of portions of the memory; and a control circuit capable of performing write operations to the pages of the memory, each write operation to a page of the memory requiring a reading step of a former datum on said page via the first port, and including a writing step of a new datum to the page via the second port, taking account of the former datum.



REFERENCE VOLTAGE GENERATION APPARATUSES AND METHODS

Thu, 27 Oct 2016 08:00:00 EDT

A method and apparatuses for generating a reference voltage are disclosed. One example apparatus includes a current source coupled to a first power supply. The current source supplies a first current. A reference memory cell is coupled to the current source at a reference node. The reference memory cell has a select device comprising a chalcogenic semiconductor material. A clamp circuit is coupled between the reference memory cell and a second power supply. The clamp circuit is configured to control a second current such that when the first current and second current are substantially equal, the reference voltage generated at the reference node tracks a threshold voltage of the select device.



ELECTRONIC DEVICE AND METHOD FOR OPERATING ELECTRONIC DEVICE

Thu, 27 Oct 2016 08:00:00 EDT

An electronic device comprising a semiconductor memory unit that may a variable resistance element configured to be changed in its resistance value in response to current flowing through both ends thereof; an information storage unit configured to store switching frequency information corresponding to a switching frequency which minimizes an amplitude of a voltage to be applied to both ends of the variable resistance element to change the resistance value of the variable resistance element and switching amplitude information corresponding to a minimum amplitude; and a driving unit configured to generate a driving voltage with the switching frequency and the minimum amplitude in response to the switching frequency information and the switching amplitude information and apply the driving voltage to both ends of the variable resistance element.



Rewritable Multibit Non-Volatile Memory With Soft Decode Optimization

Thu, 27 Oct 2016 08:00:00 EDT

A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by applying a continuous input scanning sense voltage that spans a range of read compare points. Full sequence programming is enabled as is interleaved coding of the user data over all of the data bit sets associated with the storage elements.



PARTIAL/FULL ARRAY/BLOCK ERASE FOR 2D/3D HIERARCHICAL NAND

Thu, 27 Oct 2016 08:00:00 EDT

A novel 2D/3D hierarchical-BL NAND array with at least one plane on independent Psubstrate comprising a plurality of LG groups respectively associated with a plurality of local bit lines (LBLs) laid at a level below a plurality of broken or non-broken global bit lines (GBLs) connected to Page Buffer. Each LG group includes multiple blocks and connects an independent power supply line to each of the plurality of LBLs. Each block including N-bit 2D/3D NAND strings each with S cells connected in series and terminated by two string-select devices and coupled to a common source line. In particular, random-size partial-block WLs are selected from each block of randomly selected LG groups of one plane of the 2D/3D NAND array for erase at the same time with border WLs being optionally preread and program into another plane of the 2D/3D NAND array or optionally saved off-chip and wrote back for data security.



Circuits and Methods for Performance Optimization of SRAM Memory

Thu, 27 Oct 2016 08:00:00 EDT

In described examples, a memory controller circuit controls accesses to an SRAM circuit. Precharge mode control circuitry outputs: a burst mode enable signal to the SRAM circuit indicating that a series of SRAM cells along a selected row of SRAM cells will be accessed; a precharge first mode signal to the SRAM circuit indicating that a first access along the selected row will occur; and a precharge last mode signal to the SRAM circuit indicating that a last access along the selected row will occur. The SRAM circuit includes an array of SRAM cells arranged in rows and columns to store data. Each SRAM cell is coupled to: a corresponding word line along a row of SRAM cells; and a corresponding pair of complementary bit lines.



INTEGRATED CIRCUIT CHIP HAVING TWO TYPES OF MEMORY CELLS

Thu, 27 Oct 2016 08:00:00 EDT

An integrated circuit chip includes a first type memory cell and a second type memory cell. The first type memory cell includes a first reference line landing pad and a first word line landing pad. The first reference line landing pad of the first type memory cell and the first word line landing pad of the first type memory cell are aligned along a first direction. The second type memory cell includes a first reference line segment extending along the first direction and a first word line landing pad. The first word line landing pad of the second type memory cell and the first reference line segment of the second type memory cell are spaced apart along a second direction different from the first direction.



SEMICONDUCTOR MEMORY DEVICE

Thu, 27 Oct 2016 08:00:00 EDT

A semiconductor memory device may include: a plurality of banks suitable for performing an all bank refresh operation or single bank refresh operation; an address output control unit suitable for generating a plurality of output control signals in response to a single bank refresh pulse signal; an address latch unit suitable for outputting a target row address of a bank corresponding to an activated output control signal; and an address output unit suitable for outputting a row address adjacent to the target row address to a selected bank.



INTEGRATED CIRCUIT

Thu, 27 Oct 2016 08:00:00 EDT

An integrated circuit device comprises a first data processing element having a first data interface configured to synchronously communicate data according to a first clock signal at a first clock speed, and a second data interface configured to synchronously communicate data at a second clock speed lower than the first clock speed; and a second data processing element configured to operate in response to a second clock signal at the second clock speed and to synchronously communicate data with the first data processing element via the second data interface according to the second clock speed; the first data processing element being configured to derive, from a source clock signal, the first clock signal and the second clock signal; and the first data processing element and the second data processing element each comprising a clock signal interface by which the second clock signal is provided by the first data processing element to the second data processing element.



FAST PROGRAMMING OF MAGNETIC RANDOM ACCESS MEMORY (MRAM)

Thu, 27 Oct 2016 08:00:00 EDT

A method of programming an MTJ includes selecting an MTJ that is coupled to an access transistor at the drain of the access transistor. The gate of the access transistor is coupled to a selected word line (WL), the selected WL being substantially at a first voltage, Vdd; whereas the WLs that are not coupled to the MTJ are left to float. A second voltage, Vx, is applied to the unselected bit lines (BLs) and further applied to a source line (SL), the SL being coupled to the source of the access transistor. A third voltage, Vdd or 0 Volts, is applied to a selected BL, the selected BL being coupled the MTJ. The first voltage is applied to a SL, the SL being coupled to the source of the access transistor thereby causing the WL to boot above the first voltage.



A Memory Device, Comprising at Least One Element and Associated Method Spintronics

Thu, 27 Oct 2016 08:00:00 EDT

A storage device, comprising at least one spintronic element suitable for representing a state among at least n states associated with the spintronic element, n>1, characterized in that each of the n states is associated with at least one characteristic of a group of magnetic skyrmions in the spintronic element, and in that said characteristic associated with a state n ∘i is different from said characteristic associated with a state n ∘j when the states n ∘i and n ∘j are two different states among the n states.



BITCELL STATE RETENTION

Thu, 27 Oct 2016 08:00:00 EDT

In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.



APPARATUSES AND METHODS FOR PROVIDING ACTIVE AND INACTIVE CLOCK SIGNALS TO A COMMAND PATH CIRCUIT

Thu, 27 Oct 2016 08:00:00 EDT

Apparatuses and methods for providing active and inactive clock signals to a command path circuit are described. An example method includes providing an active clock signal to a command path for a first portion of a command cycle for a command of back-to-back commands. The command path decodes the command and provides an output command signal responsive to the clock signal. The method further includes providing an inactive clock signal to the command path for a second portion of the command cycle for the command of the back-to-back commands.



METHODS AND APPARATUSES FOR COMMAND SHIFTER REDUCTION

Thu, 27 Oct 2016 08:00:00 EDT

Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.



MEMORY ELEMENTS AND CROSS POINT SWITCHES AND ARRAYS OF SAME USING NONVOLATILE NANOTUBE BLOCKS

Thu, 27 Oct 2016 08:00:00 EDT

Under one aspect, a covered nanotube switch includes: (a) a nanotube element including an unaligned plurality of nanotubes, the nanotube element having a top surface, a bottom surface, and side surfaces; (b) first and second terminals in contact with the nanotube element, wherein the first terminal is disposed on and substantially covers the entire top surface of the nanotube element, and wherein the second terminal contacts at least a portion of the bottom surface of the nanotube element; and (c) control circuitry capable of applying electrical stimulus to the first and second terminals. The nanotube element can switch between a plurality of electronic states in response to a corresponding plurality of electrical stimuli applied by the control circuitry to the first and second terminals. For each different electronic state, the nanotube element provides an electrical pathway of different resistance between the first and second terminals.



MEMORY STORAGE DEVICE HAVING CLOCK AND DATA RECOVERY CIRCUIT

Thu, 20 Oct 2016 08:00:00 EDT

A clock and data recovery circuit module, a memory storage device and a phase lock method are provided. The module includes sampling circuits, a first logic circuit module, a delay circuit module, a second logic circuit module, a frequency adjustment circuit and a clock control circuit. The sampling circuits sample a data signal according to reference clocks. The first logic circuit module performs a first logic operation according to a sampling result. The delay circuit module delays a result of the first logic operation. The second logic circuit module performs a second logic operation according to said result and the delayed first logic result. The frequency adjustment circuit outputs a frequency adjustment signal according to a result of the second logic operation, and the clock control circuit performs a phase locking accordingly. Therefore, a circuit complexity of the clock and data recovery circuit module may be reduced.



THREE DIMENSIONAL NAND FLASH WITH SELF-ALIGNED SELECT GATE

Thu, 20 Oct 2016 08:00:00 EDT

An integrated circuit may include a pillar of semiconductor material, a field effect transistor having a channel that is formed in the pillar of semiconductor material, and two or more memory cells, stacked vertically on top of the field effect transistor, and having channels that are formed in the pillar semiconductor of material.



REPAIR OF MEMORY DEVICES USING VOLATILE AND NON-VOLATILE MEMORY

Thu, 20 Oct 2016 08:00:00 EDT

Apparatus and methods for hybrid post package repair are disclosed. One such apparatus may include a package including memory cells and volatile memory. The volatile memory may be configured to store defective address data corresponding to a first portion of the memory cells that are deemed defective post-packaging. The apparatus may also include a decoder configured to select a second portion of the memory cells instead of the first portion of the memory cells when received current address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory. The apparatus may also include non-volatile memory in the package. The apparatus may also include a mapping logic circuit in the package. The mapping logic circuit may be configured to program the replacement address data to the non-volatile memory subsequent to the defective address data being stored to the volatile memory.



METHOD AND DEVICE FOR PROGRAMMING MEMORY CELLS OF THE ONE-TIME-PROGRAMMABLE TYPE

Thu, 20 Oct 2016 08:00:00 EDT

A memory cell of the one-time-programmable type is programmed by application of a programming voltage having a value sufficient to obtain a breakdown of a dielectric of a capacitor within the cell. A programming circuit generates the programming voltage as a variable voltage that varies as a function of a temperature (T) of the cell. In particular, the programming voltage varies based on a variation law decreasing as a function of the temperature.



SEMICONDUCTOR DEVICE AND METHOD OF DRIVING THE SAME

Thu, 20 Oct 2016 08:00:00 EDT

A semiconductor device may include: a control block suitable for generating a boot-up select signal in response to a boot-up mode signal and a fuse select signal; and a fuse block suitable for performing a program operation of rupturing one or more first fuse cells among a plurality of fuse cells in response to the fuse select signal, and performing a boot-up operation on a partial fuse region including the one or more first fuse cells in response to the boot-up select signal.



SEMICONDUCTOR MEMORY DEVICE

Thu, 20 Oct 2016 08:00:00 EDT

According to one embodiment, a semiconductor memory device includes: first and second memory cells; first and second word lines coupled to the first and second memory cells, respectively. When data is read from the first memory cell, first and second voltages are applied to the first word line. A voltage of the second word line varies continuously by a first potential difference with time while the first voltage is applied to the first word line, and the voltage of the first word line varies continuously by a second potential difference with time while the second voltage is applied to the first word line.



SONOS Byte-Erasable EEPROM

Thu, 20 Oct 2016 08:00:00 EDT

A SONOS byte-erasable EEPROM is disclosed. In one aspect, an apparatus includes a plurality of SONOS memory cells forming an EEPROM memory array. The apparatus also includes a controller that generates bias voltages to program and erase the memory cells. The controller performs a refresh operation when programming selected memory cells to reduce write-disturb on unselected memory cells to prevent data loss.



METHOD AND APPARATUS FOR IMPROVING DATA RETENTION AND READ-PERFORMANCE OF A NON-VOLATILE MEMORY DEVICE

Thu, 20 Oct 2016 08:00:00 EDT

Methods and apparatuses are contemplated herein for enhancing the read performance and data retention of nonvolatile memory devices. In an example embodiment, a method is provided for controlling a nonvolatile memory device that includes a matrix of memory cells, wherein each memory cell in the matrix includes a programmable floating gate. The method includes programming a floating gate of a first memory cell of the nonvolatile memory device, and shifting a voltage of the floating gate of the first memory cell of the nonvolatile memory device by creating a coupling effect that impacts the floating gate of the first memory cell. In this regard, the method may include programming one or more nearby memory cells, in which case the coupling effect may comprise a floating gate coupling effect between the first memory cell and the one or more nearby memory cells.



STORAGE DEVICE AND RELIABILITY VERIFICATION METHOD

Thu, 20 Oct 2016 08:00:00 EDT

A method controlling the execution of a reliability verification operation in a storage device including a nonvolatile memory device includes; determining whether a read count for a designated unit within the nonvolatile memory device exceeds a count value limit, and upon determining that the read count exceeds the count value limit, executing the reliability verification operation directed to the designated unit, wherein the count value limit is based on at least one of read count information, page bitmap information and environment information stored in the storage device.



CENTRALIZED VARIABLE RATE SERIALIZER AND DESERIALIZER FOR BAD COLUMN MANAGEMENT

Thu, 20 Oct 2016 08:00:00 EDT

A memory circuit includes an array subdivided into multiple divisions, each connectable to a corresponding set of access circuitry. A serializer/deserializer circuit is connected to a data bus and the access circuitry to convert data between a (word-wise) serial format on the bus and (multi-word) parallel format for the access circuitry. Column redundancy circuitry is connect to the serializer/deserializer circuit to provide defective column information about the array. In converting data from a serial to a parallel format, the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column. In converting data from a parallel to a serial format the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column.



NONVOLATILE MEMORY DEVICES AND METHODS OF OPERATING THE SAME

Thu, 20 Oct 2016 08:00:00 EDT

Methods of operating a nonvolatile memory device include performing erase loops on a memory block using a first voltage, performing program loops on memory cells of the memory block using a second voltage, and increasing the first and second voltages based on program/erase cycle information for the memory cells. The first voltage may include an erase verification voltage and the second voltage may include a program voltage.



SEMICONDUCTOR DEVICE INCLUDING CELL REGION STACKED ON PERIPHERAL REGION AND METHOD OF FABRICATING THE SAME

Thu, 20 Oct 2016 08:00:00 EDT

Provided are semiconductor devices including a peripheral region and a cell region stacked thereon and a method of fabricating the same. The semiconductor device may include a peripheral region including a lower substrate and a peripheral circuit provided thereon and a cell region including an upper substrate and a cell array provided thereon. The cell region may be stacked on the peripheral region. When an operation signal is applied to the cell region from the peripheral region, at least a portion of the peripheral and cell regions may be used as a ground pattern applied with a ground signal, thereby being in an electrical ground state.



MITIGATION OF DATA RETENTION DRIFT BY PROGRMMING NEIGHBORING MEMORY CELLS

Thu, 20 Oct 2016 08:00:00 EDT

A method includes, in a plurality of memory cells that share a common isolation layer and store in the common isolation layer quantities of electrical charge representative of data values, assigning a first group of the memory cells for data storage, and assigning a second group of the memory cells for protecting the electrical charge stored in the first group from retention drift. Data is stored in the memory cells of the first group. Protective quantities of the electrical charge that protect from the retention drift in the memory cells of the first group are stored in the memory cells of the second group.



NONVOLATILE MEMORY DEVICES AND METHODS OF PROGRAMMING AND READING NONVOLATILE MEMORY DEVICES

Thu, 20 Oct 2016 08:00:00 EDT

In a method of programming a nonvolatile memory device, a program operation is performed on a selected memory cell coupled to a selected word line in response to a program command, a negative bias voltage is applied to the selected word line, a verification pass voltage is applied to an unselected word line after the negative bias voltage is applied to the selected word line, and a first program verification voltage, which is higher than the negative bias voltage and lower than a ground voltage, is applied to the selected word line.



Non-volatile memory for high rewrite cycles application

Thu, 20 Oct 2016 08:00:00 EDT

A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.



MEMORY CIRCUITS USING A BLOCKING STATE

Thu, 20 Oct 2016 08:00:00 EDT

A memory circuit with blocking states. In one embodiment, the memory circuit includes a two non-volatile transistors connected in series. The input state of the memory cell and the stored state of the memory cell are configured to be a plurality of states including a zero state, a one state, a no care state, and an input blocking state. When the input state of the memory cell is the blocking state, the memory cell is configured to be in a blocking mode unless the stored state of the memory cell is the no care state. When the stored state of the memory cell is the blocking state, the memory cell is configured to be in the blocking mode unless the input state of the memory cell is the no care state.



METHOD FOR PROGRAMMING MEMORY DEVICE AND ASSOCIATED MEMORY DEVICE

Thu, 20 Oct 2016 08:00:00 EDT

A method for programming a memory device comprises the following steps: performing an interleaving programming, including: programming a first memory cell during a first time interval and correspondingly verifying the first memory cell during a second time interval; programming a second memory cell during a third time interval and correspondingly verifying the second memory cell during a fourth time interval between the first and second time intervals; and inserting at least one dummy cycle between the first and second time intervals to ensure that a resistance change per unit of time of the first memory cell is less than a threshold.



APPARATUSES, MEMORIES, AND METHODS FOR ADDRESS DECODING AND SELECTING AN ACCESS LINE

Thu, 20 Oct 2016 08:00:00 EDT

Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. The first select line is configured to provide a first voltage, the second select line is configured to provide a second voltage, and the polarity line is configured to provide a polarity signal. The address decoder circuit is configured to receive address information and further configured to couple the access line to the first select line responsive to the address information having a combination of logic levels and the polarity signal having a first logic level and further configured to couple the access line to the second select line responsive to the address information having the combination of logic levels and the polarity signal having a second logic level.



Method of Operating Incrementally Programmable Non-Volatile Memory

Thu, 20 Oct 2016 08:00:00 EDT

An array of programmable non-volatile devices, such as a nominal OTP cell, is operated such that a Vt representing a particular binary logic state is changed over time. This allows for re-programming and emulating a few times or multi-time programmable device.



Method of Operating Incrementally Programmable Non-Volatile Memory

Thu, 20 Oct 2016 08:00:00 EDT

An array of programmable non-volatile devices, such as a nominal OTP cell, is operated such that a Vt representing a particular binary logic state is changed over time. This allows for re-programming and emulating a few times or multi-time programmable device.



PROGRAMMING MEMORIES WITH MULTI-LEVEL PASS SIGNAL

Thu, 20 Oct 2016 08:00:00 EDT

Methods of operating a memory include applying a multi-step pass voltage to a plurality of memory cells selected for a programming operation, applying a programming pulse to the plurality of memory cells selected for the programming operation after applying a voltage level of a particular step of the multi-step pass voltage to the plurality of memory cells selected for the programming operation, applying a particular voltage level to any data lines coupled to a first subset of memory cells of the plurality of memory cells selected for the programming operation prior to applying a voltage level of a certain step of the multi-step pass voltage, and applying the particular voltage level to any data lines coupled to a second subset of memory cells of the plurality of memory cells selected for the programming operation only after applying the voltage level of the certain step of the multi-step pass voltage.