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SOFT POST PACKAGE REPAIR OF MEMORY DEVICES

Thu, 06 Apr 2017 08:00:00 EDT

Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the detective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus.



SEMICONDUCTOR DEVICES

Thu, 06 Apr 2017 08:00:00 EDT

A first data input circuit receives test data from a first pad to generate first input control data for generating cell input data stored in a memory cell array during a first operation period. A first data output circuit receives first output control data generated from cell output data outputted from the memory cell array to output the first output control data to an internal node coupled to a second pad during a second operation period.



Fully Depleted Silicon On Insulator Flash Memory Design

Thu, 06 Apr 2017 08:00:00 EDT

The present invention relates to a flash memory system wherein one or more circuit blocks utilize fully depleted silicon-on-insulator transistor design to minimize leakage



DEVICES AND METHODS TO PROGRAM A MEMORY CELL

Thu, 06 Apr 2017 08:00:00 EDT

Subject matter disclosed herein relates to memory devices and, more particularly, to programming a memory cell.



MEMORY UNIT AND METHOD OF OPERATING A MEMORY UNIT SECTOR

Thu, 06 Apr 2017 08:00:00 EDT

Disclosed is a memory unit that includes a sector of memory cells. The sector includes a first memory cell configured to selectively take on a state representation of a first plurality of state representations and a second memory cell configured to selectively take on at least one of a second plurality of state representations. The second plurality of state representations is different than the first plurality of state representations. An apparatus includes a processing unit and a memory unit coupled to the processing unit. The memory unit includes a sector of memory cells. Further disclosed are a method of operating a memory unit sector and a method of controlling a sector of a memory unit.



METHODS AND APPARATUSES FOR LOW POWER STATIC RANDOM ACCESS MEMORY (SRAM) CELL AND ARRAY ARCHITECTURE FOR ABOVE, NEAR AND BELOW THRESHOLD VOLTAGE OPERATION

Thu, 06 Apr 2017 08:00:00 EDT

Circuits and methods for implementing a 10-T SRAM cell with independent read and write data ports, no data line precharge between cycles, and single-ended read and write access into the SRAM cell. The single ended nature of the cell and the elimination of a precharge period between accesses on both read and write ports saves considerable active power. This, in conjunction with the elimination of traditional column decode such that only the addressed SRAM cells are connected to their read or write data lines saves additional power while retaining reasonably high speeds, very good yield and enables the SRAM to operate in the voltage range that are near and below the threshold voltages of the MOSFET transistors.



REFRESH TIMER SYNCHRONIZATION BETWEEN MEMORY CONTROLLER AND MEMORY

Thu, 06 Apr 2017 08:00:00 EDT

A memory controller is configured to communicate to a DRAM an indication of when a most-recent memory-controller-triggered refresh cycle occurred prior to a transition to a self-refresh mode of operation in which the DRAM self-triggers its refresh cycles.



SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING PEAK CURRENT WITH RESPECT TO EXTERNAL POWER IN MULTI-MEMORY DIE STRUCTURES

Thu, 06 Apr 2017 08:00:00 EDT

A semiconductor memory device is disclosed that can differentially control a driving ability and current consumption of the charge pump circuit according to operation state information of other memory die. The semiconductor memory device includes a plurality of charge pump circuits installed on a plurality of memory dies, and a pump managing circuit installed on each of the memory dies to control the charge pump circuits and receive operation state information with respect to other memory die to generate control signals for controlling the charge pump circuits on its own memory die.



LOW STANDBY POWER WITH FAST TURN ON FOR NON-VOLATILE MEMORY DEVICES

Thu, 06 Apr 2017 08:00:00 EDT

Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.