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PHASE CHANGE MEMORY

Thu, 25 Aug 2016 08:00:00 EDT

A phase change memory includes a substrate, a number of row electrode leads located on the substrate, and a number of column electrode leads located on the substrate and intersected with the number of row electrode leads to define a number of sections. A number of phase change memory units is received in the number of sections and includes a first circuit and a second circuit. The first circuit includes a carbon nanotube wire electrically connected between the first row electrode lead and first column electrode lead, the carbon nanotube wire includes a bending portion. The second circuit includes the first row electrode lead, the carbon nanotube wire, a phase change layer, and the second row electrode lead electrically connected in series, wherein the phase change layer is electrically connected between the bending portion of the carbon nanotube wire and the second row electrode.



MEMORY SYSTEM, MEMORY CONTROLLER AND MEMORY CONTROL METHOD

Thu, 25 Aug 2016 08:00:00 EDT

According to one embodiment, a memory system includes a nonvolatile memory, a memory interface, a storage unit which stores defective memory cell information, and a storage location control unit which creates second data of a second data length longer than a first data length based on an area at a write destination of first data of the first data length, causes the memory interface to write a plurality of second data to the nonvolatile memory, causes the memory interface to read the second data corresponding to the first data instructed to be read from the nonvolatile memory, and restores the first data based on the read second data and the defective memory cell information.



ONE TIME PROGRAMMABLE NON-VOLATILE MEMORY AND READ SENSING METHOD THEREOF

Thu, 25 Aug 2016 08:00:00 EDT

A read sensing method for an OTP non-volatile memory is provided. The memory array is connected with plural bit lines. The read sensing method includes following steps. Firstly, the plural bit lines are precharged to a precharge voltage. Then, a selected memory cell of the memory array is determined, wherein the selected memory cell is connected with a first bit line of the plural bit lines. Then, the bit line corresponding to the selected memory cell is connected with the data line, and the data line is discharged to a reset voltage. After a cell current from the selected memory cell is received, a voltage level of the data line is gradually changed from the reset voltage. According to a result of comparing a voltage level of the data line with a comparing voltage, an output signal is generated.



SEMICONDUCTOR DEVICE

Thu, 25 Aug 2016 08:00:00 EDT

A memory cell (101) includes a memory transistor (10A) having channel length L1 and channel width W1, and a plurality of select transistors (10B) each electrically being connected in series with the memory transistor and independently having channel length L2 and channel width W2, wherein each of the memory transistor and the plurality of select transistors includes an active layer (7A) formed from a common oxide semiconductor film, the memory transistor is a transistor which is capable of being irreversibly changed from a semiconductor state where drain current Ids depends on gate voltage Vg to a resistor state where drain current Ids does not depend on gate voltage Vg, and channel length L2 is greater than channel length L1.



NONVOLATILE MEMORY DEVICE, STORAGE DEVICE HAVING THE SAME, AND OPERATION AND READ METHODS THEREOF

Thu, 25 Aug 2016 08:00:00 EDT

A method is for operating a nonvolatile memory device, the nonvolatile memory device including at least one string connected to a bit line, the at least one string including a plurality of memory cells connected in series, each of the plurality of memory cells being connected to a respective word line among a plurality of word lines and stacked in a direction perpendicular to a substrate. The method includes applying a word line voltage needed for an operation to a first word line among the word lines, applying a recovery voltage higher than a ground voltage to the first word line after the operation, and then floating the first word line.



STORAGE DEVICES AND METHODS OF OPERATING STORAGE DEVICES

Thu, 25 Aug 2016 08:00:00 EDT

A method of operating a storage device may include receiving a read command and a read address, performing a read operation on selected memory cells corresponding to a selected string selection line and a selected word line based on the read address and performing a reliability verification read on unselected memory cells. Data read by the read operation may be output to an external device, and data read by the reliability verification read may be not output to the external device.



MEMORY CONTROLLER AND OPERATING METHOD THEREOF

Thu, 25 Aug 2016 08:00:00 EDT

An operating method of a memory controller includes: performing a first hard decision read operation based on a read retry table including an index representing a read environment of a semiconductor memory device, wherein the read retry table defines hard read voltage values for a plurality of hard read voltage levels of a multi-level cell; and performing a second hard decision read operation by independently changing each of the hard read voltage levels based on the hard read voltage values of the read retry table when the first hard decision read operation fails.



METHOD AND APPARATUS FOR STRESSING A NON-VOLATILE MEMORY

Thu, 25 Aug 2016 08:00:00 EDT

A method and memory for stressing a plurality of non-volatile memory cells is provided. The method includes entering a memory cell stressing mode and providing one or more erase stress pulses to the plurality of non-volatile memory cells; determining that a threshold voltage of at least a subset of the plurality of non-volatile memory cells has a first relationship that is either greater than or less than a first predetermined voltage; providing one or more program stress pulses to the plurality of memory cells; and determining that the threshold voltage of at least a subset of the plurality of memory cells has a second relationship to a second predetermined voltage that is different than the first relationship.



SEMICONDUCTOR MEMORY DEVICE

Thu, 25 Aug 2016 08:00:00 EDT

A semiconductor memory device includes a first memory block having a first memory cell transistor and a first select transistor, a second memory block having a second memory cell transistor and a second select transistor, a first select gate line that is electrically connected to a gate of the first select transistor, and a second select gate line that is electrically connected to a gate of the second select transistor. During writing of data to a memory cell transistor in the first block, a first voltage is applied to the first select gate line during a first time period, a second voltage is applied to the second select gate line during a second time period after the first time period, and a third voltage lower than the first voltage is applied to the first select gate line during a third time period after the second time period.



NON-VOLATILE MEMORY WITH A VARIABLE POLARITY LINE DECODER

Thu, 25 Aug 2016 08:00:00 EDT

The present disclosure relates to a memory including a memory array with at least two rows of memory cells, a first driver coupled to a control line of the first row of memory cells, and a second driver coupled to a control line of the second row of memory cells. The first driver is made in a first well, the second driver is made in a second well electrically insulated from the first well, and the two rows of memory cells are produced in a memory array well electrically insulated from the first and second wells.



SEMICONDUCTOR MEMORY DEVICE AND PRODUCTION METHOD THEREOF

Thu, 25 Aug 2016 08:00:00 EDT

A semiconductor memory device according to an embodiment comprises a memory cell array including first and second wiring line layers disposed sequentially above memory cells, the first wiring line layer including a first wiring line and a first dummy wiring line, and the second wiring line layer including a second wiring line and a second dummy wiring line, the second wiring line being disposed at the same position in the first direction as the first dummy wiring line, the second dummy wiring line being disposed at the same position in the first direction as the first wiring line, and during an access operation by a control circuit, the first and second wiring lines being electrically connected to at least one of the memory cells, and the first and second dummy wiring lines being fixed at a certain first potential.



AND-TYPE SGVC ARCHITECTURE FOR 3D NAND FLASH

Thu, 25 Aug 2016 08:00:00 EDT

A memory device includes a plurality of strings of memory cells. A plurality of stacks of conductive strips includes first upper strips configured as first string select lines for the strings in the plurality of strings, second upper strips configured as second string select lines for the strings in the plurality of strings, and intermediate strips configured as word lines for the strings in the plurality of strings. The memory device includes control circuitry coupled to the first string select lines and the second string select lines, and configured to select a particular string in the plurality of strings by applying a first turn-on voltage to a first string select line in the first string select lines coupled to the particular string, and a second turn-on voltage to a second string select line in the second string select lines coupled to the particular string.



Semiconductor Memory Device

Thu, 25 Aug 2016 08:00:00 EDT

A semiconductor memory device capable of a high-accuracy data search is provided. Each of the memory cells can hold two bits of information and includes a first cell and a second cell. The semiconductor memory device also includes a match line and a search line pair to transfer search data. The semiconductor memory device further includes a logic operation cell to drive the match line based on comparison results between information held in the first and the second cell and search data transferred by the search line pair and a search line driver to drive the search line pair. In a state with the search line pair precharged to a third voltage between a first voltage and a second voltage, the search line driver drives, according to the search data, one and the other search line included in the search line pair to the first and the second voltage, respectively.



DYNAMIC TAG COMPARE CIRCUITS EMPLOYING P-TYPE FIELD-EFFECT TRANSISTOR (PFET)-DOMINANT EVALUATION CIRCUITS FOR REDUCED EVALUATION TIME, AND RELATED SYSTEMS AND METHODS

Thu, 25 Aug 2016 08:00:00 EDT

Dynamic tag compare circuits employing P-type Field-Effect Transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and thus increased circuit performance, are provided. A dynamic tag compare circuit may be used or provided as part of searchable memory, such as a register file or content-addressable memory (CAM), as non-limiting examples. The dynamic tag compare circuit includes one or more PFET-dominant evaluation circuits comprised of one or more PFETs used as logic to perform a compare logic function. The PFET-dominant evaluation circuits are configured to receive and compare input search data to a tag(s) (e.g., addresses or data) contained in a searchable memory to determine if the input search data is contained in the memory. The PFET-dominant evaluation circuits are configured to control the voltage/value on a dynamic node in the dynamic tag compare circuit based on the evaluation of whether the received input search data is contained in the searchable memory.



THREE DIMENSIONAL RESISTIVE MEMORY ARCHITECTURES

Thu, 25 Aug 2016 08:00:00 EDT

In one example, a three dimensional resistive memory architecture includes adjacent memory tiles with each tile including a multilevel resistive crossbar. array and at least one decoder. The multilevel crossbar array includes layers of row crossbars, layers of column crossbars, and layers of resistive memory elements interposed between cross points of the row crossbars and the column crossbars, in which at least one layer of crossbars extends from a first tile through an adjacent tile and is used to address resistive memory elements in the adjacent tile. The at least one decoder underlies the multilevel resistive crossbar array and includes an address matrix comprising digital lines and analog lines, in which the digital lines select which crossbars are connected to the analog lines.



RESISTIVE SWITCHING MEMORY WITH CELL ACCESS BY ANALOG SIGNAL CONTROLLED TRANSMISSION GATE

Thu, 25 Aug 2016 08:00:00 EDT

In one embodiment, a semiconductor memory device includes a plurality of resistive switching memory cells, where each resistive switching memory cell can include: (i) a programmable impedance element having an anode and a cathode; (ii) a word line pair configured to control access to the programmable impedance element, where the word line pair comprises first and second word lines; (iii) a PMOS transistor having a source coupled to the cathode, a drain coupled to a bit line, and a gate coupled to the first word line; and (iv) an NMOS transistor having a source coupled to the bit line, a drain coupled to the cathode, and a gate coupled to the second word line.



GEOMETRY DEPENDENT VOLTAGE BIASES FOR ASYMMETRIC RESISTIVE MEMORIES

Thu, 25 Aug 2016 08:00:00 EDT

In one example, a system includes a multi-plane memory array with shared crossbars and memory elements accessed through the shared crossbars and support circuitry. The support circuitry includes a bias multiplexer to determine an orientation of a target memory element in the multi-plane memory array and output voltage biases with a polarity based on the orientation of the target memory element. Methods for generating and applying geometry dependent voltage biases are also provided.



APPARATUSES AND METHODS OF READING MEMORY CELLS

Thu, 25 Aug 2016 08:00:00 EDT

A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (VTH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (VTH1) of the memory cell and determining whether the VTH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped VTH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (VTH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the VTH1 and the VTH2.



MEMORY CONTROLLER, NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM

Thu, 25 Aug 2016 08:00:00 EDT

According to one embodiment, a memory system includes a nonvolatile semiconductor memory and a memory controller. The memory controller has a first signal generation section that generates a first signal related with a read voltage used for read operation of the nonvolatile semiconductor memory, a second signal generation section that generates a second signal that specifies the temperature coefficient used for the correction for temperature of the read voltage, and a first interface section that outputs the first signal, the second signal and a read command. The nonvolatile semiconductor memory has a word line, a memory cell array includes memory cells connected to the word line, and a second interface section that receives the first signal, the second signal and the read command.



MEMORY SENSING

Thu, 25 Aug 2016 08:00:00 EDT

Technologies are generally described herein for technologies to sense the threshold voltage for memory cells in one sensing operation. The memory cells may be storage circuits for a flash memory device, such as a multilevel flash memory device. Data may be stored and retrieved in the memory cells of the flash memory without involving the use of hardwired or predetermined thresholds. According to some configurations, the sense time distribution from a set of flash cells (e.g., one row), may be processed to decode the digital state of each memory cell. In some examples, computer-executable instructions may be used to process and decode the digital state of the memory cells.



READ-ASSIST CIRCUITS FOR MEMORY BIT CELLS EMPLOYING A P-TYPE FIELD-EFFECT TRANSISTOR (PFET) READ PORT(S), AND RELATED MEMORY SYSTEMS AND METHODS

Thu, 25 Aug 2016 08:00:00 EDT

Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type FET (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide memory bit cells having PFET read ports, as opposed to NFET read ports, to increase memory read times to the memory bit cells, and thus improve memory read performance. To mitigate or avoid a read disturb condition that could otherwise occur when reading the memory bit cell, read-assist circuits are provided for memory bit cells having PFET read ports.



NEGATIVE SUPPLY RAIL POSITIVE BOOST WRITE-ASSIST CIRCUITS FOR MEMORY BIT CELLS EMPLOYING A P-TYPE FIELD-EFFECT TRANSISTOR (PFET) WRITE PORT(S), AND RELATED SYSTEMS AND METHODS

Thu, 25 Aug 2016 08:00:00 EDT

Write-assist circuits for memory bit cells (“bit cells”) employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-Effect transistor (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide bit cells having PFET write ports, as opposed to NFET write ports, to reduce memory write times to the bit cells, and thus improve memory performance. To mitigate a write contention that could otherwise occur when writing data to bit cells, a write-assist circuit provided in the form of a negative supply rail positive boost circuit can be employed to weaken an NFET pull-down transistor in a storage circuit of a memory bit cells having a PFET write port(s).



BITLINE POSITIVE BOOST WRITE-ASSIST CIRCUITS FOR MEMORY BIT CELLS EMPLOYING A P-TYPE FIELD-EFFECT TRANSISTOR (PFET) WRITE PORT(S), AND RELATED SYSTEMS AND METHODS

Thu, 25 Aug 2016 08:00:00 EDT

Write-assist circuits for memory bit cells (“bit cells”) employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-Effect transistor (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide bit cells having PFET write ports, as opposed to NFET write ports, to reduce memory write times to the bit cells, and thus improve memory performance. To mitigate a write contention that could otherwise occur when writing data to bit cells, a write-assist circuit provided in the form of positive bitline boost circuit can be employed to strengthen a PFET access transistor in a memory bit cell having a PFET write port(s).



WORDLINE NEGATIVE BOOST WRITE-ASSIST CIRCUITS FOR MEMORY BIT CELLS EMPLOYING A P-TYPE FIELD-EFFECT TRANSISTOR (PFET) WRITE PORT(S), AND RELATED SYSTEMS AND METHODS

Thu, 25 Aug 2016 08:00:00 EDT

Write-assist circuits for memory bit cells (“bit cells”) employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-Effect transistor (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide bit cells having PFET write ports, as opposed to NFET write ports, to reduce memory write times to the bit cells, and thus improve memory performance. To mitigate a write contention that could otherwise occur when writing data to bit cells, a write-assist circuit provided in the form of negative wordline boost circuit can be employed to strengthen a PFET access transistor in a memory bit cell having a PFET write port(s).



P-TYPE FIELD-EFFECT TRANSISTOR (PFET)-BASED SENSE AMPLIFIERS FOR READING PFET PASS-GATE MEMORY BIT CELLS, AND RELATED MEMORY SYSTEMS AND METHODS

Thu, 25 Aug 2016 08:00:00 EDT

P-type Field-effect Transistor (PFET)-based sense amplifiers for reading PFET pass-gate memory bit cells (“bit cells”) are disclosed. Related methods and systems are also disclosed. Sense amplifiers are provided in a memory system to sense bit line voltage(s) of the bit cells for reading the data stored in the bit cells. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-effect Transistor (NFET) drive current due for like-dimensioned FETs. In this regard, in one aspect, PFET-based sense amplifiers are provided in a memory system to increase memory read times to the bit cells, and thus improve memory read performance.



STATIC RANDOM-ACCESS MEMORY (SRAM) SENSOR

Thu, 25 Aug 2016 08:00:00 EDT

An apparatus includes a static random-access memory and circuitry configured to initiate a corrective action associated with the static random-access memory. The corrective action may be initiated based on a number of static random-access memory cells that have a particular state responsive to a power-up of the static random-access memory.



Semiconductor Memory Devices Including Redundancy Memory Cells

Thu, 25 Aug 2016 08:00:00 EDT

A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.



MEMORY MODULE, MEMORY SYSTEM INCLUDING THE SAME, AND DATA STORAGE SYSTEM INCLUDING THE MEMORY MODULE

Thu, 25 Aug 2016 08:00:00 EDT

A memory module includes a first printed circuit board (PCB) which includes a first surface, a second surface, first taps formed on the first surface, and second taps formed on the second surface, a first buffer attached to the first PCB, and first memory devices attached to the first PCB, in which the first buffer is configured to transmit signals input through the first taps and the second taps to the first memory devices, and signals re-driven by the first buffer among the signals are transmitted to a second module through the second taps.



MEMORY DEVICE WITH SHARED READ/WRITE CIRCUITRY

Thu, 25 Aug 2016 08:00:00 EDT

In some examples, a memory device may be configured to read or write multiple bit cells as part of the same operation. In some cases, the tunnel junctions forming the bit cells may be arranged to utilize shared read/write circuitry. For instance, the tunnel junctions may be arranged such that both tunnel junctions may be written using the same write voltages. In some cases, the bit cells may be configured such that each bit cell is driven to the same state, while in other cases, select bit cells may be driven high, while others are driven low.



MAGNETORESISTIVE DEVICE, MAGNETORESISTIVE RANDOM ACCESS MEMORY AND MAGNETIC RECORDING METHOD

Thu, 25 Aug 2016 08:00:00 EDT

A magnetoresistive device includes a magnetic free layer having first and second surfaces, the magnetic free layer being comprised of a ferromagnetic material having a perpendicular magnetic anisotropy, a spin current generation layer contacting the first surface of the magnetic free layer, a tunnel barrier layer having one surface contacting the second surface of the magnetic free layer, a reference layer contacting another surface of the tunnel barrier layer, and a leakage field generation layer including first and second leakage field generation layers each of which is comprised of a ferromagnetic material and generates a leakage field, an in-plane component of the leakage field at an part of the magnetic free layer is formed generating a domain wall having an in-plane magnetization component in the magnetic free layer.



SEMICONDUCTOR MEMORY DEVICE

Thu, 25 Aug 2016 08:00:00 EDT

A semiconductor memory device includes a plurality of memory cells, a data bus connected to a first column of the memory cells, by which data is transferred to and from the memory cells of the first column, a data latch storing data indicating whether the first column is defective or not, and a transistor having a first terminal connected to the data bus, a second terminal connected to a voltage source, and a gate connected to an output of the data latch.



MEMORY DEVICE

Thu, 25 Aug 2016 08:00:00 EDT

To provide a memory device where multiple pieces of multilevel data can be written and read. The memory device includes first to fifth transistors, first to fourth capacitors, first to fourth nodes, and first and second wirings. The first node is connected to the first capacitor and a gate of the first transistor, the second node is connected to the second capacitor and a gate of the second transistor, the third node is connected to the third capacitor and a gate of the third transistor, and the fourth node is connected to the fourth capacitor and a gate of the fourth transistor. Multiple pieces of multilevel data is written to the first to fourth nodes through the second to fifth transistors. The second to fifth transistors each preferably include an oxide semiconductor in a channel formation region.



VERTICAL NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

Thu, 25 Aug 2016 08:00:00 EDT

A vertical non-volatile memory device is structured/fabricated to include a substrate, groups of memory cell strings each having a plurality of memory transistors distributed vertically so that the memory throughout multiple layers on the substrate, integrated word lines coupled to sets of the memory transistors, respectively, and stacks of word select lines. The memory transistors of each set are those transistors, of one group of the memory cell strings, which are disposed in the same layer above the substrate. The word select lines are respectively connected to the integrated word lines.



SEMICONDUCTOR DEVICE HAVING BURIED GATE, METHOD OF FABRICATING THE SAME, AND MODULE AND SYSTEM HAVING THE SAME

Thu, 18 Aug 2016 08:00:00 EDT

A semiconductor device includes junction regions formed in upper portions of both sidewalls of a trench formed in a semiconductor substrate, a first gate electrode buried in the trench and having a stepped upper surface, and a second gate electrode formed on the first gate electrode to overlap a junction region.



Screening for Data Retention Loss in Ferroelectric Memories

Thu, 18 Aug 2016 08:00:00 EDT

A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. Sampled groups of cells in the FRAM array are tested at various reference voltage levels, after programming to a high polarization capacitance data state and a relaxation time at an elevated temperature. Fail bit counts of the sample groups at the various reference voltage levels are used to derive a test reference voltage, against which all of the FRAM cells in the integrated circuit are then tested after preconditioning (i.e., programming) and another relaxation interval at the elevated temperature, to determine those cells in the integrated circuit that are vulnerable to long-term data retention failure.



RESISTIVE MEMORY AND MEASUREMENT SYSTEM THEREOF

Thu, 18 Aug 2016 08:00:00 EDT

A measurement system including a testing machine and a resistive memory is provided. The resistive memory includes a first storage cell. The first storage cell includes a transistor and a variable resistor. During a specific period, the testing machine provides a write voltage to change the state of the variable resistor. During a maintaining period, the testing machine maintains the level of the write voltage and measures the current passing through the variable resistor. When the current passing through the variable resistor does not arrive at a pre-determined value, the testing machine increases the level of the write voltage. Furthermore, a resistive memory utilizing the testing machine is also provided.



WEAK BIT DETECTION USING ON-DIE VOLTAGE MODULATION

Thu, 18 Aug 2016 08:00:00 EDT

Methods and apparatuses for performing a disturb test on a memory are disclosed. Circuitry may be configured to store test data into one or more data storage cells. A regulation circuit may adjust a level of a power supply coupled to the one or more data storage cells from a first level to a second level. Once the voltage level of the power supply has reached the second level, the circuitry may perform a read operation on the one or more data storage cells. Upon completion of the read operation, the regulation circuit may return the voltage level of the power supply to the first level, and the circuitry may perform another read operation, the results of which, the circuitry may compare to the test data.



SEMICONDUCTOR MEMORY DEVICE

Thu, 18 Aug 2016 08:00:00 EDT

A semiconductor memory device includes a first memory cell, a first word line electrically connected to a gate of the first memory cell, a first bit line electrically connected to one end of the first memory cell, and a controller configured to execute a write operation, which includes a first cycle and a second cycle that is executed after the first cycle. The first cycle includes a first operation of applying a program voltage to the first word line, a second operation executed after the first operation of applying a first voltage to the first bit line and a second voltage lower than the first voltage to the first word line, and a third operation executed after the second operation of applying a verify voltage to the first word line. The second cycle includes the first operation and then the third operation, and excludes the second operation.



PROGRAMMING NONVOLATILE MEMORY DEVICE USING PROGRAM VOLTAGE WITH VARIABLE OFFSET

Thu, 18 Aug 2016 08:00:00 EDT

A method of programming a nonvolatile memory device comprises applying at least one test program pulse to selected memory cells located in a scan read area, performing a scan read operation on the selected memory cells following application of the at least one test program pulse to detect at least one one-shot upper cell, calculating an offset voltage corresponding to a scan read region at which the scan read operation is performed, setting a program start bias using the offset voltage, and executing at least one program loop using the program start bias.



Boundary Word Line Search and Open Block Read Methods with Reduced Read Disturb

Thu, 18 Aug 2016 08:00:00 EDT

Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for a read operation, including post-write verify reads. Non-selected word lines that are unwritten are biased with a lower read-pass voltage then is typically used. The determination of the last written word line of a block can be done in a coarse-fine search, where the word lines are divided into a number of zones to find the zone with the last written word line, which is in turn sub-divided for a finer search.



NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

Thu, 18 Aug 2016 08:00:00 EDT

A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first transistor has one end connected to one end of the memory string. The second transistor is provided between the other end of the memory string and a second line. The diode is provided between the other end of the first transistor and a first line. The diode comprises a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type.



Flash Memory System Using Complementary Voltage Supplies

Thu, 18 Aug 2016 08:00:00 EDT

A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. During the operations of program, read, or erase, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected memory cells.



SYSTEMS, DEVICES AND METHODS FOR MEMORY OPERATIONS

Thu, 18 Aug 2016 08:00:00 EDT

Systems, devices and methods are provided for memory operations. An example system includes: a latch circuit shared by a plurality of memory blocks of a memory device and configured to provide one or more regulation signals for a memory operation; a source line circuit shared by the plurality of memory blocks and configured to provide a source line voltage to the plurality of memory blocks for the memory operation based at least in part on the one or more regulation signals; and a plurality of driver circuits configured to provide a plurality of drive signals to the plurality of memory blocks based at least in part on the one or more regulation signals.



VOLTAGE DETECTOR, METHOD FOR SETTING REFERENCE VOLTAGE AND COMPUTER READABLE MEDIUM

Thu, 18 Aug 2016 08:00:00 EDT

A voltage detector for detecting whether an input voltage is no lower than a predetermined threshold voltage, includes a reference voltage generator configured to generate a reference voltage, and a comparator configured to receive the input voltage and the reference voltage and to detect whether the input voltage is no lower than the threshold voltage that is determined by the reference voltage. Here, the reference voltage generator includes a first write MOS transistor, a second write MOS transistor, a first output MOS transistor and a second output MOS transistor each including a control gate and a floating gate.



STORAGE DEVICE AND A WRITE METHOD THEREOF

Thu, 18 Aug 2016 08:00:00 EDT

A write method of a storage device includes determining whether to perform a coarse program operation based on information about memory cells of a memory device, in response to a determination that the coarse program operation is to be performed, programming data in the memory device by performing the coarse program operation and a fine program operation, and in response to a determination that the coarse program operation is not to be performed, programming data in the memory device by performing the fine program operation.



MEMORY PROGRAMMING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE

Thu, 18 Aug 2016 08:00:00 EDT

A memory programming method for a rewritable non-volatile memory module having memory cells is provided. The memory programming method includes: performing a first programming process on the memory cells according to write data and obtaining a first programming result of the first programming process; grouping the memory cells into programming groups according to the first programming result; and performing a second programming process on the memory cells according to the write data. The second programming process includes: programming a first programming group among the programming groups by using a first program voltage; and programming a second programming group among the programming groups by using a second program voltage. The first program voltage and the second program voltage are different. Moreover, a memory control circuit unit and a memory storage device are provided.



Flash Memory Device Configurable To Provide Read Only Memory Functionality

Thu, 18 Aug 2016 08:00:00 EDT

The disclosed embodiments comprise a flash memory device that can be configured to operate as a read only memory device. In some embodiments, the flash memory device can be configured into a flash memory portion and a read only memory portion.



3D NAND MEMORY WITH DECODER AND LOCAL WORD LINE DRIVERS

Thu, 18 Aug 2016 08:00:00 EDT

A memory device includes a plurality of stacks of conductive strips, a plurality of conductive vertical structures arranged orthogonally to the plurality of stacks, memory elements in interface regions at cross-points between side surfaces of the plurality of stacks and the plurality of conductive vertical structures, multiples pluralities of conductive lines, and control circuitry. The plurality of stacks of conductive strips alternate with insulating strips, including at least a bottom layer of conductive strips, a plurality of intermediate layers of conductive strips, and a top layer of conductive strips. A first plurality of conductive lines electrically couple to the top layer of the conductive strips. A second plurality of conductive lines and a third plurality of conductive lines electrically couple to the plurality of intermediate layers. The control circuitry causes the first plurality of conductive lines to select at least a first particular stack in the plurality of stacks, the second plurality of conductive lines to select at least the first particular stack in the plurality of stacks, and the third plurality of conductive lines to select at least one particular layer in the plurality of intermediate layers.



Screening for Later Life Stuck Bits in Ferroelectric Memories

Thu, 18 Aug 2016 08:00:00 EDT

A reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays for stuck bits. The FRAM devices are subjected to a high temperature bake in wafer form. A “shmoo” of the reference voltage is performed, at an elevated temperature, for each device to identify a first reference voltage at which a first cell in the device fails a read of its low polarization capacitance data state, and a second reference voltage at which a selected number of cells in the device fail the read. The slope of the line between the first and second reference voltages, in the cumulative fail bit count versus reference voltage plane, is compared with a slope limit to determine whether any stuck bits are present in the device.



RESISTIVE MEMORY SYSTEM AND METHOD OF OPERATING THE RESISTIVE MEMORY SYSTEM

Thu, 18 Aug 2016 08:00:00 EDT

A resistive memory system having a plurality of memory cells includes a memory device having a resistive memory cell array and a controller. The controller generates write data to be written to the memory cell array by encoding input data such that the input data corresponds to an erase state and a plurality of programming states that a memory cell may have. The input data is encoded such that at least one of the number of memory cells assigned a first programming state and the number of memory cells assigned a second programming state is smaller than at least one of the numbers of memory cells in the erase state and the other programming states. The first programming state has a highest resistance level among the plurality of programming states, and the second programming state has a second highest resistance level among the plurality of programming states.