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ACCESS CONTROL AND SECURITY FOR SYNCHRONOUS INPUT/OUTPUT LINKS

Thu, 06 Apr 2017 08:00:00 EDT

Aspects include providing automatic access control and security for a synchronous input/output (I/O) link. Providing automatic access control and security includes initializing devices of a storage environment over a first link to verify that the devices are available within the storage environment; building a table of identifiers, where each of the identifiers is assigned one of the devices that have been initialized; and verifying a first device attempting to perform synchronous I/O commands across the synchronization I/O link by confirming that an identifier assigned to the first device is within the table of identifiers.



PERIPHERAL DEVICE ACCESS USING SYNCHRONOUS INPUT/OUTPUT

Thu, 06 Apr 2017 08:00:00 EDT

Aspects include accessing data located on peripheral devices using synchronous input/output (I/O). A unit of work is received by an operating system (OS) executing on a processor. The unit of work includes an I/O request to access data located on a persistent storage control unit (SCU) that is external to the processor. It is determined that the I/O request should be serviced by a synchronous I/O. A synchronous I/O is initiated to the persistent SCU to service the I/O request based on determining that the I/O request should be serviced by a synchronous I/O. The unit of work is kept active while waiting for the synchronous I/O to complete. A notification that the I/O has completed is received and the unit of work is completed in response to receiving the notification.



PERIPHERAL DEVICE ACCESS USING SYNCHRONOUS INPUT/OUTPUT

Thu, 06 Apr 2017 08:00:00 EDT

Aspects include accessing data located on peripheral devices using synchronous input/output (I/O). A unit of work is received by an operating system (OS) executing on a processor. The unit of work includes an I/O request to access data located on a persistent storage control unit (SCU) that is external to the processor. It is determined that the I/O request should be serviced by a synchronous I/O. A synchronous I/O is initiated to the persistent SCU to service the I/O request based on determining that the I/O request should be serviced by a synchronous I/O. The unit of work is kept active while waiting for the synchronous I/O to complete. A notification that the I/O has completed is received and the unit of work is completed in response to receiving the notification.



Handling CPU Hotplug Events In RCU Without Sleeplocks

Thu, 06 Apr 2017 08:00:00 EDT

Read-copy update (RCU) grace period initialization and CPU hotplugging are synchronized without a sleeplock. Periodic RCU grace period initialization includes, for each node of a combining tree, copying a first bitmask indicating online/offline status of a set of CPUs to a second bitmask indicating RCU quiescent state status of the CPUs. Periodic CPU hotplug operations include indicating CPU online/offline status to leaf nodes associated with the CPUs. This status is indicated without manipulating any bits in the first bitmask of the leaf nodes. Prior to each RCU grace period initialization, RCU grace period pre-initialization is performed at each leaf node. The RCU grace period pre-initialization includes (1) updating the first bitmask to account for the CPU hotplug operations, and (2) if this results in the first bitmask transitioning between fully cleared and not-fully cleared states, the state change is conditionally propagated to a higher level node.



Handling CPU Hotplug Events In RCU Without Sleeplocks

Thu, 06 Apr 2017 08:00:00 EDT

Read-copy update (RCU) grace period initialization and CPU hotplugging are synchronized without a sleeplock. Periodic RCU grace period initialization includes, for each node of a combining tree, copying a first bitmask indicating online/offline status of a set of CPUs to a second bitmask indicating RCU quiescent state status of the CPUs. Periodic CPU hotplug operations include indicating CPU online/offline status to leaf nodes associated with the CPUs. This status is indicated without manipulating any bits in the first bitmask of the leaf nodes. Prior to each RCU grace period initialization, RCU grace period pre-initialization is performed at each leaf node. The RCU grace period pre-initialization includes (1) updating the first bitmask to account for the CPU hotplug operations, and (2) if this results in the first bitmask transitioning between fully cleared and not-fully cleared states, the state change is conditionally propagated to a higher level node.



Avionics system of an aircraft comprising line replaceable units that can exchange messages between them and device for monitoring such an avionics system

Thu, 06 Apr 2017 08:00:00 EDT

An aircraft avionics system comprising rack mounted line replaceable units that exchange messages between them via a bus. The avionics system comprises a monitoring device arranged in the rack comprising a connector electrically linked to the bus and into which a rack mounted line replaceable unit is plugged, to be electrically linked to the bus. The monitoring device also monitors the messages exchanged, via the bus, between the line replaceable unit plugged into its connector and other units of the avionics system. The monitoring device comprises an acquisition unit to acquire signals transmitted or received by the line replaceable unit plugged into the connector during the exchange of messages with at least one other unit of the avionics system, for converting the signals into storable digital data and for assigning clock data to the data, and a storage unit for storing the storable digital data and the clock data.



SYNCHRONOUS INPUT/OUTPUT MEASUREMENT DATA

Thu, 06 Apr 2017 08:00:00 EDT

Aspects include acquiring measurement data of a synchronous input/output (I/O) link between an operating system and a recipient. The acquiring measurement data can include monitoring operating system usage of synchronous I/O commands on the synchronous I/O link and storing the operating system usage in a measurement block as the measurement data. Further, the measurement block is accessible by the operating system to determine that the measurement data is acquired.



SENSOR SYSTEMS AND METHODS UTILIZING ADAPTIVELY SELECTED CARRIER FREQUENCIES

Thu, 06 Apr 2017 08:00:00 EDT

A sensor system utilizing adaptively selected carrier frequencies is disclosed. The system includes a system bus, a bus master, and a sensor. The system bus is configured to transfer power and data. The bus master is coupled to the system bus and is configured to provide power to the bus and receive data from the bus. The sensor is coupled to the system bus and is configured to transfer data on the bus using an adaptively selected carrier frequency.



COMMUNICATION SYSTEM, COMMUNICATION SYSTEM CONTROL METHOD, AND PROGRAM

Thu, 06 Apr 2017 08:00:00 EDT

Communication systems and communication control methods are disclosed. In one example, a slave device belonging to a group of devices to which arbitration is applicable sequentially transmits a start bit and a first address including a first bit having a value different from a corresponding first bit of predetermined pattern data. A master device sequentially transmits the start bit and the predetermined pattern data. The master device arbitrates the master device and the first slave device based on the value of the first bit.



INPUT/OUTPUT APPARATUS AND METHOD

Thu, 06 Apr 2017 08:00:00 EDT

An input/output apparatus according to the present invention has an indication unit and an execution unit. The indication unit indicates that each of a plurality of data blocks between a main memory and a buffer memory is to be transferred. The execution unit transfers one data block relating to a transfer indication sent from the indication unit. After the completion of the transfer, in order to send completion information relating to the one data block to the indication unit, the execution unit determines whether transfers of all of the plurality of data blocks are completed or not based on management information for managing progresses of the transfers of the plurality of data blocks. Once determining that all of the transfers are completed, the execution unit sends, to the indication unit, total completion information showing that all of the transfers are completed.



DIRECT MEMORY ACCESS FOR PROGRAMMABLE LOGIC DEVICE CONFIGURATION

Thu, 06 Apr 2017 08:00:00 EDT

Using a storage interface circuit of a programmable IC, a first set of configuration data can be communicated between a storage circuit and the programmable IC. Using the first set of configuration data, the programmable IC can be programmed to include: a bus interface module that is designed to interface with a host device over a communication bus that links multiple devices, and an internal configuration access interface that is designed to interface between the bus interface module and programmable logic of the programmable IC. Using direct memory access (DMA) transfers through the bus interface module, a second set of configuration data can be communicated between a memory circuit and the programmable IC. Using the second set of configuration data, the programmable logic of the programmable IC can be programmed.



STORAGE CONTROLLER CACHE MEMORY OPERATIONS THAT FOREGO REGION LOCKING

Thu, 06 Apr 2017 08:00:00 EDT

Methods and structure for managing cache memory for a storage controller. One exemplary embodiment a Redundant Array of Independent Disks (RAID) storage controller. The storage controller includes an interface operable to receive Input/Output (I/O) requests from a host, a Direct Memory Access (DMA) module, a memory comprising cache data for a logical volume, and a control unit. The control unit is able to generate Scatter Gather Lists (SGLs) that indicate the location of cache data for incoming read requests. Each SGL is stored in the memory, and at least one SGL points to cache data that is no longer indexed by the cache. The control unit is also able to service an incoming read request based on the SGL, by directing the DMA module to transfer the cache data that is no longer indexed to the host.



SPACE EFFICIENT FORMATS FOR SCATTER GATHER LISTS

Thu, 06 Apr 2017 08:00:00 EDT

Methods and structure for formatting and processing Scatter Gather Lists (SGLs). One exemplary embodiment is a storage controller that includes a cache memory storing data for a logical volume, and a control unit. The control unit is able to service an Input/Output (I/O) request based on a Scatter Gather List (SGL) that refers to the cache memory, the SGL comprising multiple entries that each include a flag field and an identifier (ID) field. The entries are assigned to categories that are each associated with a different set of stored processing instructions. The control unit is able to identify a category for an entry based on a combination of both flag field and ID field for the entry, and the control unit is able to process the entry using the set of instructions associated with the identified category.



HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER

Thu, 06 Apr 2017 08:00:00 EDT

Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a pre-defined sequence on each of the lanes.



SYNCHRONOUS INPUT/OUTPUT COMMAND

Thu, 06 Apr 2017 08:00:00 EDT

Aspects include sending a request to perform a unit of work that includes a synchronous I/O operation. The sending is from an operating system (OS) executing on a server to firmware located on the server. The synchronous I/O request includes a command request block that includes an operation code identifying the synchronous I/O operation and a identifier of a persistent storage control unit (SCU). The OS waits for the synchronous I/O to complete and the unit of work remains active during the waiting. The firmware detects that the synchronous I/O operation has completed. A command response block that includes completion status information about the synchronous I/O operation is received by the OS from the firmware. The unit of work is completed in response to the I/O operation completing.



SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING

Thu, 06 Apr 2017 08:00:00 EDT

A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.



MEMORY MODULE WITH REDUCED READ/WRITE TURNAROUND OVERHEAD

Thu, 06 Apr 2017 08:00:00 EDT

A memory module includes a substrate, plural memory devices, and a buffer. The plural memory devices are organized into at least one rank, each memory device having plural banks. The buffer includes a primary interface for communicating with a memory controller and a secondary interface coupled to the plural memory devices. For each bank of each rank of memory devices, the buffer includes data buffer circuitry and address buffer circuitry. The data buffer circuitry includes first storage to store write data transferred during a bank cycle interval (tRR). The address buffer circuitry includes second storage to store address information corresponding to the data stored in the first storage.



METHOD AND APPARATUS FOR BUS LOCK ASSISTANCE

Thu, 06 Apr 2017 08:00:00 EDT

A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.



SYNCHRONOUS INPUT/OUTPUT MEASUREMENT DATA

Thu, 06 Apr 2017 08:00:00 EDT

Aspects include acquiring measurement data of a synchronous input/output (I/O) link between an operating system and a recipient. The acquiring measurement data can include monitoring operating system usage of synchronous I/O commands on the synchronous I/O link and storing the operating system usage in a measurement block as the measurement data. Further, the measurement block is accessible by the operating system to determine that the measurement data is acquired.



EFFICIENT VIRTUAL I/O ADDRESS TRANSLATION

Thu, 06 Apr 2017 08:00:00 EDT

A method includes using a network interface controller to monitor a transmit ring, wherein the transmit ring comprises a circular ring data structure that stores descriptors, wherein a descriptor describes data and comprises a guest bus address that provides a virtual memory location of the data. The method also includes using the network interface controller to determine that a descriptor has been written to the transmit ring. The method further includes using the network interface controller to attempt to retrieve a translation for the guest bus address. The method includes using the network interface controller to read the descriptor from the transmit ring.



SYNCHRONOUS INPUT/OUTPUT USING A LOW LATENCY STORAGE CONTROLLER CONNECTION

Thu, 06 Apr 2017 08:00:00 EDT

Aspects include transmitting a synchronous I/O command to a persistent storage control unit (SCU in response to a synchronous I/O request from an operating system (OS). A unit of work in the OS corresponding to the synchronous I/O request remains active at least until the synchronous I/O request is completed. Based on an operation code of the synchronous I/O command specifying a read operation and in response to detecting that the persistent SCU has stored one or more read data records in a memory located on the processor, the firmware indicates to the OS that the synchronous I/O request is completed. Based on the operation code specifying a write operation and in response to detecting an indication from the persistent SCU that write data has been written or indicating that an error has occurred, indicating to the OS that the synchronous I/O request is completed.



SYNCHRONOUS INPUT/OUTPUT COMMAND

Thu, 06 Apr 2017 08:00:00 EDT

Aspects include sending a request to perform a unit of work that includes a synchronous I/O operation. The sending is from an operating system (OS) executing on a server to firmware located on the server. The synchronous I/O request includes a command request block that includes an operation code identifying the synchronous I/O operation and a identifier of a persistent storage control unit (SCU). The OS waits for the synchronous I/O to complete and the unit of work remains active during the waiting. The firmware detects that the synchronous I/O operation has completed. A command response block that includes completion status information about the synchronous I/O operation is received by the OS from the firmware. The unit of work is completed in response to the I/O operation completing.



SYNCHRONOUS INPUT/OUTPUT COMMANDS WRITING TO MULTIPLE TARGETS

Thu, 06 Apr 2017 08:00:00 EDT

Aspects include communicating synchronous input/output (I/O) commands between an operating system and a recipient. Communicating synchronous I/O commands includes issuing a first synchronous I/O command with a first initiation bit set, where the first synchronous I/O command cause a first mailbox command to be initiated by the recipient with respect to a first storage control unit. Further, communicating synchronous I/O commands issuing a second synchronous I/O command with a second initiation bit set, where the second synchronous I/O command causes a second mailbox command to be initiated by the recipient with respect to at least one subsequent storage control unit. Communicating synchronous I/O commands also includes issuing a third synchronous I/O command with a first completion bit set in response to the first mailbox command being initiated and issuing a fourth synchronous I/O command with a second completion bit set in response to the first mailbox command being initiated.



SYNCHRONOUS INPUT/OUTPUT COMMANDS WRITING TO MULTIPLE TARGETS

Thu, 06 Apr 2017 08:00:00 EDT

Aspects include communicating synchronous input/output (I/O) commands between an operating system and a recipient. Communicating synchronous I/O commands includes issuing a first synchronous I/O command with a first initiation bit set, where the first synchronous I/O command cause a first mailbox command to be initiated by the recipient with respect to a first storage control unit. Further, communicating synchronous I/O commands issuing a second synchronous I/O command with a second initiation bit set, where the second synchronous I/O command causes a second mailbox command to be initiated by the recipient with respect to at least one subsequent storage control unit. Communicating synchronous I/O commands also includes issuing a third synchronous I/O command with a first completion bit set in response to the first mailbox command being initiated and issuing a fourth synchronous I/O command with a second completion bit set in response to the first mailbox command being initiated.



SYNCHRONOUS INPUT/OUTPUT COMMAND WITH PARTIAL COMPLETION

Thu, 06 Apr 2017 08:00:00 EDT

Aspects include communicating synchronous input/output (I/O) commands between an operating system and recipient by issuing a first synchronous I/O command with an initiation bit set, identifying that a mailbox command has been initiated to return control to an operating system before waiting for operations of the first synchronous I/O command to complete, and issuing a second synchronous I/O command with a completion bit set in response to the control returning to the operating system.



SYNCHRONOUS INPUT/OUTPUT COMMAND WITH PARTIAL COMPLETION

Thu, 06 Apr 2017 08:00:00 EDT

Aspects include communicating synchronous input/output (I/O) commands between an operating system and recipient by issuing a first synchronous I/O command with an initiation bit set, identifying that a mailbox command has been initiated to return control to an operating system before waiting for operations of the first synchronous I/O command to complete, and issuing a second synchronous I/O command with a completion bit set in response to the control returning to the operating system.



Method and Apparatus for Adaptively Managing Power

Thu, 06 Apr 2017 08:00:00 EDT

Various embodiments of the present disclosure relate to an adaptive power management method and apparatus. The electronic device includes: a first interface for communicating with a first external electronic device functionally connected to the electronic device; a second interface for receiving power supplied by a second external electronic device; and a processor, wherein the processor determines whether the electronic device is electrically connected to the second external electronic device through the second interface, generates state information corresponding to a result of the determination, and transmits the state information to the first external electronic device through the first interface. Furthermore, various embodiments are possible.