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Electrical Isolation in Serial Communication

Thu, 03 Nov 2016 08:00:00 EDT

First and second communication interfaces receive and transmit first and second communications through isolation circuitry at different communication frequency levels. In some embodiments, the first and second communication interfaces are USB 3 compatible, and the isolation circuitry is between the first and second communication interfaces and is compatible with all USB 3 communication modes.



COMMUNICATION SYSTEM, CONTROL APPARATUS, AND MANAGEMENT APPARATUS

Thu, 03 Nov 2016 08:00:00 EDT

By provided with a first extraction unit configured to extract a communication setting value corresponding to a communication cable provided to a first connector, from communication setting information, based on cable information gathered by a first gathering unit, a first setting unit configured to set the communication setting value, to a first storage device of a first communication switch, a first activation unit configured to activate a port of the first communication switch, and a first synchronization unit configured to cause a management apparatus to carry out an activation of a port of a second communication switch provided in a communication apparatus in synchronization with the activation of the port, the flexibility of configurations employing communication cables is improved.



DISPLAY DEVICE

Thu, 03 Nov 2016 08:00:00 EDT

There is provided a display device including an input unit configured to connect an external device to a serial peripheral interface (SPI) through a plurality of connection lines, a switching unit configured to connect the input unit and a flash memory of a driving board to the SPI, a data register configured to output connection setting data for determining a connection state of the switching unit, and a timing controller configured to output a control signal for determining the connection setting data according to an input of a write enable line among the plurality of connection lines.



NUMA-AWARE ROOT BUS SELECTION

Thu, 03 Nov 2016 08:00:00 EDT

A method includes determining a first host Non-Uniform Memory Access (NUMA) node of a plurality of host NUMA nodes on a host machine that provides a virtual machine to a guest, the first host NUMA node being associated with a pass-through device, creating a virtual NUMA node on the virtual machine, mapping the virtual NUMA node to the first host NUMA node, adding a virtual expander to a virtual root bus of the virtual machine, and associating the virtual expander with the virtual NUMA node.



ELECTRONIC DEVICE OPERATING METHOD AND ELECTRONIC DEVICE FOR SUPPORTING THE SAME

Thu, 03 Nov 2016 08:00:00 EDT

An electronic device is provided. The electronic device includes a memory configured to store at least one instruction associated with a universal serial bus (USB) communication function or a wireless communication function operation, and at least one processor connected to the memory and configured to execute the at least one instruction stored in the memory. When a request for execution of the wireless communication function is received during execution of the USB communication function, the at least one instruction executed by the processor is configured to deactivate the execution of USB communication function in corresponding to a type of the USB communication function.



Computing architecture with peripherals

Thu, 03 Nov 2016 08:00:00 EDT

A shared memory computing architecture (300) has M interconnect masters (350, 351, 352, 353, 354), one interconnect target (370), and a timeslot based interconnect (319). The interconnect (319) has a unidirectional timeslot based interconnect (320) to transport memory transfer requests with T timeslots and a unidirectional timeslot based interconnect (340) to transport memory transfer responses with R timeslots. For each of the R timeslots, that timeslot: corresponds to one memory transfer request timeslot and starts at least L clock cycles after the start time of that corresponding memory request timeslot. The value of L is >=3 and



INFORMATION PROCESSOR WITH TIGHTLY COUPLED SMART MEMORY UNIT

Thu, 03 Nov 2016 08:00:00 EDT

A processor includes a plurality of first processing units. A direct memory access unit is coupled to at least one first processing unit of the plurality of first processing units. The processor includes a plurality of data storage units. A second processing unit is adapted to process data from at least one data storage unit of the plurality of data storage units. The direct memory access unit is configured to transfer data stored in a memory to the at least one data storage unit of the plurality of data storage units. The second processing unit is separate from the plurality of first processing units and the direct memory access unit. The at least one first processing unit and the second processing unit are configured to work in parallel. The processor further includes a first register. The second processing unit is configured to receive an operation signal from the first register.



ADAPTIVE INTERRUPT MODERATION

Thu, 03 Nov 2016 08:00:00 EDT

Generally, this disclosure relates to adaptive interrupt moderation. A method may include determining, by a host device, a number of connections between the host device and one or more link partners based, at least in part, on a connection identifier associated with each connection; determining, by the host device, a new interrupt rate based at least in part on a number of connections; updating, by the host device, an interrupt moderation timer with a value related to the new interrupt rate; and configuring the interrupt moderation timer to allow interrupts to occur at the new interrupt rate.



Central Processing Unit With Enhanced Instruction Set

Thu, 03 Nov 2016 08:00:00 EDT

An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.



Controlling Data Transfer for Data Processing

Thu, 03 Nov 2016 08:00:00 EDT

A computer-implemented method for controlling data transfer for data processing includes: receiving a data set by a first processor; storing the data set in a buffer by the first processor; and transferring, from the buffer to a queue by the first processor, a batch data set including all data sets stored in the buffer during a time interval, under a condition that the queue is not accessed by a second processor while the transferring is being performed, wherein the batch data set is to be processed by the second processor. In the method, the time interval is adjusted depending on a state of the queue.



ENHANCED INITIALIZATION FOR DATA STORAGE ASSEMBLIES

Thu, 03 Nov 2016 08:00:00 EDT

Systems, methods, apparatuses, and software for data storage systems are provided herein. In one example, a data storage platform includes data storage assemblies each comprising one or more storage drives that service data storage operations over associated storage interfaces. A control processor is coupled to ones of the data storage assemblies over at least two types of sideband communication interfaces different than the storage interfaces of the storage drives. During an initialization process for the one or more storage drives, the control processor configured to transfer initialization data to each of the data storage assemblies over a first type of sideband communication interface and transfer further initialization data to at least one of the data storage assemblies over a second type of sideband communication interface when the at least one of the data storage assemblies does not respond to the initialization data over the first type of sideband communication interface.



STORAGE APPARATUS, CONTROL APPARATUS AND COMPUTER-READABLE RECORDING MEDIUM HAVING STORED THEREIN CONTROL PROGRAM

Thu, 03 Nov 2016 08:00:00 EDT

A storage apparatus includes a plurality of control devices configured to control access a plurality of storage devices, and a relay apparatus including a plurality of coupling devices, each of which is configured to couple the control devices so as to be communicable with each other. The relay apparatus includes, for each coupling device, a monitoring controller configured to perform monitoring of the relay apparatus. A first monitoring controller provided in a first coupling device from among the coupling devices notifies, when the first monitoring controller detects an abnormal state in the relay apparatus, a first control device from among the control devices of information relating to the abnormal state detected by the first monitoring controller. The first control device performs a decoupling process that decouples an abnormal part from the relay apparatus based on the information relating to the abnormal state received from the first monitoring controller.



CONTROL APPARATUS, STORAGE APPARATUS AND COMPUTER-READABLE RECORDING MEDIUM HAVING STORED THEREIN CONTROL PROGRAM

Thu, 03 Nov 2016 08:00:00 EDT

A control apparatus served as a first control apparatus includes a first information storage unit configured to store therein coupling information relating to a coupling relationship between a plurality of control apparatus and a plurality of devices, the plurality of control apparatus including the first control apparatus and controlling access to the plurality of devices, and a processor. The processor specifies, in response to a first access request to a first device from among the plurality of devices, a second control apparatus responsible for the first device based on the coupling information stored in the first information storage unit, and issues an instruction to access to the first device based on the first access request received by the first control apparatus to the specified second control apparatus through a relay apparatus that relays information to be transferred between the plurality of control apparatus.



DISTRIBUTED INTELLIGENT PLATFORM MANAGEMENT INTERFACE (D-IPMI) SYSTEM AND METHOD THEREOF

Thu, 03 Nov 2016 08:00:00 EDT

Certain aspects direct a distributed Intelligent Platform Management Interface (D-IPMI) system. The system includes a computing device and a distributed management device. The distributed management device includes a first management device and at least one second management device physically separated from each other. A stack interface connects the first management device and the second management device to perform an internal communication between the first management device and the second management device. The first management device may be used to perform time critical functions related to the computing device, and the second management device may be used to perform non-critical functions. For example, the first management device may perform system power control of the computing device, monitor system components and obtaining system information of the computing device, and perform system communication with the computing device. The second management device may perform an external communication through the external interface.



CIRCUIT FOR CONTROLLING ACCESS TO MEMORY USING ARBITER

Thu, 03 Nov 2016 08:00:00 EDT

The present invention relates to a technology enabling a normal access by controlling a read access through an arbiter in a circuit for controlling an access to memory to which clock signals are input through two ports, respectively for a read access to a single port memory. The present invention includes an arbiter that generates an internal clock signal through a state transition among a first state for generating a first clock signal, a second state for generating a second clock signal, a standby state and a neutral state when generating the internal clock signal for reading data from the memory on the basis of the first clock signal and the second clock signal, and a read end signal that is supplied from the memory.



UNIVERSAL SERIAL BUS SMART HUB

Thu, 03 Nov 2016 08:00:00 EDT

A USB smart hub may provide enhanced battery charging, data storage security, vendor matching, device authentication, data capture/debug, and role switching. The smart hub may include an upstream port, a plurality of downstream ports, a processor, and a memory coupled to the processor for storing USB host stack code and configuration parameters. The smart hub may include a USB hub core having a core to implement a standard USB hub interface. The smart hub may include a plurality of 2:1 multiplexors coupled between the downstream ports, the core downstream ports, and the processor. The processor may control the 2:1 multiplexors. The processor may be configured to detect when a USB device is coupled to a downstream port and to run the USB host stack code and to enumerate the USB device. The processor may provide enhanced features based on the configuration parameters.



BUS CONNECTION TARGET DEVICE, STORAGE CONTROL DEVICE AND BUS COMMUNICATION SYSTEM

Thu, 03 Nov 2016 08:00:00 EDT

The present invention includes an abnormality detector which detects abnormality which is being transferred and issues an error notification to a connection monitor, and a disconnection processor which, when receiving the error notification, disconnects connection made via a bus switch, so that it is possible to prevent propagation of abnormality when abnormality is detected in data which is being transferred.



NETWORK FUNCTIONS VIRTUALIZATION PLATFORMS WITH FUNCTION CHAINING CAPABILITIES

Thu, 03 Nov 2016 08:00:00 EDT

A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. The coprocessor may include multiple virtual function hardware acceleration modules each of which is configured to perform a respective accelerator function. A virtual machine running on the host processor may wish to perform multiple accelerator functions in succession at the coprocessor on a given data. In one suitable arrangement, intermediate data output by each of the accelerator functions may be fed back to the host processor. In another suitable arrangement, the successive function calls may be chained together so that only the final resulting data is fed back to the host processor.



FIELD-PROGRAMMABLE GATE ARRAY CONFIGURATION CIRCUIT, RADIO-FREQUENCY UNIT AND MAGNETIC RESONANCE SYSTEM

Thu, 03 Nov 2016 08:00:00 EDT

In a field-programmable gate array (FPGA) configuration circuit, and a radio-frequency unit and a magnetic resonance system having a configuration circuit, the configuration circuit has at least two FPGA modules, each FPGA module being individually connected to a bus; at least two storage devices, each storage device storing a configuration file; one of the at least two FPGA modules being connected to the at least two storage devices separately, and an input end, connected separately to the at least two storage devices. A selection signal is provided for selecting one of the at least two storage devices. The FPGA module connected to the at least two storage devices reads a configuration file stored in a storage device selected on the basis of the selection signal, and sends, via the bus, the configuration file that has been read to the FPGA module other than the FPGA module connected to the at least two storage devices.



CHIP STARTING METHOD, MULTI-CORE PROCESSOR CHIP AND STORAGE MEDIUM

Thu, 03 Nov 2016 08:00:00 EDT

A chip starting method, a multi-core processor chip and a storage medium. The chip starting method comprises: setting a first starting priority for more than two processors, and separately setting, for each processor, a second priority of starting each storage unit in more than two storage units; determining, according to the first priority, a first processor that is to be started and has the highest priority; the first processor successively loading a start program from each storage unit according to the second priority corresponding to the first processor, and executing the start program to perform an initialization operation; ending program loading of the first processor when loading of the start program from any storage unit in the more than two storage units succeeds, or loading of the start program from all storage units in the more than two storage units fails; and starting program loading of the second processor and so on until program loading of the more than two processors is completed.



MULTI-THREAD NETWORK STACK BUFFERING OF DATA FRAMES

Thu, 03 Nov 2016 08:00:00 EDT

Systems, methods, apparatuses, and software for networked data systems are provided herein. In one example, a networked data processing system is presented. The system includes a processing system configured to execute an operating system that comprises a network module for handling data frames received over one or more network interfaces of the networked data processing system, the data frames directed to one or more applications. The network module is configured to establish a plurality of data buffers individually associated with application threads of the one or more applications, store associated ones of the data frames for the application threads in the data buffers as the data frames are processed through a network stack of the networked data processing system, and maintain data exclusivity locks for the plurality of data buffers and individually associate the data exclusivity locks with the application threads.



Smart Load Balancing Replication When Adding or Removing Storage Disks in a Distributed Storage System

Thu, 03 Nov 2016 08:00:00 EDT

A mechanism is provided for balancing workload to one or more storage disks in a plurality of storage disks during redistribution or replication associated with adding or removing a storage disk to the plurality of storage disks. Historical information in collected information from the plurality of storage disks is analyzed to identify I/O operation patterns on a per storage disk level. An average amount of I/O operations that occur within each storage disk for a given time period are identified. For each storage disk that is impacted, a disk on/off-hoarding plan is generated that identifies a subset of I/O operations from a set of I/O operations to execute in the given time period using the average amount of I/O operations that historically occur within the storage disk that is impacted during the given time period. The subset of I/O operations are then executed in the given time period.