Thu, 25 Aug 2016 08:00:00 EDTBaseboard management systems and methods with distributed intelligence for multi-node platforms. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include a plurality of modules, each of the plurality of modules including a plurality of nodes, each of the plurality of nodes including a system-on-chip (SoC), each of the plurality of SoCs including an integrated management controller (iMC), each of the plurality of iMCs configured to implement a first intelligent platform management interface (IPMI) stack having a first architecture; and a plurality of baseboard management controllers (BMCs), each of the BMCs disposed on a corresponding one of the plurality of modules, each of the BMCs coupled to the plurality of iMCs on the corresponding one of the plurality of modules, each of the plurality of iMCs configured to implement a second IPMI stack having a second architecture different from the first architecture.
Thu, 25 Aug 2016 08:00:00 EDTA system includes a slave device, and first and second master devices. A chipset of the slave device is capable of communication with a specific number of master devices. The first master device is configured to connect the information handling system with the slave device, to receive a transmission power setting of the slave device while the first master device is connected to the slave device, to disconnect the from the slave device, and to continuously track a received signal strength indicator of the slave device while the first master is disconnected from the slave. The second master device configured to connect with the slave device in response to the first master device disconnecting from the slave device, wherein the connection to the second master causes the slave device to communicate with at least one more master device than the specific number of master devices.
Thu, 25 Aug 2016 08:00:00 EDTThe present invention provides integrated circuit and apparatus having USB connector; the integrated circuit includes a signaling circuit and an interface for relaying signal between the USB connector and the signaling circuit, wherein an interconnect scheme of the signaling circuit is different from USB interconnect defined by USB specification; for example, a frequency adopted for signaling can be programmable, be lower than wireless band and/or be different from a frequency of USB SuperSpeed interconnect.
Thu, 25 Aug 2016 08:00:00 EDTHot-plug actions are enabled in an M-host, N-card system architecture. An arbiter receives status signals from the N hot-pluggable cards, and transfers the status signals to at least some of the M host devices. In response to the status signals indicating a hot-plug action, the arbiter receives at least one host command. The arbiter transfers the host command to one or more of the N hot-pluggable cards according to an arbiter algorithm.
Thu, 25 Aug 2016 08:00:00 EDTA communication apparatus includes a first connector, a communication unit, and at least one processor. The first connector is configured to be attachable to and removable from a second connector of a portable telephone to which a cable is attached in transmission and reception of data to and from another device. The communication unit is configured to convert data into a radio signal and transmit the radio signal and to convert a received radio signal into data. The processor is configured to receive data from a portable telephone through the first connector, output the received data to the communication unit, receive data converted by the communication unit, and output the received data to a portable telephone through the first connector.
Thu, 25 Aug 2016 08:00:00 EDTAn information processing apparatus is connected through a plurality of paths to a plurality of controllers included in a storage device and includes a processor. The processor is configured to issue, to the storage device, an inquiry about a recommended path through which a data access command is to be issued to the storage device. The processor is configured to compare a delay predictive time with a response predictive time in regard to the data access command. The delay predictive time is a predictive value of a delay time due to a data communication using an inter-controller communication between the plurality of controllers. The response predictive time is a predictive value of a response time when the inquiry is issued to the storage device. The processor is configured to suppress the issuance of the inquiry when the response predictive time is equal to or longer than the delay predictive time.
Thu, 25 Aug 2016 08:00:00 EDTMethods and structure for enhancing connection pathways for storage controllers. An exemplary system includes a stack of Serial Attached Small Computer System Interface (SAS) expanders that are coupled to each other in series. The stack includes two end expanders that are endpoints of the stack which are directly coupled to only one other SAS expander of the stack, and a plurality of middle expanders that are each directly coupled to two other SAS expanders of the stack. The system further includes a plurality of storage devices that are coupled to the SAS expanders of the stack, and a SAS storage controller comprising multiple SAS ports that are each directly coupled to a different SAS expander of the stack, wherein at least one of the multiple SAS ports is directly coupled to a middle expander of the stack.
Thu, 25 Aug 2016 08:00:00 EDTThis application relates to methods and apparatus for transfer of data between a host device (400) and a peripheral device (300) via a USB Type-C connector (100; 304) of the host device. A data controller is described that has a path controller (309, 310; 706) for establishing signal paths between circuitry of the host device and contacts (101) of said USB Type-C connector. The path controller is operable in at least first and second modes. In the first mode the path controller establishes separate signal paths to each of at least first, second, third and fourth contacts (A6, A7, B6, B7) of the USB Type-C connector and a plurality of the established signal paths are for transfer of analogue audio data. In the second mode the path controller establishes a pair of signal paths to only a subset of said first to fourth contacts to provide a differential digital data path.
Thu, 25 Aug 2016 08:00:00 EDTTechniques to generate local configuration data of a connection of local end of a cable to a SAS expander, store the data to a memory of the expander, then send a request to a local module at the local end of the cable to store the data to a memory at the local end of the cable, and send a request to a SAS device connected to a remote end of the cable to store the data at a memory located at the remote end of the cable. In response to a disconnection and reconnection of the local end of the cable with the expander, send a request to the local module to retrieve the data. If the retrieved data is different than the stored data, then generate a signal to alert of a misconfiguration between the local end of the cable and the expander.
Thu, 25 Aug 2016 08:00:00 EDTIn an example, a method for transmitting data includes determining, at a Universal Serial Bus (USB) host, a USB data transfer type of USB data being transmitted from the host device to a USB device, and determining a priority of the USB data based on the determined USB data transfer type. The example method also includes controlling transfer of the USB data from a protocol adaptation layer (PAL) of the USB host to a network layer of the USB host based on the determined priority.
Thu, 25 Aug 2016 08:00:00 EDTIn one aspect of the present description, in an input/output (I/O) device having multiple CPUs and multiple I/O ports, a cycle of I/O port rotations is initiated in which each port rotation of the cycle includes rotating an assignment of at least one I/O port from one CPU to a different CPU of a plurality of the CPUs. In the illustrated embodiment, an I/O port assignment for each CPU of the plurality CPUs is rotated for at least a portion of the cycle. Other features and aspects may be realized, depending upon the particular application.
Thu, 25 Aug 2016 08:00:00 EDTA communication system for inter-chip communication includes system processors that communicate with one another via data channels of a communication bus. A processor designated as a master processor assumes control of the transmission to the other processor designated as a slave processor. A data channel is operated in a separate physical communication bus for each data communication direction
Thu, 25 Aug 2016 08:00:00 EDTA hybrid message-based scheduling technique efficiently load balances a storage I/O stack partitioned into one or more non-blocking (i.e., free-running) messaging kernel (MK) threads that execute non-blocking message handlers (i.e., non-blocking services) and one or more operating system kernel blocking threads that execute blocking services. The technique combines the blocking and non-blocking services within a single coherent extended programming environment. The messaging kernel (MK) operates on processors apart from the operating system kernel that are allocated from a predetermined number of logical processors (i.e., hyper-threads) for use by an MK scheduler to schedule the non-blocking services within storage I/O stack as well as allocate a remaining number of logical processors for use by the blocking services. In addition, the technique provides a variation on a synchronization primitive that allows signaling between the two types of services (i.e., non-blocking and blocking) within the extended programming environment.
Thu, 25 Aug 2016 08:00:00 EDTAn image forming apparatus according to the present embodiment includes a main substrate, a sub substrate that is connected to communicate with the main substrate, and a sub device that is connected to communicate with the sub substrate. The main substrate includes a transfer unit configured to memory-transfer a boot program of the sub substrate and device information necessary in a case where the sub device performs an activation process to a memory of the sub substrate, the sub substrate includes a control unit configured to perform the activation process of the sub substrate based on the boot program and a transmission unit configured to transmit the device information to the sub device, and the sub device includes an execution unit configured to execute the activation process of the sub device using the device information transmitted by the transmission unit.
Thu, 25 Aug 2016 08:00:00 EDTProvided is a processor system including: an integer core which reads and processes instructions transmitted from a lower level unit through an external bus and performs an ISR (Interrupt Service Routine) if an interrupt occurs during a process; a data memory which is directly connected to the integer core through no external bus and stores a GPR (General Purpose Register) and an SPR (Special Purpose Register); and a nested vectored interrupt controller (NVIC) which is directly connected to the integer core and the data memory through no external bus, performs backup of the GPR and SPR from the integer core if an interrupt occurs during the process, and controls an interrupt operation in a manner that the backup GPR and SPR are transmitted to the data memory. Since the processor system has a structure where the nested vectored interrupt controller and the data memory are directly connected to the integer core, operations necessary during an interrupt process, that is, operations of push of GPR and push of SPR and operations of pop of GPR and pop of SPR are speedily performed, so that it is possible to improve an interrupt process rate.
Thu, 25 Aug 2016 08:00:00 EDTSystems and methods are provided for detection of device functions asserting a spurious interrupt. An example method includes detecting, by a central processing unit executing an operating system, a spurious hardware interrupt signal from a device function, wherein a plurality of device functions include the device function, determining an Interrupt Request (IRQ) value from the spurious hardware interrupt signal, wherein the plurality of device functions share the IRQ value, and scanning each of the plurality of device functions to determine the device function generated the spurious hardware interrupt signal.
Thu, 25 Aug 2016 08:00:00 EDTIn one embodiment, a method includes defining a hardware feature policy for one or more hardware components of a system; and enabling and/or disabling one or more hardware features of one or more of the hardware components based on the hardware feature policy, where the hardware feature policy comprises instructions to enable and/or disable access to the one or more hardware features based on one or more criteria.
Thu, 25 Aug 2016 08:00:00 EDTA system and method for configuring a virtual computing environment to operate in direct interrupt mode; receiving a triggering event triggering a transition from direct interrupt mode to virtual interrupt mode; copying contents of a physical interrupt queue into a virtual interrupt queue; acknowledging vectors present in the physical interrupt queue; and transitioning the virtual computing environment to virtual interrupt mode. The system includes a processor for performing the steps of the method.
Thu, 25 Aug 2016 08:00:00 EDTA first identification of a series of volumes associated with a virtual disk that is associated with a virtual machine is received. A second identification of the series of volumes associated with the virtual disk is received. An operation associated with the virtual disk may be identified as being interrupted in view of a comparison of the first identification with the second identification. In response to identifying that the operation has been interrupted, a volume from at least one of the first or second identifications may be removed.
Thu, 25 Aug 2016 08:00:00 EDTA line multiplexed UART interface is provided that multiplexes a UART transmit and CTS functions on a transmit pin and that multiplexes a UART receive and RTS functions on a receive pin. In this fashion, the conventional need for an additional RTS pin and an additional CTS pin is obviated such that the line multiplexed UART interface uses just the transmit pin and the receive pin.
Thu, 18 Aug 2016 08:00:00 EDTThe present invention discloses an input/output (I/O) signal processing circuit and processing method. The I/O signal processing circuit includes a level adjustable I/O circuit and an adjustment circuit. The I/O signal processing circuit includes an output driver and/or an input comparator. The output driver transmits an output signal via a signal transmission line according to an output data. The output driver has an adjustable high operation voltage level and an adjustable low operation voltage level, which determine a high level and a low level of the output signal, respectively. The input comparator receives an input signal via the signal transmission line and comparing the input signal with an adjustable reference voltage, so as to generate an input data. The adjustment circuit generates an adjustment signal according to voltage drop related information, to correspondingly adjust the adjustable high and low operation voltage level and/or the adjustable reference voltage.
Thu, 18 Aug 2016 08:00:00 EDTA calibratable communications link includes multiple parallel lines. Calibration is performed at dynamically variable and/or interruptible intervals determined by an automated mechanism. Calibration is preferably initiated responsive to a command generated by an executable software process, which initiates calibration responsive to detection of a probable impending need as indicated by, e.g., temperature change, calibrated parameter drift, error rate, etc. Calibration is also preferably initiated according to probable minimal disruption of device function, as indicated by low activity level. Furthermore, in one aspect calibration may be temporarily suspended to transmit data and then resumed.
Thu, 18 Aug 2016 08:00:00 EDTMethods and structure for devices that implement multiple versions of the Serial Attached Small Computer System Interface (SAS) protocol. One exemplary embodiment comprises a SAS device that includes at least one physical link (PHY) that supports a specified generation of SAS protocols, and at least one PHY that supports a different generation of SAS protocols and that does not support the specified generation of SAS protocols. The SAs device also includes an Input/Output (I/O) processor able to select a PHY to service a SAS connection, based on the generation of SAS protocols supported by the PHY.
Thu, 18 Aug 2016 08:00:00 EDTAn electronic device may include system and serial peripheral interface (SPI) clocks, and a host interface each switchable between active and inactive states, a serial controller coupled to the system clock, and a memory. A slave controller may generate a request active signal based upon a transaction request from a host and causing each of the system clock, SPI clock, and host interface into the active state, store request data in the memory, and switch the host interface to the inactive state based upon the request data being stored. The serial controller may process the request based upon the request active signal, and generate a request complete signal based upon the request being processed. The slave controller may switch the system clock to the inactive state based upon the request complete signal. The SPI clock may be switched to the inactive state based upon the request complete signal.
Thu, 18 Aug 2016 08:00:00 EDTA multiple processor architecture with flexible external input/output interface is provided. In one embodiment, an open flexible processor architecture avionics device comprises: a multiple processor architecture having a primary processor, a secondary processor, a random access memory (RAM) coupled to at least the secondary processor, and a shared memory coupled to the primary and secondary processor; and a flexible input/output (I/O) interface coupled to the multiple processor architecture, wherein the flexible I/O interface provides I/O access to the primary processor using a fixed I/O protocol, and provides I/O access to the secondary processor using at least one re-configurable I/O protocol; wherein the primary processor is dedicated to executing embedded software for implementing a primary base functionality, the primary processor has read and write access to the shared memory, and the primary processor is not reprogrammable; and wherein the secondary processor has read-only access to the shared memory and is programmable.
Thu, 18 Aug 2016 08:00:00 EDTA system on a chip (SoC) can be configured to operate in one of a plurality of modes. In a first mode, the SoC can be operated as a network compute subsystem to provide networking services only. In a second mode, the SoC can be operated as a server compute subsystem to provide compute services only. In a third mode, the SoC can be operated as a network compute subsystem and the server compute subsystem to provide both networking and compute services concurrently.
Thu, 18 Aug 2016 08:00:00 EDTA method of providing information at a channel level is provided. Each component of the channel can be represented by pre-calculated s-parameter matrix. Selection of the components allows the s-parameter matrices to be combined together to form an s-parameter matric representative of the channel. The channel can then be evaluated to determine if it meets desired criteria. Changes to the channel can be quickly evaluated by selecting different components or different configurations of the channel.
Thu, 18 Aug 2016 08:00:00 EDTA semiconductor die assembled in a wafer-level package includes a processing circuit, a multiplexer, and a transmit interface. The processing circuit generates a plurality of signal outputs. The multiplexer multiplexes the signal outputs into a multiplexed signal. The transmit interface transmits the multiplexed signal to another semiconductor die assembled in the wafer-level package.
Thu, 18 Aug 2016 08:00:00 EDTIncluding control data in a serial audio stream is presented herein. A device can include a clock component that is configured to send, via a clock pin of the device, a bit clock signal directed to a slave device. A frame component can send, via a frame pin of the device, a frame clock signal directed to the slave device. A control component can receive, via a data pin of the device during a first portion of a phase of a period of the frame clock signal, slave data from the slave device on a bit-by-bit basis based on the bit clock signal according to an integrated interchip sound (I2S) based protocol; and send, via the data pin during a second portion of the phase after the first portion, a set of control bits directed to the slave device on the bit-by-bit basis based on the bit clock signal.
Thu, 18 Aug 2016 08:00:00 EDTIn one embodiment, a computer-implemented method includes instructing two or more processors that are operating in a normal state of a symmetric multiprocessing (SMP) network to transition from the normal state to a slow state. The two or more processors reduce their frequencies to respective target frequencies in a transitional state when transitioning from the normal state to the slow state. It is determined that the two or more processors have achieved their respective target frequencies for the slow state. The slow state is entered, responsive to this determination. Responsive to entering the slow state, a first processor of the two or more processors is instructed to send empty packets across an interconnect to compensate for a first greatest potential rate differential between the first processor and a remainder of the two or more processors during the slow state.
Thu, 18 Aug 2016 08:00:00 EDTSystems, methods, circuits and computer-readable mediums for managing single-wire communications. In one aspect, a method includes starting a transmission cycle by transmitting a clock pulse to a single-wire bus, sampling a data bit transmitted from a single-wire device through the single-wire bus within the transmission cycle after the transmission of the clock pulse, and determining whether a sampling period of the sampling is smaller than a sampling threshold for the data bit. In response to determining that the sampling period is not smaller than the sampling threshold, the method further includes determining that the transmitted data bit is an invalid data bit, and in response: transmitting a high logic voltage level pulse to the single-wire bus for timeout and restarting the transmission cycle for retransmission of the data bit.
Thu, 18 Aug 2016 08:00:00 EDTSystems, methods, circuits and computer-readable mediums for adaptive speed single-wire communications. In one aspect, a method includes receiving a sensing signal from a device through a single-wire bus, analyzing one or more properties of the received sensing signal, the one or more properties including at least one of a pulse width of the sensing signal and a duration between sequential pulses in the sensing signal, adjusting one or more communication parameters for single-wire communications with the device based on the analyzed one or more properties, and transmitting a specific signal to the device through the single-wire bus at an adjusted transmission speed based on the adjusted one or more communication parameters.
Thu, 18 Aug 2016 08:00:00 EDTA data acquisition system includes an electronic device and a data acquisition terminal. The electronic device includes a data storage section and a first interface. The data acquisition terminal includes a terminal communication control section and a second interface to be connected to the first interface. The terminal communication control section instructs the electronic device to transmit data stored in the data storage section of the electronic device through the first interface. In response to an instruction from the terminal communication control section, the electronic device transmits the data stored in the data storage section to the data acquisition terminal by a predetermined communication scheme. The predetermined communication scheme is a communication scheme that uses a communication standard prescribed in a layer lower than an application layer in an open systems interconnection reference model.
Thu, 18 Aug 2016 08:00:00 EDTA semiconductor die assembled in a wafer-level package includes a communication interface and a bus master. The bus master is coupled to a communication bus through the communication interface. The bus master communicates with a bus slave of another semiconductor die assembled in the wafer-level package via the communication bus, and is controlled by a flow control mechanism that manages a transaction flow initiated by the bus master over the communication bus.
Thu, 18 Aug 2016 08:00:00 EDTEmbodiments of the technology can provide steering of one or more I/O resources to compute subsystems on a system-on chip (SoC). The SoC may include a first I/O subsystem comprising a plurality of first I/O resources and a second I/O subsystem comprising a plurality of second I/O resources. A steering engine may steer at least one of the first I/O resources to either a network compute subsystem or to a server compute subsystem and may steer at least one of the second I/O resources to either the network compute subsystem or to the server compute subsystem.
Thu, 18 Aug 2016 08:00:00 EDTA wafer-level package has a first die and a second die. The first die has a first clock source arranged to generate a first clock, a first sub-system arranged to generate transmit data, and an output circuit arranged to output the transmit data according to the first clock. The second die has a second sub-system, a second clock source arranged to generate a second clock, and an input circuit having an asynchronous first-in first-out (FIFO) buffer. The input circuit buffers the transmit data transferred from the output circuit in the asynchronous FIFO buffer according to the first clock, and outputs the buffered transmit data in the asynchronous FIFO buffer to the second sub-system according to the second clock.
Thu, 18 Aug 2016 08:00:00 EDTA direct memory access (DMA) controller issues a standby request a predetermined period of time before data transfer having a high priority starts and prohibits data transfer having a low priority in advance, and thus data transfer having a high priority can generate a transfer cycle from a data transfer start point in time without waiting. Accordingly, a transfer time is reduced, a variation in the transfer time is reduced, and thus a real time property of a system is improved.
Thu, 18 Aug 2016 08:00:00 EDTSystems, methods, and computer programs are disclosed for scheduling volatile memory maintenance events. One embodiment is a method comprising: a memory controller determining a time-of-service (ToS) window for executing a maintenance event for a volatile memory device coupled to the memory controller via a memory data interface; the memory controller providing a signal to each of a plurality of processors on a system on chip (SoC) for scheduling the maintenance event; each of the plurality of processors independently generating in response to the signal a corresponding schedule notification for the maintenance event; and the memory controller determining when to execute the maintenance event in response to receiving one or more of the schedule notifications generated by the plurality of processors and based on a processor priority scheme.
Thu, 18 Aug 2016 08:00:00 EDTSystems, methods, and computer programs are disclosed for scheduling volatile memory maintenance events. One embodiment is a method comprising: a memory controller determining a time-of-service (ToS) window for executing a maintenance event for a volatile memory device coupled to the memory controller via a memory data interface; the memory controller providing an interrupt signal to a processing unit; determining a priority for the maintenance event; and scheduling the maintenance event according to the priority.
Thu, 18 Aug 2016 08:00:00 EDTA device includes a routing buffer. The routing buffer includes a first port configured to receive a signal relating to an analysis of at least a portion of a data stream. The routing buffer also includes a second port configured to selectively provide the signal to a first routing line of a block of a state machine at a first time. The routing buffer further includes a third port configured to selectively provide the signal to a second routing line of the block of the state machine at the first time.
Thu, 18 Aug 2016 08:00:00 EDTA method and system for transferring data over a plurality of control lines includes receiving, by a first device, a command from a host device to transfer the data from the first device to a second device; and independently transmitting, by the first device, the data to the second device based on the command, where the data is independently transferred using the plurality of control lines. The method further includes transferring of the data from the first device to the second device performed independent of the host device; and sending, by the first device, a data transfer completion message to the host device.
Thu, 11 Aug 2016 08:00:00 EDTA transceiver circuit for operating in a controller area network (CAN), having a CAN bus network and a control unit, that supports a flexible data rate (CAN FD), is described. The transceiver circuit comprises: a transmit CAN path and a receive CAN path; an input node on the transmit CAN path; a detection module operably coupled to the input node on the transmit CAN path and arranged to receive an input frame from the control unit before the input frame is transmitted on the CAN bus network and determine whether the input frame on the transmit CAN path comprises a CAN FD frame; and at least one switching module, operably coupled to the detection module and coupleable to the CAN bus network, where the at least one switching module is operable to impart a first voltage value on the CAN bus network in response to the input frame being determined as comprising a CAN FD frame.
Thu, 11 Aug 2016 08:00:00 EDTAn electronic component, a semiconductor package, and an electronic device including the electronic component and/or the semiconductor package are provided. The electronic component includes an electronic element; an encapsulation member that encapsulates the electronic element and has a first surface and a second surface substantially parallel to each other; and a lead electrically connected to the electronic element and extending outward from the encapsulation member. The lead is disposed entirely in a region between a plane of the first surface of the encapsulation member and a plane of the second surface of the encapsulation member.
Thu, 11 Aug 2016 08:00:00 EDTMethods and apparatus for enabling rapid transactions over a speed limited bus are disclosed. In one exemplary embodiment of the present disclosure, a host controller and an application specific integrated circuit (ASIC) are connected via an Inter-Integrated Circuit (I2C) Bus that is further adapted to enable a simplified signaling scheme. Unlike traditional I2C bus transactions which are flexible but speed limited, the simplified signaling scheme reduces bus overhead and enables rapid transactions. In an exemplary context, the simplified signaling scheme enables the ASIC to rapidly configure a series of photodiodes with different channel gain parameters so as to, for example, measure heartbeats by visually detecting a pulse within human flesh.
Thu, 11 Aug 2016 08:00:00 EDTA reconfigurable register device includes an arrangement of storage elements arranged sequentially in a chain structure. Each storage element stores a state of a binary signal. A combinatorial logic circuitry connectable to the arrangement of storage elements enables the arrangement of storage elements to form a binary synchronous counter. A bypass logic circuitry connectable to the arrangement of storage elements enables the arrangement of storage elements to form a serial shift register. A switching circuitry has a mode signal input terminal receiving a mode signal indicative of at least one of a counter mode and a shift register mode. The switching circuitry is configured to connect the arrangement of storage elements to the combinatory logic circuitry if the mode signal indicates the counter mode, and to connect the arrangement of storage elements to the bypass logic circuitry if the mode signal indicates the shift register mode.
Thu, 11 Aug 2016 08:00:00 EDTEmbodiment of present disclosure relates to a Universal Serial Bus (USB) hub for switching downstream ports between host mode and slave mode comprising upstream port connectable to host port of host, downstream port and switching module. The downstream port is connectable to device port of peripheral device and acts in host mode and said device port acts in slave mode. The switching module comprises master port, switching port and control unit. The master port is connectable to upstream port. The switching port is connectable to other end of downstream port, the switching port acts in host mode. The control unit receives switch command from host to switch downstream port from host mode to slave mode; switches switching port to slave mode and enables downstream port to act in the slave mode when host emulates functionality of slave mode as required by peripheral device using vendor specific USB class.
Thu, 11 Aug 2016 08:00:00 EDTAn apparatus, including a case having a front panel, and multiple transceiver modules mounted on the front panel. The apparatus also includes at least one midplane adapter card having a first connector configured to transport networking signals, and a second connector configured to transport bus signals. The apparatus additionally includes a switch input/output board mounted within the case, coupled to the multiple transceiver modules, and having multiple first slots configured to accept the first connectors, and networking switch circuitry coupled to the first slots and configured to establish a network connection between two or more of the transceiver modules. The apparatus further includes a motherboard mounted within the case, and having a bus with multiple second slots configured to accept the second connectors, and a processor configured to manage the networking switch circuitry and to receive and process data commands in response to communications received from the transceiver modules.
Thu, 11 Aug 2016 08:00:00 EDTA reading apparatus suited for being inserted into a first electronic device or a second electronic device is disclosed. The first electronic device has a first interface receptacle. The second electronic device has a second interface receptacle. The reading apparatus has a first interface-module and a second interface-module. The first interface-module comprises a plurality of pins corresponding to the first interface receptacle and used to transmit a first interface signal. The pins comprise a plurality of first pins which are disposed on a top surface of a circuit board, and comprises a first positive-negative direction determining pin which is used to confirm whether the first interface-module is positively inserted or negatively inserted into and the first interface receptacle. The second interface-module comprises a plurality of conduction pad corresponding to the second interface receptacle and used to transmit a second interface signal.
Thu, 11 Aug 2016 08:00:00 EDTAt least one Universal Serial Bus (USB) device is coupled to shared memory. The memory is accessible via the at least one USB interface wherein the memory is configured to be shared between the at least one USB device, the memory configured with a memory arbiter, wherein the memory arbiter decides which of the at least one USB device can access a read-write memory space of the memory during a time period.
Thu, 11 Aug 2016 08:00:00 EDTA subscriber station for a bus system and a method for time-optimized data transmission in a bus system are provided. The subscriber station comprises a coding device for coding and/or decoding bits of a message to/from at least one further subscriber station of the bus system, in which at least temporarily an exclusive, collision-free access of a subscriber station to a bus line of the bus system is ensured, wherein the coding device is designed to allocate, during the coding of the message, to at least two bits as bit combination, a predetermined voltage level for a bit time and/or wherein the coding device is designed to allocate, during the decoding of the message, at least two bits as bit combination to a predetermined voltage level for a bit time.