Thu, 23 Feb 2017 08:00:00 ESTA packet data processing method, apparatus, and system. The method is executed by a first processing apparatus, and includes: acquiring packet data that needs to be processed, where the packet data that needs to be processed includes first packet data information and second packet data, and the first packet data information includes a header of the packet data that needs to be processed and a storage address of the packet data that needs to be processed in the first processing apparatus; sending the first packet data information to a second processing apparatus; and receiving first packet data information (includes an updated header after being processed and the storage address) processed by the second processing apparatus, and generating finished packet data using the first packet data information processed by the second processing apparatus and the second packet data.
Thu, 23 Feb 2017 08:00:00 ESTThe disclosure provides a PCI Express Scaled Port, a computing device and a method of communicating between PCI Express components. In one embodiment, the PCI Express Scaled Port includes: (1) an interface configured to communicate flow control negotiating packets with another PCI Express Port and (2) a FCC Controller configured to generate the flow control negotiating packets, wherein the flow control negotiating packets include a flow control credit for PCI Express packets and a scaling factor for the flow control credit.
Thu, 23 Feb 2017 08:00:00 ESTMethods and apparatuses relating to balanced transmittal of data are described. In one embodiment, an apparatus includes an encoder to encode input data into at least one data group with each data group having an equal number of a first level signal and a second, lower level signal to transmit the at least one data group over single conductors in parallel, and a decoder to decode the at least one data group into output data. In another embodiment, a method includes encoding input data with an encoder into at least one data group with each data group having an equal number of a first level signal and a second, lower level signal to transmit the at least one data group over single conductors in parallel, and decoding the at least one data group into output data with a decoder.
Thu, 23 Feb 2017 08:00:00 ESTComputing devices are often designed in view of a particular usage scenario, but may be unsuitable for usage in other computing scenarios. For example, a notebook computer with a large display, an integrated keyboard, and a high-performance processor suitable for many computing tasks may be heavy, large, and power-inefficient; and a tablet lacking a keyboard and incorporating a low-powered processor may improve portability but may present inadequate performance for many tasks. Presented herein is a configuration of a computing device featuring a display unit with a resource-conserving processor that may be used independently (e.g., as a tablet), but that may be connected to a base unit featuring a resource-intensive processor. The operating system of the device may accordingly transition between a resource-intensive computing environment and a resource-conserving computing environment based on the connection with the base unit, thereby satisfying the dual roles of workstation and portable tablet device.
Thu, 23 Feb 2017 08:00:00 ESTAn active input/output connector includes a first printed circuit board and a second printed circuit board enclosed within a housing. A first plug is in electronic communication with the first printed circuit board. A second plug is in electronic communication with the second printed circuit board. The first and second printed circuit boards are connected for communication of sensor signals from the first plug to the second plug.
Thu, 23 Feb 2017 08:00:00 ESTVarious computing systems may benefit from appropriate configuration and/or adaptation. For example, various computing systems operating in accordance with Open VPX may benefit from systems and methods for providing Open VPX profile configurators. An apparatus can include a first interface configured to connect to a backplane operable according to an open VPX specification, wherein the backplane has a first profile. The apparatus can also include a second interface configured to connect to a module operable according to the open VPX specification, wherein the module has a second profile. The apparatus can further include circuitry configured to permit communication between the first interface and the second interface according to the open VPX specification. The circuitry can be configurable to adapt the module to communicate with the backplane when the first profile does not match the second profile.
Thu, 23 Feb 2017 08:00:00 ESTAn example device in accordance with an aspect of the present disclosure includes at least one interface set, including a first interface, at least one second interface, and at least one third interface. A first portion of the first interface is coupled to a second portion of the at least one second interface. A second portion of the first interface is coupled to a first portion of the at least one third interface. The first portion of the first interface is isolated from the second portion of the first interface, the first portion of the second interface is isolated from the second portion of the second interface, and the first portion of the third interface is isolated from the second portion of the third interface.
Thu, 23 Feb 2017 08:00:00 ESTA method (700) for reconfiguring pin assignments on a connector (100) is provided. The method (700) includes reading a present accessory type (34a) from an accessory (30) coupled to the connector (100) having a plurality of pins (110) wherein the present accessory type (34a) is associated with an accessory pin assignment (31) of the connector (100), and comparing the present accessory type (34a) to a stored accessory type (18a) associated with a connector pin assignment (17) to determine if the accessory pin assignment (31) is compatible with the connector pin assignment (17).
Thu, 23 Feb 2017 08:00:00 ESTA storage system includes a holder, and a plurality of storage devices arranged along a line in the holder, each of the storage devices including first and second connection interfaces. Each of the first connection interfaces is electrically connected to a second connection interface of another storage device and each of the second connection interfaces is electrically connected to a first connection interface of another storage device, such that an electrical loop connection is formed through the plurality of the storage devices.
Thu, 23 Feb 2017 08:00:00 ESTA host connected to a switch using a PCI Express (PCIe) link. At the switch, the packets are received and routed as appropriate and provided to a conventional switch network port for egress. The conventional networking hardware on the host is substantially moved to the port at the switch, with various software portions retained as a driver on the host. This saves cost and space and reduces latency significantly. As networking protocols have multiple threads or flows, these flows can correlate to PCIe queues, easing QoS handling. The data provided over the PCIe link is essentially just the payload of the packet, so sending the packet from the switch as a different protocol just requires doing the protocol specific wrapping. In some embodiments, this use of different protocols can be done dynamically, allowing the bandwidth of the PCIe link to be shared between various protocols.
Thu, 23 Feb 2017 08:00:00 ESTA data acquisition system includes a receptacle and a data acquisition device. The receptacle has a housing, sensor inputs to receive data signals from sensors coupled to an object, and a rib to block insertion of a standard Universal Serial Bus (USB) plug and facilitate insertion of a modified USB plug having a slot that mates with the rib. The data acquisition device includes circuitry to receive, store and process data, a USB plug having pins operatively coupled to the circuitry, a first subset of pins configured to receive data signals from the receptacle and a second subset of pins configured to support standard USB communication with USB-compliant devices, and a slot formed in the USB plug such that the slot facilitates interconnection of the USB plug both with standard USB-compliant devices and with the receptacle, the slot mating with the rib to facilitate interconnection.
Thu, 23 Feb 2017 08:00:00 ESTA network interface controller includes a media access controller connected to receive an in-band packet and further connected to receive a sideband packet. The network interface controller includes a host adapter that includes a receive route connected to receive the in-band packet and the sideband packet from the media access controller, and further connected to transmit the in-band packet to a host. The network interface controller includes a sideband port controller comprising a sideband receive buffer. The host adapter further includes a first receive buffer to store the in-band packet and to store the sideband packet. The host adapter further includes an arbiter connected to allow, at a time, the in-band packet to advance from the first receive buffer along the receive route towards the host and further connected to allow, at a different time, the sideband packet to advance to the sideband receive buffer of the sideband port controller.
Thu, 23 Feb 2017 08:00:00 ESTA network interface controller includes a media access controller and a host adapter. The host adapter includes a transmit route connected to receive an in-band packet from a host and further connected to transmit the in-band packet to the media access controller. The network interface controller also includes a sideband port controller connected to receive a sideband packet destined for a network from a sideband endpoint and further connected to transmit the sideband packet to the host adapter. The host adapter further includes a host buffer to store the in-band packet, a sideband buffer to store the sideband packet, and an arbiter connected to allow, at different times, the in-band packet to advance along the transmit route from the host buffer to the media access controller and the sideband packet to advance along the transmit route from the sideband buffer to the media access controller.
Thu, 23 Feb 2017 08:00:00 ESTA paired queue apparatus and method comprising request and response queues wherein queue head and tail pointer update values are communicated through an enhanced pointer word data format providing pointer indicator information and optional auxiliary information in a single transfer, wherein auxiliary information provides additional system communication without consuming additional bandwidth. Auxiliary information is optionally contained in a response data entry written to a response queue or in a request entry written to a request queue.
Thu, 23 Feb 2017 08:00:00 ESTA mobile system includes a first interface configured to transmit a payload in synchronization with a first clock signal through a first channel at a first transfer rate; and a second interface that includes: a payload storage connected to the first channel and configured to receive the payload from the first channel; and a payload receiver connected to the payload storage and configured to receive the payload from the payload storage in synchronization with a second clock at a second transfer rate through a second channel. A length of the second channel is shorter than a length of the first channel, and the first clock signal is asynchronous with the second clock signal.
Thu, 23 Feb 2017 08:00:00 ESTSynchronization of effects across multiple devices using local, distributed control, and eliminating the need for central direction of the effects with the associated large bandwidth required. In one embodiment, each device stores data and instructions for creating its own effects. The devices periodically communicate with a host or each other to maintain synchronization, and compensate for any drift. This approach minimizes the use of bandwidth and battery power in the devices.
Thu, 23 Feb 2017 08:00:00 ESTA utilizing function apparatus include at least one processor, and a memory storing instructions that, when executed by the at least one processor, causes the at least one processor to, based on an operation, set one of at least one function temporarily unable to be executed, when it is detected that the utilizing function apparatus is connected to an external device after setting the one function temporarily unable to be executed, acquire information about an area of the memory of the utilizing function apparatus, as first information, when it is detected that the connection with the external device is released, acquire the information about the area of the memory, as second information, and when the acquired first information and second information are different, set the one function back able to be executed.
Thu, 23 Feb 2017 08:00:00 ESTIn an approach to automatic connection detection in an environment, the environment including a first device and a switching device, a first port on the first device being connected to a second port on the switching device, automatic connection detection occurs by associating a fifth port on the switching device to the second port. In response to detecting an identifier of a sixth port on a third device at the first port on the first device, it's determined that the sixth port on the third device is connected to the fifth port.
Thu, 23 Feb 2017 08:00:00 ESTA method includes providing device management services to by defining one or more transaction control primitives and one or more transaction initiation commands for modifying a management tree of a managed device, mapping the transaction control primitives and transaction initiation commands to device management commands for the managed device, transmitting the device management commands to the managed device, determining a relevance of any of the transmitted device management commands that fail to execute, and based on the relevance determination, allowing the managed device to modify the management tree without executing the commands that fail to execute.
Thu, 23 Feb 2017 08:00:00 ESTA multi-node computer system, comprising: a plurality of nodes, a system control unit and a carrier board. Each node of the plurality of nodes comprises a processor and a memory. The system control unit is responsible for: power management, cooling, workload provisioning, native storage servicing, and I/O. The carrier board comprises a system fabric and a plurality of electrical connections. The electrical connections provide the plurality of nodes with power, management controls, system connectivity between the system control unit and the plurality of nodes, and an external network connection to a user infrastructure. The system control unit and the carrier board provide integrated, shared resources for the plurality of nodes. The multi-node computer system is provided in a single enclosure.
Thu, 23 Feb 2017 08:00:00 ESTAn electronic apparatus that is capable of checking connection between the electronic apparatus body and accessories without performing communication between the electronic apparatus body and accessories. The electronic apparatus is capable of communicating with an accessory device connected. A detection unit detects whether the accessory device supports both a first communication method and a second communication method of which communication speed is higher than communication speed of the first communication method. A setting unit sets the second communication method during communication when the detection unit detects that the accessory device supports both the first communication method and the second communication method, and to set the first communication method except communicating.
Thu, 23 Feb 2017 08:00:00 ESTTechniques for low-power USB Type-C receivers with high DC-level shift tolerance and high noise rejection are described herein. In an example embodiment, a USB-enabled device comprises a receiver circuit coupled to a Configuration Channel (CC) line of a USB Type-C subsystem. The receiver circuit is configured to receive data from an incoming signal on the CC line even when the incoming signal has more than 250 mV of DC offset with respect to local ground, and to reject the incoming signal even when the incoming signal includes noise with a magnitude of more than 300 mVpp.
Thu, 16 Feb 2017 08:00:00 ESTThe instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.
Thu, 16 Feb 2017 08:00:00 ESTThe present invention provides method and associated interface circuit for mitigating interference due to signaling of a bus between two electronic apparatuses. The method may include: via the bus mechanically compliant to a bus specification, communicating and transporting data at a nonstandard speed which is not compliant to the bus specification. The method may further include: before communicating and transporting data at the nonstandard speed, signaling via the bus at a standard speed to configure a speed switching from the standard speed to the nonstandard speed, with the standard speed compliant to the bus specification. For example, the bus specification may be USB specification, the standard speed may be 5 Gbps (SuperSpeed of USB 3.0 specification), and the nonstandard speed may be lower than the standard speed, e.g., 2.5 Gbps, which forms a spectrum notch at a frequency of wireless connection, e.g., 2.4 GHz of Wi-Fi.
Thu, 16 Feb 2017 08:00:00 ESTData transfer between a data storage device and a peripheral device bypasses an application processor that is coupled to the data storage device and to the peripheral device. In one embodiment, the data storage device includes a memory controller configured to receive, from an application processor, a message indicating a set of logical addresses and a data transfer identifier corresponding to the set of logical addresses. The memory controller is responsive to a request for memory access that includes the data transfer identifier and that is received from a peripheral device. The memory controller is configured to respond to the request by performing a memory access operation based on the set of logical addresses.
Thu, 16 Feb 2017 08:00:00 ESTEHF communication systems described herein can selectively implement any one of the USB standards by mapping appropriate USB signal conditions over an EHF contactless communication link. The EHF contactless communication link may serve as an alternative to conventional board-to-board and device-to-device connectors, and as such enables wired connection USB signaling protocols to be used in a non-wired environment provided by the EHF contactless communications link. Use of a USB protocol over the EHF communications link can be accomplished by establishing the EHF link between counterpart EHF communication units, and then by establishing the appropriate USB protocol over the link.
Thu, 16 Feb 2017 08:00:00 ESTAn asynchronous first-in first-out (AFIFO) buffer apparatus has an AFIFO buffer and a rate control circuit. The AFIFO buffer receives a data input from a first processing circuit operating under a first clock, and transmits a data output to a second processing circuit operating under a second clock, where the first clock is asynchronous to the second clock. The rate control circuit actively controls a data transfer rate of the data input regardless of a water level of the AFIFO buffer, and further adaptively applies compensation to the data transfer rate according to the water level of the AFIFO buffer.
Thu, 16 Feb 2017 08:00:00 ESTA Thunderbolt sharing console includes a high speed switch electrically coupled to at least one Thunderbolt host, a MCU coupled to the high speed switch, and a Thunderbolt interface chip coupled to the high speed switch, wherein the MCU can be used to control the high speed switch for determining which one of the at least one Thunderbolt host is coupled to the Thunderbolt interface chip.
Thu, 16 Feb 2017 08:00:00 ESTEmbodiments of the present invention disclose a data processing apparatus. Output ends of an input switching module in the apparatus are respectively connected to input ends of cache units included in a cache module; a control end of a write arbiter is connected to a control end of the input switching module; Input ends of an output switching module are respectively connected to output ends of the cache units; Output ends of the output switching module are respectively connected to input ends of a rearranger; a control end of a read arbiter is connected to a control end of the output switching module; and output ends of the rearranger are respectively connected to output ends of the data processing apparatus.
Thu, 16 Feb 2017 08:00:00 ESTThe present disclosure provides a method and system for dynamically migrating a port in a PCIe switch. The PCIe switch comprises emulated P2P bridges stored in a memory and a processor to load the emulated P2P bridge address range values from the memory to a routing table. The processor can configure the routing table so that the P2P bridges can be remapped to various physical ports of the switch. Therefore, a device connected to a physical port may be migrated from one host to another, via the operations of the processor.
Thu, 16 Feb 2017 08:00:00 ESTAn information processing apparatus includes a first bus interface to receive first data transferred in a pixel-parallel transfer mode, a second bus interface to receive second data transferred in a line-parallel transfer mode, a selector to select one of the first data transferred in the pixel-parallel transfer mode and the second data transferred in the line-parallel transfer mode, as input data, a transfer switching circuit to switch between the line-parallel transfer mode and the pixel-parallel transfer mode to process the input data according to the switched transfer mode.
Thu, 16 Feb 2017 08:00:00 ESTSystems and methods for analyzing a PCIe network using a graph-theory based analysis are disclosed. A management CPU is coupled to the root complex of the PCIe system and is operable to survey potential CPU-resource combinations in a PCIe system and assign a group of PCIe resources to a CPU. A first switch and a second switch are coupled to the root node, and a first CPU and a first group of PCIe resources are coupled to the first switch. The management CPU assigns a group of PCIe resources to a CPU based on the isolation of the first and second CPUs or a distance between the first and second CPUs and the groups of PCIe resources. According to some embodiments, for potential pairs of devices and NTB/CPUs, the distance between components is assessed, possible alternative paths are identified, and the isolation of the pair is determined.
Thu, 16 Feb 2017 08:00:00 ESTThis invention relates to a dynamically addressable master-slave system and a method for dynamic addressing of slave units, wherein a master unit and a plurality of slave units are provided and the slave units are connected to the master unit via a bus system and can receive at least one broadcast command from the master unit via the bus line of the bus system, wherein the master-slave system is configured such that the master unit can send respective broadcast commands to the slave units, on the one hand, for activation, and on the other hand, for performing the dynamic addressing process of slave addresses, and wherein the slave units each comprise an address input and an address output and are serially connected via an address line that is separate from the bus line.
Thu, 16 Feb 2017 08:00:00 ESTA system according to one embodiment includes at least two socket servers each having a plurality of sockets, each socket being configured to receive a processor, and a plurality of adapters coupled to the serial computer expansion buses, the adapters being configured to enable communication between the processors of different ones of the socket servers. Each of the socket servers have at least one serial computer expansion bus coupled to each of the sockets thereof.
Thu, 16 Feb 2017 08:00:00 ESTA universal serial bus (USB) device is provided for storing a digital coin. The USB device includes an electronic media for storing a digital coin, a USB male port connected to the electronic media; and circuitry to erase bits of the digital coin from the electronic media as the bits are sent from the USB male port.
Thu, 16 Feb 2017 08:00:00 ESTBoardroom table systems are provided that include a plurality of USB Type-C receptacles that can provide power and/or data transfer functionality to one or more devices attached thereto. Power transferred by the boardroom table system may be managed by USB Power Delivery, and may come from a source of wall power, or from a device coupled to one of the USB Type-C receptacles. Data transferred by the boardroom table system may include USB data, Ethernet data, video data, and/or any other type of data transmittable via a USB Type-C receptacle. In some embodiments, boardroom table systems also include presentation devices. In such embodiments, a device coupled to a USB Type-C receptacle could both transmit or receive power, exchange data, and transmit video to the presentation device via the same USB Type-C receptacle of the boardroom table system, thus eliminating the need for multiple sockets and cables.
Thu, 16 Feb 2017 08:00:00 ESTA method of profiling transactions on an integrated circuit chip. The method comprises, for each transaction: extracting the transaction from interconnect circuitry of the integrated circuit chip; and filtering the transaction at a filtering circuit to determine which passband a parameter of the transaction lies within; sending an increment signal to a counter of a bank of counters, the counter having a counter value indicative of a number of transactions having the parameter lying within the passband; and outputting the counter values of the bank of counters.
Thu, 16 Feb 2017 08:00:00 ESTRealized are a switch on/off control method and a switch circuit that can reduce a processing load when controlling on/off of a switch whose various operations are controlled based on control data. All commands in a command table included in a RAM are DMA-transferred to an SPI controller, and the DMA-transferred commands are transmitted to an IPD via SPI communication, so as to perform on/off control. DIAG commands irrelevant to the on/off control of the IPD are written in advance in the entire region of the command table, transfer source addresses from which the commands are DMA-transferred to the IPD at phases at which the IPD is to be controlled to be turned on and off are calculated, and an ON command and an OFF command for controlling the IPD to be turned on and off are written over the diagnosis commands that were written in advance at the calculated transfer source addresses.
Thu, 16 Feb 2017 08:00:00 ESTAccording to one embodiment, an interface of a memory system includes a circuit configured to adjust output resistance for data output. When the circuit has received a command in a second state, the circuit adjusts output resistance during a first period. The first period is a period from when the interface completes reception of the command to when the interface starts transmission of data read from the memory. The second state is a state in which power consumption is lower than that in a first state in which operation is caused by a command.
Thu, 16 Feb 2017 08:00:00 ESTAccording to one embodiment, an apparatus comprises one or more memory devices and one or more processors coupled to a circuit board. The memory devices are configured according to a second memory technology. The processors are configured to receive messages conforming to a first memory technology, translate the messages from the first memory technology to the second memory technology, and send the translated messages to the memory devices.
Thu, 16 Feb 2017 08:00:00 ESTAn apparatus, shipping container, and system for in-package storing of data for an electronic device are disclosed. In one example, the apparatus comprises an electronic device that has a housing and is packaged in a shipping container that substantially encloses the electronic device. The housing includes a first communication interface and the shipping container includes a second communication interface. The second communication interface is in electrical communication with the first communication interface such that power and data signals can be communicated via the first and second communication interfaces between the electronic device and another electronic device located outside the shipping container.
Thu, 16 Feb 2017 08:00:00 ESTA diagnostic method of diagnosing a type of a field device, includes: setting a plurality of connection units included in an I/O module to be in a state of being capable of inputting or outputting a hybrid signal which is an analog signal having a digital signal superimposed thereon, the connection units being connected to the field device and capable of inputting the hybrid signal, outputting the hybrid signal, inputting a digital signal, and outputting a digital signal; and diagnosing the type of the field device which is connected to the connection units of the I/O module, based on the digital signal included in the hybrid signal obtained through the connection units.
Thu, 16 Feb 2017 08:00:00 ESTA control method and a control device are provided. A router receives data sent by a first device, where the data carries an identifier of an input/output (I/O) device, determines, according to the identifier of the I/O device and a correspondence between the I/O device and a controller, a controller corresponding to the identifier of the I/O device, sends the data to the controller corresponding to the identifier of the I/O device such that the controller processes the data according to firmware code stored in the controller, receives the processed data sent by the controller, and sends the processed data to a second device, where the second device or the first device is the I/O device. The firmware code is generally programmable, and therefore a control device applying the foregoing control method can be relatively flexibly implemented.
Thu, 16 Feb 2017 08:00:00 ESTExamples relate to extending hardware support for sensors embedded in peripherals. In some examples, a driver is used to determine that a peripheral device includes a sensor in response to the peripheral device being attached to a mobile computing device, where the driver is preloaded in an operating system kernel of the mobile computing device. Next, a list of supported hardware features is updated to include a peripheral hardware feature that is provided by a sensor of the peripheral device, and the list of supported hardware features is sent to an application store server. At this stage, a list of available applications that are compatible with the list of supported hardware features is received from the application store server.
Thu, 16 Feb 2017 08:00:00 ESTTechniques to determine an adjustment to front end bandwidth of a server based on backend bandwidth and to adjust power consumption of an input/output (I/O) device.
Thu, 09 Feb 2017 08:00:00 ESTA peripheral device capable of being worn, carried by a user, or used in an in-vehicle computer system operates in conjunction with an application to acquire, store, and present data relevant to a user's health, physical activity, environment, air quality, or other parameters of interest. For power efficient operation and enhanced performance, control parameters of the peripheral device such as duty cycle, sampling rate, and sleep state may be wirelessly and automatically controlled by the mobile device. Furthermore, the mobile application can provide a wireless energy signal to the peripheral device to recharge the battery of the peripheral device. The control parameters may be automatically controlled by the mobile application dependent on the user's location, activity, mode of transportation or other parameters without intervention from a user.
Thu, 09 Feb 2017 08:00:00 ESTIn one embodiment, an apparatus comprises a processor core and a power control unit. The power control unit is to identify the occurrence of a power loss from a primary power source, instruct the I/O controller to block further write requests from the one or more I/O devices and to send at least one pending write request stored by the I/O controller to the memory controller, and instruct the memory controller to complete at least one pending write request stored by the memory controller and to cause the memory to be placed into a self-refresh mode.
Thu, 09 Feb 2017 08:00:00 ESTAn apparatus comprising a plurality of physical IO ports configured to couple to a plurality of remote LCs that provide IO resources, and a processor coupled to the plurality of physical IO ports and configured to map the remote LCs to a plurality of vNICs by allocating at least some of the IO resources to the local vNICs, receive an OS kernel IO call comprising a request to access a first of the vNICs, determine a first of the remote LCs that corresponds to the first vNIC, and direct the request to access the first remote LC.
Thu, 09 Feb 2017 08:00:00 ESTApparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. One method includes providing a plurality of launch clock signals, including launch clock signals having a different phase shifts, determining a type of transition in signaling state that will occur on each wire of the 3-wire interface at a boundary between two consecutively transmitted symbols, and selecting one of the plurality of launch clock signals to initiate the transition of signaling state on each wire of the 3-phase interface. Selecting one of the plurality of launch clock signals may include selecting a first launch clock signal when the transition in signaling state terminates at an undriven state, and selecting a second launch clock signal when the transition in signaling state begins at an undriven state. An edge in the first launch clock signal may occur before a corresponding edge in the second launch clock signal.
Thu, 09 Feb 2017 08:00:00 ESTA hybrid virtual general purpose input/output (VGI) architecture is provided including a pair of devices coupled through a high-speed cable. The architecture enables a device to communicate sideband signals through the high-speed cable using two pins coupled to respective interconnects of a bus. In an aspect, the architecture may implement link selection without protocol consolidation where the device may configure the two pins for I2C (or I3C) signaling or VGI signaling. In another aspect, the architecture may implement link bridging with protocol consolidation where the device may transmit (or receive) I2C (or I3C) signals through the high-speed cable using a VGI communication protocol.