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ASYNCHRONOUS TRANSCEIVER FOR ON-VEHICLE ELECTRONIC DEVICE

Thu, 27 Oct 2016 08:00:00 EDT

An on-vehicle electronic device has a generating unit configured to generate a first clock for data communication with another on-vehicle electronic device through a CXPI communication network; and an adjusting unit configured to adjust a duty width of the first clock.



Photonics-Optimized Processor System

Thu, 27 Oct 2016 08:00:00 EDT

A photonics-optimized multi-processor system may include a plurality of processor chips, each of the processor chips comprising at least one input/output (I/O) component. The multi-processor system may also include first and second photonic components. The at least one I/O component of at least one of the processor chips may be configured to directly drive the first photonic component and receive a signal from the second photonic component. A total latency from any one of the processor chips to data at any global memory location may not be dominated by a round trip speed-of-light propagation delay. A number of the processor chips may be at least 10,000, and the processor chips may be packaged into a total volume of no more than 8 m3. A density of the processor chips may be greater than 1,000 chips per cubic meter.



ALLOCATING VIRTUAL RESOURCES TO ROOT PCI BUS

Thu, 27 Oct 2016 08:00:00 EDT

Systems and methods for allocating virtual resources to a root PCI bus. An example method may comprise: intercepting, by a hypervisor being executed by a processing device of a host computer system, a virtual machine read operation with respect to a certain address range within a Peripheral Component Interconnect (PCI) configuration space; presenting, to a virtual machine running on the host computer system, an identifier of a root PCI bus; presenting, to the virtual machine, a PCI-to-PCI bridge associated with the root PCI bus; presenting, to the virtual machine, a PCI device that is communicatively coupled to a secondary PCI bus, wherein the secondary PCI bus is communicatively coupled to the PCI-to-PCI bridge; receiving, from the virtual machine, an identifier of a resource pool associated with the PCI-to-PCI bridge; associating the resource pool with the root PCI bus; and notifying of the resource pool a guest operating system of the virtual machine.



Photonics-Optimized Processor System

Thu, 27 Oct 2016 08:00:00 EDT

A photonics-optimized multi-processor system may include a plurality of processor chips, each of the processor chips comprising at least one input/output (I/O) component. The multi-processor system may also include first and second photonic components. The at least one I/O component of at least one of the processor chips may be configured to directly drive the first photonic component and receive a signal from the second photonic component. A total latency from any one of the processor chips to data at any global memory location may not be dominated by a round trip speed-of-light propagation delay. A number of the processor chips may be at least 10,000, and the processor chips may be packaged into a total volume of no more than 8 m3. A density of the processor chips may be greater than 1,000 chips per cubic meter.



BUS COMMUNICATIONS WITH MULTI-DEVICE MESSAGING

Thu, 27 Oct 2016 08:00:00 EDT

Methods and systems are described for reading from or writing to a plurality of slave devices connected to a communications bus having a common data line. The slave devices are mapped to a virtual device address and the communication is initiated by the master by signaling a start condition and the virtual device address. Each of the slave devices mapped to the virtual device address identifies a register in that slave device associated with the virtual device address and, in sequence, performs a read or write operation on the bus with regard to its identified register in a respective predetermined time slot within the communication or to a corresponding virtual register address assigned to the slave device previously.



SECURE DIGITAL HOST CONTROLLER VIRTUALIZATION

Thu, 27 Oct 2016 08:00:00 EDT

Described herein are methods and system for virtualization of the secure digital (SD) host controller to enable sharing a SD device among various multiple host processors in a multi-processor computing system. In one implementation the method of sharing a SD device amongst a plurality of hosts of a multi-host computing system comprises detecting the SD device on occurrence of a reset event, receiving an enumeration request, from at least a first host and a second host of the plurality of hosts, to enumerate the SD device with respect to the second host, enumerating the SD device with respect to the second host, and initiating data exchange between the SD device and each of the plurality of hosts.



HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-SELECT SIGNALING MODE

Thu, 27 Oct 2016 08:00:00 EDT

A memory controller and buffers on memory modules each operate in two modes, depending on the type of motherboard through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.



INPUT SYSTEM AND METHOD

Thu, 27 Oct 2016 08:00:00 EDT

An input system includes a communication device and a first input device. The communication device includes a communication chip and a communication port. The first input device includes a signal port connectable with the communication port and a device connecting port connectable with a second input device. In an input method, the communication device transmits a first pairing signal to the first input device so as to acquire a first identification code and a connection information of the first input device, and then the communication device transmits a first inquiring signal containing the first identification code to the first input device so as to acquire a first input signal from the first input device. If a second pairing signal and a second inquiring signal are transmitted to the second input device, the communication device acquires a second input signal from the second input device.



Photonics-Optimized Processor System

Thu, 27 Oct 2016 08:00:00 EDT

A photonics-optimized multi-processor system may include a plurality of processor chips, each of the processor chips comprising at least one input/output (I/O) component. The multi-processor system may also include first and second photonic components. The at least one I/O component of at least one of the processor chips may be configured to directly drive the first photonic component and receive a signal from the second photonic component. A total latency from any one of the processor chips to data at any global memory location may not be dominated by a round trip speed-of-light propagation delay. A number of the processor chips may be at least 10,000, and the processor chips may be packaged into a total volume of no more than 8 m3. A density of the processor chips may be greater than 1,000 chips per cubic meter.



DATA PROCESSING SYSTEM WITH SPECULATIVE FETCHING

Thu, 27 Oct 2016 08:00:00 EDT

A data processing system includes an instruction pipeline, a bus interface unit, and a cache. The instruction pipeline is configured to assert a discard signal when a speculative read request is determined to have been mispredicted. The speculative read request has a corresponding access address. The bus interface unit is configured to communicate with an external system interconnect. The cache includes a cache array and cache control circuitry. The cache control circuitry is configured to receive the discard signal from the instruction pipeline and, when the discard signal is asserted after the access address has been provided to the external system interconnect by the bus interface unit in response to a determination by the cache control circuitry that the access address missed in the cache array, selectively store the read information returned from the access address into the cache array.



METHOD FOR EXTENDING FUNCTION BY DOCKING AND ELECTRONIC DEVICE THEREOF

Thu, 27 Oct 2016 08:00:00 EDT

A first electronic device comprises a body, a docking portion that is provided on the body and is detachably coupled to the second electronic device, a terminal that comes into contact according to the coupling of the second electronic device, and a controller that identifies the coupling to the second electronic device, determines the basic performance of the second electronic device, determines the extended performance that can be provided by the first electronic device based on the basic performance of the second electronic device, and controls the second electronic device according to the basic performance of the second electronic device and the extended performance.



COMBO CHIP FOR USB CONNECTOR

Thu, 20 Oct 2016 08:00:00 EDT

A combo chip is provided. The combo chip is applicable to an USB connector, and includes an USB type-C circuit, an USB non-type-C circuit, a switch unit, and a mode control unit. The switch unit is connected to the USB type-C circuit and the USB non-type-C circuit, and the mode control unit is connected to a control terminal of the switch unit. After performing one or more mode determination procedures, the mode control unit controls the switch unit to connect the USB type-C circuit to a first pin and a second pin while disconnecting the USB non-type-C circuit from the first pin and the second pin, or otherwise controls the switch unit to connect the USB non-type-C circuit to the first pin and the second pin while disconnecting the USB type-C circuit from the first pin and the second pin.



ENHANCED VIRTUAL GPIO WITH MULTI-MODE MODULATION

Thu, 20 Oct 2016 08:00:00 EDT

A multi-modulation scheme is provided that combines pulse-width modulation and phase modulation to transmit a plurality of GPIO signals as virtual GPIO signals.



SYSTEM FOR COMMUNICATION VIA A PERIPHERAL HUB

Thu, 20 Oct 2016 08:00:00 EDT

Wireless peripherals may be used by workers to facilitate communication, data entry, data visualization, safety, and security. Typically, these peripherals must communicate with a back-end system; however, direct communication is often impossible. Instead, the peripherals must communicate through an intermediary device (i.e., a base station) to reach the back-end system. To be most effective, the back-end system must be able to adapt its communication/response to a worker's identity, location, and/or peripherals. To facilitate this, the present invention embraces a peripheral hub, worn by a worker. The peripheral hub uses information regarding the worker and/or his peripherals to generate a peripheral manifest. The peripheral hub can transmit the peripheral manifest to the back-end system via the base station, and using information from the peripheral manifest, the back-end system may communicate/respond appropriately to the worker.



ULTRA HIGH CAPACITY SOLID STATE DRIVE

Thu, 20 Oct 2016 08:00:00 EDT

A solid state drive with modular memory. The solid state drive may include a modular array of memory cards installed on a controller board, each memory card being connected to the controller board utilizing a respective connector. Redundant data, e.g., parity data, may be stored in the solid state drive, making it possible for a solid state drive controller on the controller board to restore the contents of a removed memory card (e.g., a memory card that has failed) on a replacement memory card installed in its place. The connector utilized to connect each memory card to the controller board may be an industry standard, commercial off the shelf connector, e.g., an M.2 connector; the functions of the conductors in the connector may be redefined, from the industry standard definitions, for the purposes of embodiments of the present invention.



SYSTEMS AND METHODS FOR ENABLING COMMUNICATION BETWEEN AN ACCESSORY CHARGER ADAPTER (ACA) AND AN ACA-AGNOSTIC UNIVERSAL SERIAL BUS CONTROLLER

Thu, 20 Oct 2016 08:00:00 EDT

A physical layer integrated circuit (PHY), including an accessory charger adapter (ACA) bridge circuit to communicate with an ACA via a universal serial bus (USB) cable having at least an ID pin and a VBUS pin. The PHY is also to communicate with an ACA-agnostic USB controller configured to act as an A-device or as a B-device. The ACA comprises a USB accessory port. The ACA bridge circuit comprises detection and control logic configured to detect, based on a resistance sensed on the ID pin, that a B-device is connected to the USB accessory port of the ACA and, as a result of such a detection, generate a signal to the USB controller that causes the USB controller to act as an A-device and ignore a VBUS drive signal from the USB controller that, if not ignored, would cause the PHY to drive the VBUS pin. The detection and control logic is also configured to detect, based on a resistance sensed on the ID pin, that an off/idle A-device or nothing is connected to the USB accessory port of the ACA and, as a result of such a detection, modify a signal to the USB controller that prevents the USB controller from being aware of a voltage on the VBUS pin.



CONTROLLER AREA NETWORK BUS

Thu, 20 Oct 2016 08:00:00 EDT

The present disclosure describes a vehicle implementing a processing module for receiving data from a high-speed CAN bus and sending data to a low-speed CAN bus. The processing module shunts into the data from the high-speed CAN bus without affecting the self-contained data flow of the high-speed CAN bus. The processing module analyzes the received data and generates data (by forwarding or other means) to be sent to a low-speed CAN bus according to the received data. The processing module is designed to be replaceable and/or upgradable without affecting other components during the life-cycle of the vehicle. The processing module may further contain expansion modules that perform tasks in response to the received data.



LOW POWER PARALLELIZATION TO MULTIPLE OUTPUT BUS WIDTHS

Thu, 20 Oct 2016 08:00:00 EDT

A Serializer/Deserializer (SerDes) is described with an architecture that simultaneously provides flexibility for many different gear ratios as well as reduced power consumption. The SerDes utilizes latches where flops were previously used to help reduce power consumption, among other things. The SerDes also includes a main register bank with a plurality of sub-banks that can be filled according to any number of different schemes, thereby enabling the SerDes to accommodate different output widths.



ADAPTER BOARD SYSTEM

Thu, 20 Oct 2016 08:00:00 EDT

A board adapter system includes a first adapter board. A secondary first processor coupling is located on the first adapter board, and the first adapter board passes signals between a primary first processor coupling on a first board and a first processor coupled to the secondary first processor coupling when the first adapter board engages the primary first processor coupling. A first/third processor communication bus extends between the secondary first processor coupling and the second board connector on the first adapter board, and passes signals between the first processor and a third processor that is coupled to the second board connector. A first/fourth processor communication bus extends between the secondary first processor coupling and the second board connector, and passes signals between the first processor and a fourth processor that is coupled to the second board connector on the first adapter board.



CHIP LEVEL SWITCHING FOR MULTIPLE COMPUTING DEVICE INTERFACES

Thu, 20 Oct 2016 08:00:00 EDT

Various semiconductor chips and computing devices are disclosed. In one aspect a semiconductor chip is provided that includes a first interface controller, a first physical layer connected to the first interface controller, a second interface controller, a second physical layer connected to the second interface controller, and a switch connected between the first interface controller and the second interface controller and the first physical layer and the second physical layer. The switch is operable in one mode to route signals to/from the first interface controller via the first physical layer and route signals to/from the second interface controller via the second physical layer and in another mode to route signals to/from both the first interface controller and the second interface controller via the first physical layer.



ELECTRONIC DEVICE AND METHOD FOR PERFORMING HYBRID COMMUNICATION WITH EXTERNAL ELECTRONIC DEVICE

Thu, 20 Oct 2016 08:00:00 EDT

Disclosed is an electronic device including a first communication circuit that perform communication by using a first communication protocol, and a processor electrically connected to the first communication circuit, wherein the processor activates the first communication circuit based on a predetermined mutual operation, sets an operating mode of the electronic device based on at least part of the activation of the first communication circuit, and operates a universal serial bus (USB) host controller through a switching circuit based on the set operating mode.



SMART WATCH WITH TRANSMISSION FUNCTION

Thu, 20 Oct 2016 08:00:00 EDT

A smart watch with transmission function is disclosed. The smart watch with transmission function includes a movement structure, two transmission watch straps, a first connecting element and a second connecting element. The movement structure includes a judgment unit. The two transmission watch straps connect with respect to the two ends of the movement structure, and thereby connect to the judgment unit. The first connecting element is disposed on one of the two transmission watch straps and opposed to one end of the movement structure. The second connecting element is disposed on another transmission watch strap and opposed to another end of the movement structure.



Negotiation Between Multiple Processing Units for Switch Mitigation

Thu, 20 Oct 2016 08:00:00 EDT

A method for maintaining data and clock line synchronization, which may include a clock line that may be driven high after a clock line falling edge to mitigate a clock error. Additionally, the clock error may be mitigated by maintaining a saturated state of a device. Furthermore, a register may be connected to a microcontroller and/or a graphical processing unit to negotiate control of a switch and a bus.



DATA TRANSMISSION AND RECEPTION SYSTEM

Thu, 20 Oct 2016 08:00:00 EDT

A communication system is provided. The communication system includes slave modules outputting collected data to a master module, and outputting data priority processing request information to the master module; and the master module connected to slave modules, collecting data from the slave modules, and processing, by priority, data from a corresponding slave module based on the data priority processing request information received from at least one slave module.



PROCESSING SYSTEM HAVING KEYWORD RECOGNITION SUB-SYSTEM WITH OR WITHOUT DMA DATA TRANSACTION

Thu, 20 Oct 2016 08:00:00 EDT

A processing system has a keyword recognition sub-system and a direct memory access (DMA) controller. The keyword recognition sub-system has a processor and a local memory device. The processor performs at least keyword recognition. The local memory device is accessible to the processor and is arranged to buffer at least data needed by the keyword recognition. The DMA controller interfaces between the local memory device of the keyword recognition sub-system and an external memory device, and is arranged to perform DMA data transaction between the local memory device and the external memory device.



BRIDGE CONFIGURATION IN COMPUTING DEVICES

Thu, 20 Oct 2016 08:00:00 EDT

Systems and methods are disclosed for configuring an interface bridge. A computing system includes a device controller, an interface bridge module coupled to the device controller configured to provide bridge functionality according to a first communication standard, a primary communication interface conforming to the first communication standard and coupled to the interface bridge module. The computing system further includes a first non-volatile memory module coupled to the interface bridge module, the first non-volatile memory module storing first stage boot loader code, a second non-volatile memory module coupled to the device controller, and a secondary communication interface conforming to a second communication standard coupled to the device controller. The device controller is configured to receive update package data over the secondary communication interface, the update package data including a firmware image, and write the update package data to the second non-volatile memory module.



IMAGE FORMING APPARATUS THAT TRANSMITS AND RECEIVES INFORMATION BETWEEN PLATFORMS, RECORDING MEDIUM, AND METHOD

Thu, 20 Oct 2016 08:00:00 EDT

An image forming apparatus includes a storage device, main process circuitry, and sub-process circuitry. The main process circuitry writes main-side transmission information to the storage device by all transmission/reception methods usable by the main process circuitry itself. The sub-process circuitry executes a specific process using the main-side transmission information read from the storage device to write process result information that indicates an execution result of the specific process to the storage device by a sub-usable method. The main process circuitry reads the process result information that has been written to the storage device by the sub-process circuitry by the sub-usable method from the storage device by the sub-usable method.



Synchronization Safeguards for Detecting Race Conditions in Multithreaded Programs

Thu, 20 Oct 2016 08:00:00 EDT

Each of a plurality of accesses by a multithreaded program to shared data structures stored within a database is monitored. The accesses are implemented by varying application programming interface (API) methods. Thereafter, it is determined, based on pre-defined synchronization safeguards, whether each of the accesses is valid or invalid based on the utilized corresponding API method. Those accesses to the shared data structures that were determined to be valid are allowed to proceed while those accesses to the shared data structures that were determined to be invalid are prevented from proceeding.



CONTROL MODULE OF NODE AND FIRMWARE UPDATING METHOD FOR THE CONTROL MODULE

Thu, 20 Oct 2016 08:00:00 EDT

A control module of a node comprising a baseboard management controller (BMC), a first memory and a second memory is present. The first memory stores a working firmware, the second memory stores a default firmware. The BMC normally connects with the first memory and reads the working firmware to boot during a booting procedure. If the BMC cannot boot through executing the working firmware after a firmware updating procedure executed for updating the working firmware failed, it switches to connect with the second memory and reads the default firmware to replace with the working firmware to boot. After the BMC boots through the default firmware successfully, it switches back to connect with the first memory, and re-updates the working firmware again.



Architecture and Method for an Interconnected Data Storage System Using a Unified Data Bus

Thu, 20 Oct 2016 08:00:00 EDT

A system and method for providing an interconnected data storage system that is able to avoid multiple data transfers, and thus increase the overall performance of the interconnected data storage system. A unified data bus interconnects a computing device with a plurality of storage devices via a plurality of storage systems; each of the plurality of storage systems having a main memory, processor, at least one storage controller, and a connecting port. The unified data bus is a local, high bandwidth bus that allows resources to be shared between the plurality of storage systems and with the computing device. Additionally, the unified data bus allows data to be transferred from the computing device to each of the plurality of storage devices in a single multi-target transfer. Furthermore, the architecture allows for a simpler management software that further increases performance of the interconnected data storage system.



SCALABLE AND AREA OPTIMIZED METHOD TO IMPLEMENT COMMAND QUEUES IN SRIOV BASED NVM DEVICES

Thu, 20 Oct 2016 08:00:00 EDT

Provided are method for dynamically allocating resources to command queues and response queues by a non-volatile memory (NVM) controller. The method includes creating command queues and response queues for at least one operating system among a plurality of operating systems running on a host system and mapping the created command queues and response queues to a plurality of internal shared queue registers. The plurality of operating systems running on the host system communicate with at least one NVM controller independently.



LIMITING IN-RUSH CURRENT FOR PLUG-IN CAPACITIVE LOADS

Thu, 20 Oct 2016 08:00:00 EDT

A circuit for limiting an in-rush current for devices coupling to a capacitive load may include a port configured to receive a device and a first capacitor coupled to the port. Additionally, the circuit may include a first resistor coupled in series with the first capacitor and a switch coupled in parallel with the first resistor. The switch is configured to close after an in-rush current event has passed, thereby bypassing the first resistor from the circuit and enabling the first capacitor to effectively filter noise from the voltage output to the port.



CAR MULTIMEDIA DEVICE

Thu, 20 Oct 2016 08:00:00 EDT

A car multimedia device includes a positioning board, a display and a data transmitting chip. The data transmitting chip is near the positioning board and is coupled to the display. A docking bay is defined in the multimedia device for docking an electronic device. The positioning board is located on one side of the docking bay. When the electronic device is located in the docking bay, the electronic device is configured to lean against the positioning board for facilitating coupling to the data transmitting chip.



DEVICE MANAGEMENT APPARATUS, DEVICE MANAGEMENT SYSTEM, AND DEVICE MANAGEMENT METHOD

Thu, 13 Oct 2016 08:00:00 EDT

A device management apparatus connected to a plurality of devices via a network includes a collecting unit that receives usage data indicating a status of use of each of the devices from each of the devices and that stores the received usage data in a storage device, and a common data acquiring unit that acquires common data that is common to the devices from the usage data of each of the devices stored in the storage device.



Dynamic Interconnect with Partitioning on Emulation and Protyping Platforms

Thu, 13 Oct 2016 08:00:00 EDT

A dynamic interconnect is described herein. The dynamic interconnect includes a transmit module, a receive module, and a multiplexer. Signal changes are detected in a group of transmit channels, and in response to the signal change an output of the multiplexer is switched to the channel where the change occurs.



PLL SYSTEM WITH MASTER AND SLAVE DEVICES

Thu, 13 Oct 2016 08:00:00 EDT

A master phase locked loop device is operable in association with one or more slave devices including slave digitally controlled oscillators (sDCOs), one or more digital PLL (DPLL) channels include a master digitally controlled oscillator (mDCO). A master synchronization timer generating master timing pulses to read phase and frequency information from the mDCO(s). A peripheral interface sends the read frequency and phase information to the one or more slave devices. A synchronization interface sends the master timing pulses to synchronize a replica synchronization timer in the sDCO(s) that generates slave timing pulses for use in updating the phase and frequency information received at the slave device(s).



TRANSITION-MINIMIZED LOW SPEED DATA TRANSFER

Thu, 13 Oct 2016 08:00:00 EDT

A method of transition minimized low speed data transfer is described herein. In an embodiment, a data rate of a set data to be transmitted on a data bus is determined. A one hot value is encoded on the data bus in response to a low data rate. An XOR operation is performed with a previous state of the data bus and the encoded one hot value. Additionally, a resulting value of the XOR operation is driven onto the data bus.



STANDARDIZED HOT-PLUGGABLE TRANSCEIVING UNIT WITH SDI SIGNAL TO IP FLOWS CONVERSION CAPABILITIES

Thu, 13 Oct 2016 08:00:00 EDT

A standardized hot-pluggable transceiving unit comprising a housing, a SDI connector, and a signal conversion module. The housing is adapted to being inserted into a chassis of a hosting unit. The SDI connector receives a SDI signal comprising a video payload and at least one other payload. The signal conversion module is in the housing, and converts the SDI signal into a first IP flow for transporting the video payload and at least one other IP flow for transporting the at least one other payload. The generated IP flows are outputted from the SFP unit by one or more connectors different from the SDI connector. The other payload can be an audio or a metadata payload. In another aspect, a transceiving unit provides for combining a plurality of IP flows each comprising a different type of payload into a SDI signal.



HIGH SPEED DATA SERIALIZATION THROUGH HERMETIC SEALS

Thu, 13 Oct 2016 08:00:00 EDT

A method for transmitting data between the inside and outside of a hermetically sealed chamber, including: serializing first data into a first serial data for transmission; transmitting the first serial data at a first frequency using a first transmission line that connects the inside and outside of the hermetically sealed chamber; wherein the first transmission line is coupled to a first ground.



WIRELESS MODULE

Thu, 13 Oct 2016 08:00:00 EDT

A wireless module includes a socket and a wireless plug. The socket is configured to couple to a circuit board. The wireless plug has a coupling unit, a data transmission unit, and a data operation unit. The coupling unit is configured to transfer data between the socket and the data operation unit. The data operation unit is configured to encode data from the coupling unit and decodes data from the data transmission unit. The data transmission unit is configured to send out the encoded data or receive data wirelessly. When the data transmission unit sends out the encoded data, the data is transferred from the socket via the coupling unit and the data operation unit. When the data transmission unit receives data, the received data is transferred to the socket via the data operation unit and the coupling unit.



UNIVERSAL SERIAL BUS (USB) FILTER HUB

Thu, 13 Oct 2016 08:00:00 EDT

Embodiments relate a universal serial bus (USB) filter hub. An aspect includes receiving, by the USB filter hub that is in communication with a host computer system, a connection from a USB device at a USB port of the USB filter hub. Another aspect includes determining, by the USB filter hub, a type of the USB device. Another aspect includes determining whether the type of the USB device is valid. Yet another aspect includes, based on determining that the type of the USB device is valid, filtering commands that are communicated between the USB device and the host computer system via the USB filter hub based on a predetermined command set corresponding to the determined type of the USB device.



MINIMIZING THERMAL IMPACTS OF LOCAL-ACCESS PCI DEVICES

Thu, 13 Oct 2016 08:00:00 EDT

A method includes performing operations on a compute node including a plurality of processors each having a local PCI processing element and a local processor interconnect, wherein the local processor interconnect of each processor is connected to the local processor interconnect of at least one other processor. The method further includes identifying a PCI device that is directly attached to the local PCI processing element of a first one of the processors and positioned in an upstream airflow direction from the first processor. The operating system monitors the PCI device and, in response to determining that the PCI device is performing a power-intensive operation, directs operations away from the first processor to a second one of the processors, wherein the local processor interconnect of the second processor is directly connected to the processor interconnect of the first processor.



Advanced PCI Express Board Assembly

Thu, 13 Oct 2016 08:00:00 EDT

An advanced PCI Express board assembly is intended for efficiently placing more electronic components or modules having a large height (up to 8.57 mm) in comparison with traditional PCI Express add-in boards. This assembly comprises two PCBs connected together. The first one has the minimum possible sizes. This PCB includes a PCI Express male edge connector and is intended to be plugged in to motherboard female PCI Express connector. The second PCB is parallel to first one and is located in the middle of the space (slot) defined for one add-in PCI Express board. This position makes possible to place high electronic components or modules on the both sides (top and bottom) of the second PCB.



METHOD FOR IMPROVING THE PERFORMANCE OF SYNCHRONOUS SERIAL INTERFACES

Thu, 13 Oct 2016 08:00:00 EDT

A slave device for exchanging data with a master device over a serial interface sends data to the master device upon receipt of a command from the master device. A controller responsive to a command byte in a receive register commences transmission of data in the transmit register under the control of a clock signal prior to reception of a complete command.



INTEGRATED COMPONENT INTERCONNECT

Thu, 13 Oct 2016 08:00:00 EDT

A data structure is accessed that defines configuration parameters of one or more integrated blocks in an integrated circuit device. One or more of the integrated blocks is configured based on corresponding configuration parameters defined in the data structure. The configuration parameters are set prior to runtime and are to be persistently stored in the data structure.



APPARATUS AND METHOD FOR EXTERNAL ACCESS TO CORE RESOURCES OF A PROCESSOR, SEMICONDUCTOR SYSTEMS DEVELOPMENT TOOL COMPRISING THE APPARATUS, AND COMPUTER PROGRAM PRODUCT AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM ASSOCIATED WITH THE METHOD

Thu, 13 Oct 2016 08:00:00 EDT

There is disclosed an apparatus for external access to core resources (211,212) of a processor (2) comprising a processing core (21), a shared memory (22), and a multiple paths Direct Memory Access, DMA, controller (23). Access to core critical resources can be performed while the core is executing an application program. The proposed apparatus comprises a Manager module (13) which is operable to setup the DMA controller to copy the assigned core resources via allocated DMA channel into a safe memory region. Further, an Observer module (14) is operable to read the transferred data and make the correlation on the host apparatus side. This allows accessing data used by the core via the DMA controller into, e.g., a run-time debugger accessible region.



PROCESSING OF EVENTS FOR ACCELERATORS UTILIZED FOR PARALLEL PROCESSING

Thu, 13 Oct 2016 08:00:00 EDT

According to embodiments of the present invention, machines, systems, methods and computer program products for processing events including efficiently processing interrupt service requests for peripheral devices, such as hardware accelerators, utilized in parallel processing are provided. For each core engine of a peripheral device, the peripheral device detects whether one or more interrupt signals have been generated. Information associated with the one or more interrupt signals are stored in one or more registers of peripheral device memory, for each core engine. The information is aggregated and stored in a vector of registers in the peripheral device memory, and the aggregated information is written to memory associated with a CPU to enable CPU processing of interrupt requests from each core engine of the peripheral device.



Computer architecture with peripherals

Thu, 13 Oct 2016 08:00:00 EDT

A shared memory computing device that has a system interconnect, an on-chip random access memory (RAM), at least one sub-computing device and a peripheral. The RAM is connected to the system interconnect. Each sub-computing device has: (a) a first local interconnect, (b) an interconnect master connected to a local interconnect of the sub-computing device; and (c) an interconnect bridge; in which the interconnect master is adapted to issue memory transfer requests to the RAM over that bridge. The peripheral comprises a target port which is connected to the first local interconnect of the first of the at least one sub-computing devices; and a first interconnect master port which is adapted to issue memory transfer requests to the RAM. The interconnect master of the first of the at least one sub-computing devices is adapted to issue memory transfer requests to the first peripheral.



MEMORY APPLIANCE COUPLINGS AND OPERATIONS

Thu, 13 Oct 2016 08:00:00 EDT

System and method for improved transferring of data involving memory device systems.



N-BASE NUMBERS TO PHYSICAL WIRE STATES SYMBOLS TRANSLATION METHOD

Thu, 13 Oct 2016 08:00:00 EDT

System, methods and apparatus are described that facilitate a device to encode/decode data in a data communications interface coupled to a plurality of wires. The device determines a value of a sequence of data bits allocated to a frame, converts the value into a sequence of symbols associated with the frame, and transmits the sequence of symbols to a receiver. The device performs the converting by calculating base-N coefficients of a base-N number polynomial for the frame based on the value, where N is greater than 2, calculating base-2 coefficients of a base-2 number polynomial for each symbol according to a respective base-N coefficient corresponding to each symbol, determining changes of states of the plurality of wires for each symbol according to the base-2 coefficients respectively calculated for each symbol, and generating the sequence of symbols based on the changes of states of the plurality of wires for each symbol.