Tue, 13 Sep 2016 08:00:00 EDTA method for forming an amorphous semiconductor which contains an impurity element and has low resistivity and a method for manufacturing a semiconductor device with excellent electrical characteristics with high yield are provided. In the method for forming an amorphous semiconductor containing an impurity element, which utilizes a plasma CVD method, pulse-modulated discharge inception voltage is applied to electrodes under the pressure and electrode distance with which the minimum discharge inception voltage according to Paschen's Law can be obtained, whereby the amorphous semiconductor which contains an impurity element and has low resistivity is formed.
Tue, 08 Mar 2016 08:00:00 ESTA highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. An oxide semiconductor film which can have a first crystal structure by heat treatment and an oxide semiconductor film which can have a second crystal structure by heat treatment are formed so as to be stacked, and then heat treatment is performed; accordingly, crystal growth occurs with the use of an oxide semiconductor film having the second crystal structure as a seed, so that an oxide semiconductor film having the first crystal structure is formed. An oxide semiconductor film formed in this manner is used for an active layer of the transistor.
Tue, 08 Mar 2016 08:00:00 ESTWhen forming sophisticated semiconductor-based gate electrode structures of transistors, the pre-doping of one type of gate electrode structure may be accomplished after the actual patterning of the electrode material by using an appropriate mask or fill material for covering the active regions and using a lithography mask. In this manner, a high degree of flexibility is provided with respect to selecting an appropriate patterning regime, while at the same time a uniform and superior cross-sectional shape for any type of gate electrode structure is obtained.
Tue, 01 Mar 2016 08:00:00 ESTA semiconductor device having favorable electric characteristics and a manufacturing method thereof are provided. A transistor includes an oxide semiconductor layer formed over an insulating layer, a source electrode layer and a drain electrode layer which overlap with part of the oxide semiconductor layer, a gate insulating layer in contact with part of the oxide semiconductor layer, and a gate electrode layer over the gate insulating layer. In the transistor, a buffer layer having n-type conductivity is formed between the source electrode layer and the oxide semiconductor layer and between the drain electrode layer and the oxide semiconductor layer. Thus, parasitic resistance is reduced, resulting in improvement of on-state characteristics of the transistor.
Tue, 02 Feb 2016 08:00:00 ESTA semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.
Tue, 05 Jan 2016 08:00:00 ESTA microelectronic assembly and method of making, which includes a first microelectronic element (including a substrate with first and second opposing surfaces, a semiconductor device, and conductive pads at the first surface which are electrically coupled to the semiconductor device) and a second microelectronic element (including a handler with first and second opposing surfaces, a second semiconductor device, and conductive pads at the handler first surface which are electrically coupled to the second semiconductor device). The first and second microelectronic elements are integrated such that the second surfaces face each other. The first microelectronic element includes conductive elements each extending from one of its conductive pads, through the substrate to the second surface. The second microelectronic element includes conductive elements each extending between the handler first and second surfaces. The conductive elements of the first microelectronics element are electrically coupled to the conductive elements of the second microelectronics element.
Tue, 17 Nov 2015 08:00:00 ESTA method for producing a Ga-containing group III nitride semiconductor having reduced threading dislocation is disclosed. A buffer layer in a polycrystal, amorphous or polycrystal/amorphous mixed state, comprising AlGaN is formed on a substrate. The substrate having the buffer layer formed thereon is heat-treated at a temperature higher than a temperature at which a single crystal of a Ga-containing group III nitride semiconductor grows on the buffer layer and at a temperature that the Ga-containing group III nitride semiconductor does not grow, to reduce crystal nucleus density of the buffer layer as compared with the density before the heat treatment. After the heat treatment, the temperature of the substrate is decreased to a temperature that the Ga-containing group III nitride semiconductor grows, the temperature is maintained, and the Ga-containing group III nitride semiconductor is grown on the buffer layer.
Tue, 27 Oct 2015 08:00:00 EDTAn object is to provide a thin film transistor and a method for manufacturing the thin film transistor including an oxide semiconductor with a controlled threshold voltage, high operation speed, a relatively easy manufacturing process, and sufficient reliability. An impurity having influence on carrier concentration in the oxide semiconductor layer, such as a hydrogen atom or a compound containing a hydrogen atom such as H2O, may be eliminated. An oxide insulating layer containing a large number of defects such as dangling bonds may be formed in contact with the oxide semiconductor layer, such that the impurity diffuses into the oxide insulating layer and the impurity concentration in the oxide semiconductor layer is reduced. The oxide semiconductor layer or the oxide insulating layer in contact with the oxide semiconductor layer may be formed in a deposition chamber which is evacuated with use of a cryopump whereby the impurity concentration is reduced.
Tue, 20 Oct 2015 08:00:00 EDTTo provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.
Tue, 22 Sep 2015 08:00:00 EDTDisclosed is a semiconductor device including an oxide semiconductor film. A first oxide semiconductor film with a thickness of greater than or equal to 2 nm and less than or equal to 15 nm is formed over a gate insulating layer. First heat treatment is performed so that crystal growth from a surface of the first oxide semiconductor film to the inside thereof is caused, whereby a first crystal layer is formed. A second oxide semiconductor film with a thickness greater than that of the first oxide semiconductor film is formed over the first crystal layer. Second heat treatment is performed so that crystal growth from the first crystal layer to a surface of the second oxide semiconductor film is caused, whereby a second crystal layer is formed. Further, oxygen doping treatment is performed on the second crystal layer.
Tue, 15 Sep 2015 08:00:00 EDTEmbodiments generally relate to optoelectronic devices and more specifically, to textured layers in optoelectronic devices. In one embodiment, a method for providing a textured layer in an optoelectronic device includes depositing a first layer of a first material and depositing an island layer of a second material on the first layer. Depositing the island layer includes forming one or more islands of the second material to provide at least one textured surface of the island layer, where the textured surface is operative to cause scattering of light.
Tue, 08 Sep 2015 08:00:00 EDTMethods for fabricating integrated circuits include fabricating a logic device on a substrate, forming an intermediate semiconductor substrate on a surface of the logic device, and fabricating a capacitor-less memory cell on the intermediate semiconductor substrate. Integrated circuits with capacitor-less memory cells formed on a surface of a logic device are also disclosed, as are multi-core microprocessors including such integrated circuits.
Tue, 01 Sep 2015 08:00:00 EDTThe object of the invention is to provide a method for fabricating a semiconductor device having a peeled layer bonded to a base material with curvature. Particularly, the object is to provide a method for fabricating a display with curvature, more specifically, a light emitting device having an OLED bonded to a base material with curvature. An external force is applied to a support originally having curvature and elasticity, and the support is bonded to a peeled layer formed over a substrate. Then, when the substrate is peeled, the support returns into the original shape by the restoring force, and the peeled layer as well is curved along the shape of the support. Finally, a transfer object originally having curvature is bonded to the peeled layer, and then a device with a desired curvature is completed.
Tue, 01 Sep 2015 08:00:00 EDTA metrology system for gauging and spatially mapping a semiconductor material on a substrate can be used in controlling deposition and thermal activation processes.
Tue, 18 Aug 2015 08:00:00 EDTA III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.
Tue, 18 Aug 2015 08:00:00 EDTA process for preparing a semiconductor structure for mounting to a carrier is disclosed. The process involves causing a support material to substantially fill a void defined by surfaces formed in the semiconductor structure and causing the support material to solidify sufficiently to support the semiconductor structure when mounted to the carrier.
Tue, 18 Aug 2015 08:00:00 EDTIt is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.
Tue, 28 Jul 2015 08:00:00 EDTEmbodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.
Tue, 28 Jul 2015 08:00:00 EDTA method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby.
Tue, 14 Jul 2015 08:00:00 EDTA semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.
Tue, 14 Jul 2015 08:00:00 EDTA first impurity region is formed by ion implantation through a first opening formed in a mask layer. By depositing a spacer layer on an etching stop layer on which the mask layer has been provided, a mask portion having the mask layer and the spacer layer is formed. By anisotropically etching the spacer layer, a second opening surrounded by a second sidewall is formed in the mask portion. A second impurity region is formed by ion implantation through the second opening. An angle of the second sidewall with respect to a surface is 90°±10° across a height as great as a second depth. Thus, accuracy in extension of an impurity region can be enhanced.
Tue, 14 Jul 2015 08:00:00 EDTA light emitting element array for an illumination apparatus, an illumination apparatus and method of manufacture of the same in which an array of light-emitting elements and an array of light directing optics are provided between first and second attached mothersheet substrates wherein the thermal resistance of at least one of the mothersheet substrates is reduced by means of thickness reduction so as to provide reduced LED junction temperature.
Tue, 07 Jul 2015 08:00:00 EDTAn object of an embodiment of the present invention to be disclosed is to prevent oxygen from being taken in a single crystal semiconductor layer in laser irradiation even when crystallinity of the single crystal semiconductor layer is repaired by irradiation with a laser beam; and to make substantially equal or reduce an oxygen concentration in the semiconductor layer after the laser irradiation comparing before the laser irradiation. A single crystal semiconductor layer which is provided over a base substrate by bonding is irradiated with a laser beam, whereby the crystallinity of the single crystal semiconductor layer is repaired. The laser irradiation is performed under a reducing atmosphere or an inert atmosphere.
Tue, 09 Jun 2015 08:00:00 EDTA method for manufacturing a light-emitting device includes a step of forming an etching resistant protection layer on a substrate provided with an organic planarizing layer, a step of forming a plurality of electrodes on the etching resistant protection layer, a step of forming an organic compound layer on the substrate provided with the plurality of electrodes, a step of forming a resist layer on the organic compound layer formed on parts of electrodes among the plurality of electrodes using a photolithographic method, and a step of removing the organic compound layer in a region not covered with the resist layer by dry etching, wherein an entire surface of the organic planarizing layer on the substrate on which steps up to the step of forming the plurality of electrodes have been performed is covered with at least one of the etching resistant protection layer and the electrode.
Tue, 09 Jun 2015 08:00:00 EDTA larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor layer having a high degree of crystallinity, whereby a large-sized display device, a high-performance semiconductor device, or the like can be put into practical use. A first multi-component oxide semiconductor layer is formed over a substrate and a single-component oxide semiconductor layer is formed thereover; then, crystal growth is carried out from a surface to an inside by performing heat treatment at 500° C. to 1000° C. inclusive, preferably 550° C. to 750° C. inclusive so that a first multi-component oxide semiconductor layer including single crystal regions and a single-component oxide semiconductor layer including single crystal regions are formed; and a second multi-component oxide semiconductor layer including single crystal regions is stacked over the single-component oxide semiconductor layer including single crystal regions.
Tue, 02 Jun 2015 08:00:00 EDTIn manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.
Tue, 02 Jun 2015 08:00:00 EDTA method for fabricating a sensor includes: forming, on a base substrate, a pattern of a source electrode and a drain electrode, a pattern of a data line, a pattern of a receiving electrode, a pattern of a photodiode, and a pattern of a transparent electrode disposed by using a first patterning process; forming a pattern of an ohmic layer by using a second patterning process; forming a pattern of an active layer by using a third patterning process; forming a pattern of a gate insulating layer by using a fourth patterning process, wherein the gate insulating layer has a via hole above the transparent electrode; and forming a pattern of a gate electrode, a pattern of a gate line, and a pattern of a bias line connected to the transparent electrode via the via hole above the transparent electrode by using a fifth patterning process.
Tue, 02 Jun 2015 08:00:00 EDTA base at least one principal plane of which is a nitride is prepared for use in epitaxial growth. The base is placed on a susceptor in an epitaxial growth reactor and heated to a predetermined temperature (step A). The heating is started with inactive, nitrogen gas being supplied into the reactor. Then, active, NH3 gas is supplied. Then, a growth step (step B) of a first nitride semiconductor layer is started without an intervening step of thermally cleaning the principal nitride plane of the base. In step B, the first nitride semiconductor layer is epitaxially grown on a principal nitride plane of a base without supply of an Si source material. Then, a relatively thick, second nitride semiconductor layer is epitaxially grown on the first nitride semiconductor layer by supplying an n-type dopant source material (step C).
Tue, 26 May 2015 08:00:00 EDTMethods, systems, and structures for detecting residual material on semiconductor wafers are provided. A method includes scanning a test structure including topographic features on a surface of a semiconductor wafer. The method further includes determining, based on the scanning, that the test structure includes an amount of a residual material of a sacrificial layer that exceeds a predetermined threshold.
Tue, 26 May 2015 08:00:00 EDTDescribed herein are methods and systems for providing corrective maintenance using global knowledge sharing. A method to provide corrective maintenance with a CM system includes performing a query to generate a ranking of fixable causes based on factors (e.g., symptoms, configuration, test). The ranking may be determined based on a fixable cause percent match with the factors. The ranking of fixable causes may be associated with one or more solutions for each fixable cause. The ranking can be updated based on performing tests or solutions.
Tue, 26 May 2015 08:00:00 EDTA sensor substrate includes a blocking pattern disposed on a base substrate, a first electrode disposed on the base substrate and overlapping the blocking pattern, the first electrode including a plurality of first unit parts arranged in a first direction, each of the first unit parts including a plurality of lines connected to each other in a mesh-type arrangement, a color filter layer disposed on the base substrate, a plurality of contact holes defined in the color filter layer and exposing the first unit parts, and a bridge line between and connected to first unit parts adjacent to each other in the first direction, through the contact holes.
Tue, 26 May 2015 08:00:00 EDTThe present invention relates to a camera module including: a lens unit mounted with at least one or more lenses; an image sensor mounted with an image pickup device for converting a light converged through the lenses to an electric signal; a PCB (Printed Circuit Board) mounted with the image sensor; and a holder accommodated inside the lens unit for supporting the lens unit, wherein the lens unit is bonded and fixed at an inner surface of the holder, whereby the lens unit mounted with a plurality of lenses is bonded to a lateral surface of a holder to prevent generation of vertical tilting phenomenon at the lens unit caused by a conventional improper coating of epoxy, and particularly, the coating of epoxy on the lateral surface of the holder advantageously enhances adhesive power to increase a bonded area.
Tue, 26 May 2015 08:00:00 EDTSystems, manufactures, methods and/or techniques for a merged fiducial for chip packages are described. According to some embodiments, an integrated circuit package may include a package substrate having a first side and a second side, a plurality of conductive traces coupled to the first side and a plurality of balls disposed on the second side. The balls may be adapted to electrically connect the laminate package to a circuit board. The integrated circuit package may include a plurality of ball pads disposed on the second side, the ball pads being adapted to electrically connect the plurality of balls to the plurality of conductive traces. One or more of the ball pads may be uniquely shaped when compared to the rest of the plurality of ball pads, optionally, to serve as a fiducial to designate an A1 pin or ball of the laminate package.
Tue, 26 May 2015 08:00:00 EDTIn various embodiments, a chip arrangement is provided. The chip arrangement may include a chip carrier and a chip mounted on the chip carrier. The chip may include at least two chip contacts and an insulating adhesive between the chip and the chip carrier to adhere the chip to the chip carrier. The at least two chip contacts may be electrically coupled to the chip carrier.
Tue, 26 May 2015 08:00:00 EDTAn embodiment is an integrated circuit structure including a first die attached to a second die by a first connector. The first connector includes a solder joint portion between a first nickel-containing layer and a second nickel-containing layer, a first copper-containing layer between the first nickel-containing layer and the solder joint portion, and a second copper-containing layer between the second nickel-containing layer and the solder joint portion.
Tue, 26 May 2015 08:00:00 EDTA method for producing a solder joint between at least one base part (2) and at least one first component (3) includes the following steps: providing the base part (2); partially blasting a surface of the base part (2) using a SACO blasting agent, the blasting material (50) of which has a silicate coating (52), in such a way that a SACO-blasted region (20) and a non-blasted positioning region (40) are present; and soldering the at least first component (3) onto the non-blasted positioning region (40), wherein the SACO-blasted region (20) acts as a solder resist.
Tue, 26 May 2015 08:00:00 EDTA bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.
Tue, 26 May 2015 08:00:00 EDTA multi-chip package is provided. The multi-chip package includes a plurality of chips including at least one bad chip and at least one good chip that are stacked and a plurality of through electrodes each penetrating the chips. A logic circuit included in the at least one bad chip is isolated from each of the plurality of through electrodes.
Tue, 26 May 2015 08:00:00 EDTAn interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a first etch stop layer (ESL) over the lower conductive feature, wherein the first ESL comprises a metal compound; an upper LK dielectric layer over the first ESL; and an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature extends through the first ESL and connected to the lower conductive feature. The interconnect structure may further include a second ESL between the upper LK dielectric layer and the first ESL, or between the first ESL and the lower conductive feature, wherein the second ESL comprises a silicon compound.
Tue, 26 May 2015 08:00:00 EDTDisclosed herein is a single mask package apparatus on a device comprising a first substrate having a land disposed on a first surface, a stud disposed on the land and a protective layer disposed over the first surface of the first substrate and around the stud. The protective layer may optionally have a thickness of at least 3 μm. A PPI may be disposed over the protective layer and in electrical contact with the stud, with a first portion of the PPI extending laterally from the stud. An interconnect may be disposed on and in electrical contact with the first portion of the PPI, and a second substrate mounted on the interconnect. A molding compound may be disposed over the PPI and around the interconnect. The stud may be a substantially solid material having a cylindrical cross section and may optionally be wirebonded to the land.
Tue, 26 May 2015 08:00:00 EDTMethods for the fabrication of a Microelectromechanical Systems (“MEMS”) devices are provided, as are MEMS devices. In one embodiment, the MEMS device fabrication method includes forming at least one via opening extending into a substrate wafer, depositing a body of electrically-conductive material over the substrate wafer and into the via opening to produce a via, bonding the substrate wafer to a transducer wafer having an electrically-conductive transducer layer, and forming an electrical connection between the via and the electrically-conductive transducer layer. The substrate wafer is thinned to reveal the via through a bottom surface of the substrate wafer, and a backside conductor is produced over a bottom surface of the substrate wafer electrically coupled to the via.
Tue, 26 May 2015 08:00:00 EDTA through silicon via with sidewall roughness and methods of manufacturing the same are disclosed. The method includes forming a via in a substrate and roughening a sidewall of the via by depositing material within the via. The method further includes removing a backside of the substrate to form a through via with a roughened sidewall structure.
Tue, 26 May 2015 08:00:00 EDTIn a disclosed embodiment, a method for tiling selected vias in a semiconductor device having a plurality of vias comprises generating a layout database for the semiconductor device; creating zones around the plurality of vias; measuring density of covering metal in each zone; selecting a low density zone as being a zone that has a metal density less than a threshold metal density; and adding at least one tiling feature on a metal layer above the plurality of vias in the low density zone so that metal density of the low density zone increases to at least the same as the threshold metal density.
Tue, 26 May 2015 08:00:00 EDTAn apparatus including a die including a dielectric material on a device side, an insulating layer surrounding a die area and embedding a thickness dimension of the die; and a carrier including a plurality of layers of conductive material disposed on the device side of the die, a first one of the layers of conductive materials being formed on the insulating layer and patterned into traces at least a portion of which are connected to respective contact points on the die. A method including disposing a die on a sacrificial substrate with a device side of the die opposite the sacrificial substrate; disposing a mold on the sacrificial substrate around; introducing an insulating material into a chase of the mold; removing the mold; forming a carrier on the insulating material adjacent a device side of a die; and separating the die and the carrier from the sacrificial substrate.
Tue, 26 May 2015 08:00:00 EDTA semiconductor device comprises a first semiconductor chip including a first substrate and a plurality of first metal lines formed over the first substrate and a second semiconductor chip bonded on the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate and a plurality of second metal lines formed over the second substrate. The semiconductor device further comprises a conductive plug coupled between the first metal lines and the second metal lines, wherein the conductive plug comprises a first portion formed over a first side of a hard mask layer, wherein the first portion is of a first width and a second portion formed over a second side of the hard mask layer, wherein the second portion is of a second width greater than or equal to the first width.
Tue, 26 May 2015 08:00:00 EDTMaskless hybrid laser scribing and plasma etching wafer dicing processes are described. In an example, a method of dicing a semiconductor wafer having a front surface with a plurality of integrated circuits thereon and having a passivation layer disposed between and covering metal pillar/solder bump pairs of the integrated circuits involves laser scribing, without the use of a mask layer, the passivation layer to provide scribe lines exposing the semiconductor wafer. The method also involves plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, wherein the passivation layer protects the integrated circuits during at least a portion of the plasma etching. The method also involves thinning the passivation layer to partially expose the metal pillar/solder bump pairs of the integrated circuits.
Tue, 26 May 2015 08:00:00 EDTA land grid array (LGA) package including a substrate having a plurality of lands formed on a first surface of the substrate, a semiconductor chip mounted on a second surface of the substrate, a connection portion connecting the semiconductor chip and the substrate, and a support layer formed on part of a surface of a first land.
Tue, 26 May 2015 08:00:00 EDTThe stack package includes a first semiconductor package and a second semiconductor package. The first semiconductor package includes a first substrate having a first modulus and at least one semiconductor chip mounted on the first substrate. The second semiconductor package stacked on the first semiconductor package and includes a second substrate having a second modulus and at least one semiconductor chip mounted on the second substrate. The second modulus is less than the first modulus. Even in the event that the first semiconductor package is under severe warpage due to a temperature change, the flexible second substrate, which includes e.g., polyimide or poly ethylene terephthalate, of the second semiconductor package may be less sensitive to the temperature change, thereby improving reliability of the stack package.
Tue, 26 May 2015 08:00:00 EDTSome implementations provide a structure that includes a first package substrate, a first component, a second package substrate, a second component, and a third component. The first package substrate has a first area. The first component has a first height and is positioned on the first area. The second package substrate is coupled to the first package substrate. The second package substrate has second and third areas. The second area of the second package substrate vertically overlaps with the first area of the first package substrate The third area of the second package substrate is non-overlapping with the first area of the first package substrate. The second component has a second height and is positioned on the second area. The third component is positioned on the third area. The third component has a third height that is greater than each of the first and second heights.
Tue, 26 May 2015 08:00:00 EDTThe present invention relates generally to a semiconductor device and, more specifically, to optimizing the creep-age distance of the power semiconductor device and a preparation method thereof. The power semiconductor device includes a chip mounting unit with a die paddle and a plurality of leads arranged side by side located close to one side edge of the die paddle in a non-equidistant manner, a semiconductor chip attached on the die paddle, and a plastic packaging body covering the die paddle, the semiconductor chip, where the plastic packing body includes a plastic extension portion covering at least a part of a lead shoulder of a lead to obtain better electrical safety distance between the terminals of the semiconductor device, thus voltage creep-age distance of the device is increased.