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System and method for data compression and transmission

Tue, 01 Sep 2015 08:00:00 EDT

A system, method, and apparatus for compressing binary code comprising at least a processor, memory, storage, and an encoding device or decoding device or both. The methods include comparing a given binary code string having a certain size to be compressed or decompressed with a table comprising all possible combinations of zeroes and ones for any binary data of size x. The given binary code string and all possible combinations are partitioned in packets of size y and each packet assigned a value. A second value representing an assembly of all the values into a second value is performed. The assembly may be performed n times to obtain an nth value. The second or nth value is transmitted or received or both by the encoding and decoding devices, respectively, in place of the given binary code. Table comparison may be performed using pattern recognition.



Dynamically adjusted A/D resolution

Tue, 14 Jul 2015 08:00:00 EDT

A process variable transmitter is used to measure a process variable, and, in doing so, dynamically changes the resolution of the A/D converter based upon the measured value of the analog input signal. This can be done by automatically adjusting the configurable resolution gain adjustment based on the value of the analog signal being measured, by normalizing the input signal being measured so that it is centered in an optimal resolution window of the A/D converter, or by adjusting a voltage reference provided to the A/D converter.



User interface with enlarged icon display of key function

Tue, 26 May 2015 08:00:00 EDT

To improve the consumer experience with portable electronic devices, a user interface combines the use of capacitive sensors with tactile sensors in an input device. When a user places a finger, stylus, or other input instrument near a given key button, a capacitive sensor causes the display to display temporarily an indication of the function of that key in an enlarged format. The user may then press the associated key button to activate the desired function. In one exemplary embodiment, the capacitive sensor fixes the functionality to the function indicated in the display. In this embodiment, a tactile input applied to any key, whether the correct key, multiple keys, or a single incorrect key, results in activating the function indicated in the display as a result of the capacitive input.



Adaptive grouping of parameters for enhanced coding efficiency

Tue, 26 May 2015 08:00:00 EDT

The present invention is based on the finding that parameters including: a first set of parameters of a representation of a first portion of an original signal and a second set of parameters of a representation of a second portion of the original signal can be efficiently encoded when the parameters are arranged in a first sequence of tuples and a second sequence of tuples. The first sequence of tuples includes tuples of parameters having two parameters from a single portion of the original signal and the second sequence of tuples includes tuples of parameters having one parameter from the first portion and one parameter from the second portion of the original signal. A bit estimator estimates the number of necessary bits to encode the first and the second sequence of tuples. Only the sequence of tuples, which results in the lower number of bits, is encoded.



Differential signal transmission

Tue, 26 May 2015 08:00:00 EDT

Transport of differential signals is provided. In one aspect, a telecommunications system includes a first unit and a second unit. The first unit can calculate a differential signal from an original signal. The differential signal can represent a change in signal levels between constant time intervals in the original signal. The second unit can estimate the original signal from the differential signal received from the first unit over a communication medium.



Imaging apparatus and camera

Tue, 26 May 2015 08:00:00 EDT

An imaging apparatus including a pixel, a current source, and a signal processing circuit. The pixel outputs signal charge, obtained by imaging, as a pixel signal. The current source is connected to a transmission path for the pixel signal and has a variable current. The signal processing circuit performs signal processing on a signal depending on an output signal to the transmission path and performs control so that a current of the current source is changed in accordance with the result of signal processing.



Ergonomic keyboard

Tue, 26 May 2015 08:00:00 EDT

An ergonomic keyboard is described. In one aspect, a keyboard layout for a subject language is developed by determining a percent of frequency of monograph characters and digraphs of characters used in writing in the subject language. Thereafter, each key for the characters from each most frequent digraph is positioned under different hands on the keyboard layout, on a middle row of the keyboard layout, and under the index or middle fingers of a keyboard user. Other most frequent characters are positioned in the middle row of the keyboard layout or in a position on the keyboard layout to be struck using the index or middle fingers. The least frequent monograph characters are positioned in the bottom and top rows of the keyboard, with the least frequent characters under pinky fingers of a keyboard user. An optimized Arabic keyboard layout is also disclosed.



Keyboard device for small size tablet personal computer

Tue, 26 May 2015 08:00:00 EDT

A keyboard device for a small size tablet personal computer is provided. The keyboard device includes a first casing, a connecting plate, and a second casing. The first casing includes a first keyboard plate and a first recess. The second casing includes a second keyboard plate and a second recess. The connecting plate is connected with the first casing and the second casing. Consequently, the second casing is rotatable relative to the first casing. The first keyboard plate and the second keyboard plate are collectively defined as a whole keyboard to be operated by both hands of the user. Moreover, the small size tablet personal computer is accommodated within the first recess and the second recess collaboratively.



Fusion keyboard

Tue, 26 May 2015 08:00:00 EDT

Touch sensitive mechanical keyboards for detecting touch events and key depressions on the keyboard are provided. The keyboard can include a set of individually depressible mechanical keys having a touch sensitive area located on their surface. A touch sensor can be included to detect touch events on the surface of the keys. A keypad can also be included to detect a depression of the mechanical keys. One or more of the depressible mechanical keys can be multi-purpose keys capable of being depressed to multiple levels. The touch sensitive mechanical keyboard can receive key depression input, touch event input, or combinations thereof at the same time. The touch sensitive mechanical keyboard can further include a processor for distinguishing detected touch events from detected key depressions. The processor can generate a key depression command or a touch event command in response to the detected touch events and key depressions.



Dual-path comparator and method

Tue, 26 May 2015 08:00:00 EDT

A method includes receiving a differential voltage signal at first and second inputs of a comparator and selectively providing the differential voltage signal to one of a first conversion path and a second conversion path of the comparator during a conversion phase to determine a digital value corresponding to the differential voltage signal. The first and second conversion paths including first and second pluralities of gain stages, respectively. The method further includes coupling the selected one of the first conversion path and the second conversion path to an output to provide the digital value.



Comparator, solid-state imaging device, electronic apparatus, and driving method

Tue, 26 May 2015 08:00:00 EDT

A comparator includes: a first amplifying unit that includes a differential pair configured with a pair of transistors which are first and second transistors, and amplifies a difference of signals input to each of the gate electrodes of the first and second transistors, to output; a second amplifying unit that amplifies the signal output from the first amplifying unit; a first condenser that is disposed between a gate electrode of the first transistor and a reference signal supply unit; a second condenser that is disposed between a gate electrode of the second transistor and a pixel signal wiring; a third transistor that connects a connection point of the gate electrode of the first transistor and the first condenser to the pixel signal wiring; and a fourth transistor that connects a connection point of the gate electrode of the second transistor and the second condenser to the pixel signal wiring.



Organism state quantity measuring apparatus

Tue, 26 May 2015 08:00:00 EDT

An apparatus including a detecting unit that detects information indicating a state of an organism from the organism or an organism specimen extracted from the organism and outputs the detected information as a current, a current-voltage conversion circuit that converts the current output from the detecting unit into a voltage, a double-integration-type A/D conversion circuit having an integration capacitor that is charged based on a voltage output from the current-voltage conversion circuit and is thereafter discharged, and a counter that measures a charge time during which the integration capacitor is charged and a discharge time during which the integration capacitor is discharged, the A/D conversion circuit converting into digital quantities the charge time and the discharge time measured by the counter, and outputting the digital quantities, and an information processing unit that calculates a state quantity of the organism based on the digital quantities output from the A/D conversion circuit.



Analog-to-digital conversion

Tue, 26 May 2015 08:00:00 EDT

An analog-to-digital conversion apparatus 10 comprises a plurality of analog-to-digital converters 30 and a ramp generator 20. Each of the analog-to-digital converters 30 comprises an analog signal input for receiving an analog signal level and a ramp signal input. A control stage is arranged to compare the ramp signal with the analog signal level and, based on the comparison, to enable a counter provided at the analog-to-digital converter or to latch a digital value received from a counter. The control stage comprises a comparator in the form of a first differential amplifier with a first branch connected to the input for receiving the ramp signal, a second branch connected to the analog signal input and an output, and a biasing current source for biasing the first differential amplifier. A feedback circuit controls the biasing current source. The feedback circuit comprises a second differential amplifier OP1 with a first input connected to a node 46 on the first branch and a second input connected to a reference voltage VB such that the node on the first branch is maintained at a substantially constant voltage.



Solid-state imaging apparatus and semiconductor device

Tue, 26 May 2015 08:00:00 EDT

The present invention provides a small-sized inexpensive solid-state imaging apparatus. A D/A converter included in a successive comparison type A/D converter of the solid-state imaging apparatus includes a multiplexer which selects any of reference voltages VR0 to VR16 and sets it as an analog reference signal when coarse A/D conversion is performed, and which selects reference voltages VR (n−1) to VR (n+2) of the reference voltages VR0 to VR16 when fine A/C conversion is performed, and a capacitor array which generates an analog reference signal, based on the reference voltages VR (n−1) to VR (n+2) when the fine A/D conversion is performed. It is thus possible to reduce settling errors in reference voltage without using redundant capacitors.



Analog-to-digital conversion in pixel arrays

Tue, 26 May 2015 08:00:00 EDT

An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N≧2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.



Digital-to-analogue converter

Tue, 26 May 2015 08:00:00 EDT

The invention relates to digital-to-analog converters for converting current. The converter includes a pair of differential branches with two transistors controlled by a digital register activated at a clock frequency, and two resistive loads receiving the currents of the differential branches to produce a differential electrical signal representing the analog result of the conversion. The converter includes a dual switching circuit for the currents of the differential branches: a first switching circuit enables the transmission of the currents of the differential branches toward the loads for 70% to 95% of the clock period and shunts these currents outside the loads for the rest of the time; a second switching circuit alternately and symmetrically makes a direct link followed by a cross link between the differential branches and the loads. The converter provides a signal with high spectral purity and can work with a good level of power in the four Nyquist zones of the spectrum of the output analog signal, and notably in the second and third zones.



Circuit and method

Tue, 26 May 2015 08:00:00 EDT

Embodiments of the present invention create a circuit having a digital-to-time converter with a high-frequency input for receiving a high-frequency signal, a digital input for receiving a first digital signal, and a high-frequency output for the provision of a chronologically delayed version of the HF signal. In addition, the circuit has an oscillator arrangement for the provision of the high-frequency signal, having a phase-locked loop for adjusting a frequency of the high-frequency signal. The digital-to-time converter is designed to chronologically delay the received high-frequency signal based on the first digital signal received at its digital input.



Analog-to-digital conversion apparatus and method capable of achieving fast settling

Tue, 26 May 2015 08:00:00 EDT

A method utilized in an analog-to-digital conversion apparatus, for converting an analog input signal into a digital output signal including a first portion and a second portion, includes: using a comparator circuit to compare the analog input signal with at least one first reference level to generate a preliminary comparison result, the at least one first reference level being used for determining the first portion; estimating the first portion according to the preliminary comparison result; based on the preliminary comparison result, performing the successive approximation procedure to obtain a posterior comparison result according to a plurality of second reference levels, the second reference levels being used for determining the second portion; and, estimating the second portion according to the posterior comparison result. The preliminary and posterior comparison results are generated by the comparator circuit.



Input converter for a hearing aid and signal conversion method

Tue, 26 May 2015 08:00:00 EDT

In order to minimize noise and current consumption in a hearing aid, an input converter including a first voltage transformer and an analog-to-digital converter of the delta-sigma type for a hearing aid is devised. The analog-to-digital converter of the input converter has an input stage, an output stage, and a feedback loop, and the input stage includes an amplifier (QA) and an integrator (RLF). The first voltage transformer (IT) has a transformation ratio such that it provides an output voltage larger than the input voltage and is placed in the input converter upstream of the input stage. A second voltage transformer (OT) having a transformation ratio such that it provides an output voltage larger than the input voltage, is optionally placed in the feedback loop of the converter. The voltage transformers (IT, OT) are switched-capacitor voltage transformers, each transformer (IT, OT) having at least two capacitors (Ca, Cb, Cc, Cd). The invention further provides a method of converting an analog signal.



Sampling device with buffer circuit for high-speed ADCs

Tue, 26 May 2015 08:00:00 EDT

A sampling and interleaving stage device for use in an analog-digital-converter and for providing a sampling output signal and an analog-to-digital-converter. The sampling and interleaving stage device for use in an analog-digital-converter, including: a receiving unit having a clock unit with a plurality of clock-driven switches for receiving an input signal; for each of the plurality of clock-driven switches, a first demultiplexer, for receiving the input signal via a clock-driven switch and for providing a number of first demultiplexer outputs; for a first demultiplexer output, at least one storage element for a stored input potential depending on the input signal; and an output demultiplexer for receiving an indication about the stored input potential and for outputting a corresponding sampling output signal to a respective sampling output.



Testing a digital-to-analog converter

Tue, 26 May 2015 08:00:00 EDT

Testing a digital-to-analog converter (DAC), where the test is carried out iteratively for a plurality of digital test signal values, includes: providing the digital test signal to a DAC under test and to a servo; providing, by the DAC under test to a summer, an analog test signal, including converting the digital test signal to the analog test signal; providing, by the summer to an observation latch, a summed signal, including summing the analog test signal and an analog offset signal, the analog offset signal received from a second DAC; providing, by the observation latch to the servo, a sample of the summed signal; providing, by the servo to the second DAC in dependence upon the sample and the digital test signal, a digital offset signal, where the second DAC converts the digital offset signal to the analog offset signal; and storing, as a digital observation, the digital offset signal.



Flexible ADC calibration technique using ADC capture memory

Tue, 26 May 2015 08:00:00 EDT

Systems and methods are provided for calibrating an analog to digital converter (ADC) using one or more feedback mechanisms. In an embodiment, a capture memory module captures a portion of ADC data and post-processes the captured data using a microprocessor to perform calibration. Using the microprocessor, the capture memory module calibrates the ADC until the output of the ADC is within a desired range. In an embodiment, the capture memory module also captures a portion of data output from a digital correction module and post-processes this captured data using the microprocessor. Using the microprocessor, the capture memory module calibrates the digital correction module until the output of the digital correction module is within a desired range.



Analog-to-digital converter and analog-to-digital conversion method

Tue, 26 May 2015 08:00:00 EDT

An analog-to-digital converter according to the present invention includes first and second analog-to-digital conversion cells (11, 12), control means (10) for, when a mode specifying signal MD indicates a first mode, generating a control signal that sets first and second input ranges to the same voltage range and sets first and second clocks to different phases, and when the mode specifying signal MD indicates a second mode, generating the control signal that sets the first and second input ranges to one continuous voltage range and sets the first and second clocks to the same phase, ADC cell control means (111) for controlling the voltage ranges of the first and second input ranges according to the control signal, and a sampling clock generation unit (112) that generates the first and second sampling clocks according to the control signal.



Method and apparatus for calibration of successive approximation register analog-to-digital converters

Tue, 26 May 2015 08:00:00 EDT

A successive approximation register (SAR) ADC includes an SAR comparator circuit including first and second inputs, a control input, and first and second outputs. The SAR comparator circuit further includes a plurality of capacitors coupled to the first and second inputs and includes a plurality of switches configured to couple the plurality of capacitors to one of a first voltage and a second voltage. The SAR ADC further includes a calibration circuit coupled to the first and second outputs and to the control input of the SAR comparator. The calibration circuit is configured to control the plurality of switches to selectively couple the plurality of capacitors to one of the first and second voltages to provide a calibration signal to the SAR comparator circuit. The calibration circuit is configured to calibrate the SAR comparator based on corresponding output signals at the first and second outputs.



Estimator for estimating a probability distribution of a quantization index

Tue, 26 May 2015 08:00:00 EDT

The invention relates to an estimator for estimating a probability distribution of a quantization index generated from a source coder encoding a source signal, into a sequence of quantization indices, the source signal being described by a signal model, the source coder providing a current quantization index and current side information, the estimator being configured to obtain auxiliary parameters based on a configuration of the source coder and the current available side information and the signal model, the estimator being further configured to adaptively update the probability distribution of a quantization index upon the basis of a probability density function relating to a previous state of the estimator, the auxiliary parameters, the current quantization index and the current side information.



Using variable encodings to compress an input data stream to a compressed output data stream

Tue, 26 May 2015 08:00:00 EDT

Provided are a computer program product, system, method, and data structure for compressing an input data stream. A determination is made of consecutive data units in the input data stream that match consecutive data units in a history buffer. A copy pointer symbol indicates a copy pointer symbol referencing previously received data units in the history buffer. A determination is made of a relative displacement count in the history buffer at which the number of matching consecutive data units start. A determination is made of a range of relative displacement counts comprising one of a plurality of ranges of displacement counts including the determined relative displacement count. A determination is made of the encoding scheme associated with the determined range. An encoding of the relative displacement count is determined from the determined encoding scheme. The determined encoding of the relative displacement count is indicated in the copy pointer.



Lossless compression of the enumeration space of founder line crosses

Tue, 26 May 2015 08:00:00 EDT

Various embodiments provide lossless compression of an enumeration space for genetic founder lines. In one embodiment, an input comprising a set of genetic founder lines and a maximum number of generations G is obtained. A set of genetic crossing templates of a height h is generated. A determination is made if at least a first genetic crossing template in the set of genetic crossing templates is redundant with respect to a second genetic crossing template in the set of genetic crossing templates. Based on the at least first genetic crossing template being redundant is redundant with respect to the second genetic crossing template, the at least first genetic crossing template is removed from the set of genetic crossing templates. This process of removing the at least first genetic crossing template from the set of genetic crossing templates the redundant creates an updated set of genetic crossing templates.



NRZ signal amplifying device and method, and error rate measurement device and method

Tue, 26 May 2015 08:00:00 EDT

To set an optimum offset voltage and detect an NRZ signal with a very small amplitude. An NRZ signal amplifying device 2 includes: input-side voltage detection means 13 for detecting a high-level voltage and a low-level voltage of an input signal to the main amplifier 12; output-side voltage detection means 14 for detecting the two signals inverted relative to each other; and offset voltage control means 15 for calculating a center voltage between the detected high-level voltage and low-level voltage, setting an offset voltage at which the center voltage is the center of an appropriate input range of the main amplifier 12 to the offset circuit 11, and finely adjusting the offset voltage, such that a voltage difference between the detected two signals inverted relative to each other and a polarity change point is close to 0.



Bus signal encoded with data and clock signals

Tue, 26 May 2015 08:00:00 EDT

A CODEC includes a transmission path between an encoder and a decoder. The encoder receives bits of data in a first form in which each bit of the data is represented by switching between first and second logic states and no voltage change between consecutive bits of the same logic state and serially transmits the bits in a second form in which the first logic state is maintained at a high voltage, the second logic state is maintained at a low voltage, and an intermediate voltage is maintained between consecutive bits. The decoder receives the bits in the second form and derives a clock from the occurrences of the intermediate voltage. The clock, repetitively, is maintained at a logic high, then switches directly from the logic high to a logic low, then is maintained at the logic low, and then switches directly between the logic low and the logic high.



Legend highlighting

Tue, 26 May 2015 08:00:00 EDT

A method for manufacturing keycap includes applying a first coating layer on a surface of a keycap layer, applying a second coating layer on top of the first coating layer, etching at least a portion of the first coating layer to a first depth to form a first etched area, and etching at least a portion of the first etched area to a second depth to form a second etched area.



Controlling a voice site using non-standard haptic commands

Tue, 26 May 2015 08:00:00 EDT

An apparatus and an article of manufacture for controlling a voice site using a haptic input modality include validating a haptic input from an instrument capable of accessing a voice site, processing the haptic input on a server to determine a voice site command corresponding to the haptic input, and processing the voice site command at the server to control an interaction with the voice site.



Linear position measuring system and method for determining the position of a carriage in relation to a slide rail with an incremental scale placed along the slide rail and a scanner secured to the slide scale

Tue, 26 May 2015 08:00:00 EDT

A linear position measuring system (10) and a method for determining a position of a carriage in relation to a slide rail (12), with an incremental scale (14) placed along the slide rail (12) and a scanner secured to the slide scale. The scanner is designed to scan a plurality of incremental markings along the incremental scale (14), wherein the incremental markings can be scanned as an essentially analog signal progression. The scanner is designed to scan the incremental markings with a variable scanning frequency. The scanning frequency can be adaptively varied in relation to a currently acquired frequency of the analog signal progression, wherein the variable scanning frequency measures at least twice the currently acquired frequency of the analog signal progression.



Automotive user interface for a ventilation system of a motor vehicle

Tue, 19 May 2015 08:00:00 EDT

An automotive user interface for controlling the temperature, the distribution and of the air flow rate in a ventilation system of a motor vehicle. The automotive user interface comprises: a touch-sensitive control display unit, which comprises light-emitter diodes structured for providing a visual representation of temperatures that can be set by a user according to a generally circular arrangement; an optically semitransparent touch-sensitive control panel superimposed on the light-emitter diodes in a position corresponding to an area for setting the temperature; and an electronic control unit connected to the light-emitter diodes and to the control panel for controlling the temperature of the air in the ventilation system and the light-emitter-diode means in response to an action of touch contact by a user on the area for setting the temperature.



Selection of text prediction results by an accessory

Tue, 19 May 2015 08:00:00 EDT

A method for entering text in a text input field using a non-keyboard type accessory includes selecting a character for entry into the text field presented by a portable computing device. The portable computing device determines whether text suggestions are available based on the character. If text suggestions are available, the portable computing device can determine the text suggestions and send them to the accessory, which in turn can display the suggestions on a display. A user operating the accessory can select one of the text suggestions, expressly reject the text suggestions, or ignore the text suggestions. If a text suggestion is selected, the accessory can send the selected text to the portable computing device for populating the text field.



Method and a device for increasing the amount of information bits comprised in a symbol

Tue, 19 May 2015 08:00:00 EDT

A method for increasing the amount of information bits comprised in a symbol transferred by a source to at least one receiver. The symbol is representative of a modulated base sequence obtained by encoding a sequence of base bits selected by the source and by modulating the encoded selected sequence. The modulated base sequence has fixed points. The source encodes the selected sequence of base bits and a sequence of supplementary bits, obtains a modulated base sequence by modulating the encoded selected sequence of base bits, obtains a modulated altering sequence by modulating the sequence of supplementary bits, alters the modulated base sequence by modifying at least a part of the values of its fixed points using the modulated altering sequence in order to obtain a modulated altered sequence, and transfers the modulated altered sequence under the form of an altered symbol.



Position detection encoder

Tue, 19 May 2015 08:00:00 EDT

A position detection encoder includes a scale and a detection head and has position detection circuits which are capable of outputting respective pieces of position information on Xf, Xs two tracks. The displacement detection encoder includes: a speed detection circuit which is provided in the detection head and detects a relative speed Xf, Xs relative to the scale; and a delay generation circuit which provides a time difference between two output request signals, the time difference being provided on the basis of a fine adjustment time tadj based on the relative speed Xf, Xs and the respective pieces of position information Xf, Xs on the two tracks, the output request signals St1, St2 urging the first and second position detection circuits to output the pieces of position information on Xf, Xs the two tracks.



Light emitting apparatus, manufacturing method for the light emitting apparatus, printer, and manufacturing method for the printer

Tue, 19 May 2015 08:00:00 EDT

A light emitting apparatus including: a plurality of light emitting elements; a drive circuit including a transistor and a capacitor having one end connected to a gate of the transistor; and a signal supply circuit for receiving a digital gradation signal and outputting an analog voltage signal to the drive circuit, including a computation circuit configured to correct the input digital gradation signal to generate a corrected digital gradation signal, in which the drive circuit is configured to conduct an auto-zero operation which reduce the gate-source voltage of the transistor to a threshold voltage by flowing the drain current to the capacitor, and the computation circuit is configured to generate the corrected digital gradation signal by multiplying a correction coefficient to the input digital gradation signal subtracted by a particular signal common to the plurality of light emitting elements.



Subscription updates in multiple device language models

Tue, 19 May 2015 08:00:00 EDT

Systems and methods for intelligent language models that can be used across multiple devices are provided. Some embodiments provide for a client-server system for integrating change events from each device running a local language processing system into a master language model. The change events can be integrated, not only into the master model, but also into each of the other local language models. As a result, some embodiments enable restoration to new devices as well as synchronization of usage across multiple devices. In addition, real-time messaging can be used on selected messages to ensure that high priority change events are updated quickly across all active devices. Using a subscription model driven by a server infrastructure, utilization logic on the client side can also drive selective language model updates.



RFID transmitter for remote control

Tue, 19 May 2015 08:00:00 EDT

A transmitter for remote control, the transmitter includes an amplifier configured to receive a first audio signal from an electronic device and amplify the first audio signal, a transmission module electrically connected to the amplifier to receive the amplified first audio signal and generating a carrier signal, a power supply connected to the transmission module, and an attenuation circuit electrically connected to the transmission module to receive the carrier signal, wherein the amplified first audio signal is configured to modulate the carrier signal and the first audio signal is one of a left channel audio signal and a right channel audio signal output from the electronic device via an audio connector.



High-speed and high-resolution signal analysis system

Tue, 19 May 2015 08:00:00 EDT

An apparatus relating generally to signal analysis is disclosed. In such an apparatus, a first comparator is coupled to receive a signal input and a first input level. A second comparator is coupled to receive the signal input and a second input level different from the first input level. A time-to-digital converter is coupled at a first port thereof, such as a start port for example, to receive a first output from the first comparator and coupled at a second port thereof, such as a stop port for example, to receive a second output from the second comparator. The time-to-digital converter is coupled to provide digital words representing the signal input.



Feedforward delta-sigma modulator

Tue, 19 May 2015 08:00:00 EDT

A feedforward delta-sigma modulator includes a successive approximation analog-to-digital converter, a digital-to-analog converter, N integrators, a first adder, a second adder, and an optimization zero generation unit, where N is a positive integer. An output terminal of each integrator of the N integrators is coupled to the successive approximation analog-to-digital converter. The digital-to-analog converter is coupled between the first adder and the successive approximation analog-to-digital converter. The first adder is coupled to an input terminal of a first integrator of the N integrator. The second adder is coupled to an input terminal of a Kth integrator of the N integrators, where K is a positive integer. The optimization zero generation unit is coupled between an output terminal of a (K+1)th integrator of the N integrators and the second adder.



Technique for excess loop delay compensation in delta-sigma modulators

Tue, 19 May 2015 08:00:00 EDT

A technique for excess loop delay compensation in delta sigma modulator. The delta sigma modulator includes a loop filter. The loop filter receives an analog input signal and an output of a digital to analog converter. A comparator receives an output of the loop filter and generates a digital output signal. A reference select logic unit receives the digital output signal as a feedback and generates one or more switching signals. One or more switches are coupled to the comparator and each switch receives a pre-computed reference voltage. The one or more switches are activated by the one or more switching signals in response to the digital output signal.



Method and apparatus for generating a band pass signal

Tue, 19 May 2015 08:00:00 EDT

A modulator and a method are disclosed. The modulator is for generating a band pass signal and comprises: sigma delta modulation logic operable to receive an input signal and to perform at least a 3-level quantisation of the input signal to generate an at least 3-level quantised signal; and requantisation logic operable to requantise the at least 3-level quantised signal to a 2-level quantised signal to be provided as the band pass signal. This approach improves the coding efficiency achieved compared to that possible using a 2-level sigma delta modulator, whilst also providing improved noise performance due to the inherent linearity of the 2-level quantised signal which is provided to drive the switch mode power amplifier. Accordingly, the performance of the modulator is improved by increasing its coding efficiency whilst maintaining its linearity which improves the noise performance in adjacent channels.



Analog digital data conversion method, analog digital data converter, and analog digital conversion chip

Tue, 19 May 2015 08:00:00 EDT

The present invention is applicable to the field of communication, and provides an analog digital data conversion method, an analog digital data convertor and an analog digital conversion chip. The method includes: converting multiple groups of analog data to multiple groups of digital data; performing frequency shift on the multiple groups of digital data, wherein the multiple groups of frequency shifted digital data are independently distributed within a first preset bandwidth; filtering the multiple groups of frequency shifted digital data to remove outband information; and distributing without overlap the filtered multiple groups of digital data within a second preset bandwidth. The method substantially reduces pressure of data transmission between the converter and an FPGA or ASIC, and effectively simplifying the design of a multiband receiver.



System and method for digital-to-analog converter calibration

Tue, 19 May 2015 08:00:00 EDT

A system and method are provided for measuring current sources, such as might be useful in the calibration of a digital-to-analog converter (DAC). The method provides a first plurality of current sources. Each current source is engageable to supply a current representing a corresponding nominal value. The method selectively enables current source combinations of current. In response to measuring the current source combinations, current difference values are found, and the current source nominal values are adjusted using the current difference values. In one aspect, a reference current source is provided having a reference first value, and the current source nominal values are adjusted with respect to the reference first value. The current sources may have corresponding nominal digital values adjusted using measured digital difference values.



Optimizing compression engine throughput via run pre-processing

Tue, 19 May 2015 08:00:00 EDT

An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate a reduced representation of an input sequence of characters by replacing a repetition of a sequence of one or more characters by a code representing the repetition of the sequence of one or more characters. The second circuit may be configured to generate a compressed representation of the input sequence of characters in response to the reduced representation of the input sequence of characters. The second circuit is generally configured to recognize the code representing the repetition of the sequence of one or more characters and take into account the repetition of the sequence of one or more characters during a compression operation.



Communication system and sample rate converter thereof

Tue, 19 May 2015 08:00:00 EDT

A communication system including a configurable sample rate converter and a controller is provided. The configurable sample rate converter, configured to convert a digital signal with a first sample rate to a converted signal with a second sample rate, being operable in one of a first configuration and a second configuration. The controller, configured to dynamically control the sample rate converter to operate in one of the first configuration and the second configuration according to at least one condition.



Hierarchical entropy encoding and decoding

Tue, 19 May 2015 08:00:00 EDT

A particular implementation receives geometry data of a 3D mesh, and represents the geometry data with an octree. The particular implementation partitions the octree into three parts, wherein the symbols corresponding to the middle part of the octree are hierarchical entropy encoded. To partition the octree into three parts, different thresholds are used. Depending on whether a symbol associated with a node is an S1 symbol, the child node of the node is included in the middle part or the upper part of the octree. In hierarchical entropy encoding, a non-S1 symbol is first encoded as a pre-determined symbol ‘X’ using symbol set S2={S1, ‘X’} and the non-S1 symbol itself is then encoded using symbol set S0 (S2⊂S0), and an S1 symbol is encoded using symbol set S2. Another implementation defines corresponding hierarchical entropy decoding. A further implementation reconstructs the octree and restores the geometry data of a 3D mesh from the octree representation.



Keyboard

Tue, 19 May 2015 08:00:00 EDT

A keyboard includes a plurality of key tops having areas where light is transmitted; a gear link part provided below the key top and configured to vertically move the key top, a housing part provided below the key top, the housing part being configured to hold the gear link part; a rubber actuator configured to provide a reaction force based on vertical motion of the key top; a membrane sheet provided below the rubber actuator and having a contact, the contact being configured to open and close based on the vertical motion of the key top; a support panel provided below the membrane sheet, the support panel being configured to fix the gear link part with the housing part; a light guide plate provided below the support panel; and a light emitting diode configured to emit the light to a side surface of the light guide plate.



System and method for providing a single and dual key press keypad

Tue, 19 May 2015 08:00:00 EDT

A system and method for receiving character entries in mobile computer devices uses an improved keypad. The keypad uses a dual key press method in which each key of the keypad includes a unique key definition when it alone is pressed. Each of two adjacent keys of the keypad also include a unique key definition when the two adjacent keys are pressed at substantially the same time. A keypad controller receives inputs from the keys and decodes the single key entries and the dual key entries. The keypad occupies a relatively small keypad area while providing full size keys for the user. The keypad also has a mode key that enables a user to change the alphabet mode of the keypad to a numerical mode.