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Separate microchannel voltage domains in stacked memory architecture

Tue, 05 Jan 2016 08:00:00 EST

Separate microchannel voltage domains in a stacked memory architecture An embodiment of a memory device includes a memory stack including one or more coupled memory dies, wherein a first memory die of the memory stack includes multiple microchannels, and a logic chip coupled with the memory stack, the logic chip including a memory controller. Each of the microchannels includes a separate voltage domain, and a voltage level is controlled for each of the plurality of microchannels.



Signal processing circuit and method for driving the same

Tue, 29 Sep 2015 08:00:00 EDT

It is an object to provide a memory device for which a complex manufacturing process is not necessary and whose power consumption can be suppressed and a signal processing circuit including the memory device. In a memory element including a phase-inversion element by which the phase of an input signal is inverted and the signal is output such as an inverter or a clocked inverter, a capacitor which holds data and a switching element which controls storing and releasing of electric charge in the capacitor are provided. For the switching element, a transistor including an oxide semiconductor in a channel formation region is used. The memory element is applied to a memory device such as a register or a cache memory included in a signal processing circuit.



Memory device

Tue, 07 Jul 2015 08:00:00 EDT

A memory device including first to fourth memory cell arrays and a driver circuit including a pair of bit line driver circuits and a pair of word line driver circuits is provided. The first to fourth memory cell arrays are overlap with the driver circuit. Each of the pair of bit line driver circuits and a plurality of bit lines are connected through connection points on an edge along the boundary between the first and second memory cell arrays or on an edge along the boundary between the third and fourth memory cell arrays. Each of the pair of word line driver circuits and a plurality of word lines are connected through second connection points on an edge along the boundary between the first and fourth memory cell arrays or on an edge along the boundary between the second and third memory cell arrays.



Mismatch error reduction method and system for STT MRAM

Tue, 30 Jun 2015 08:00:00 EDT

The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a method for reading a memory cell includes combining a cell current from a memory cell with a reference current from a reference source to create an average current, enabling the average current to flow through a first mirror transistor in a sense path and a second mirror transistor in a reference path, storing the current mismatch on a capacitor coupled to the gates of the first mirror transistor and the second mirror transistor, disconnecting the memory cell from the reference path and disconnecting the reference source from the sense path, enabling the cell current only to flow through the sense path, and determining the output level of the memory cell.



Applying a bias signal to memory cells to reverse a resistance shift of the memory cells

Tue, 16 Jun 2015 08:00:00 EDT

Data is written to cells of a resistance-based, non-volatile memory. An activity metric is tracked since the writing of the data to the cells. In response to the activity metric satisfying a threshold, a bias signal is applied to the cells to reverse a resistance shift of the cells.



Group word line erase and erase-verify methods for 3D non-volatile memory

Tue, 02 Jun 2015 08:00:00 EDT

An erase operation for a 3D stacked memory device assigned storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately.



Fabrication of a magnetic tunnel junction device

Tue, 26 May 2015 08:00:00 EDT

A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, a non-transitory computer-readable medium includes processor executable instructions. The instructions, when executed by a processor, cause the processor to initiate deposition of a capping material on a free layer of a magnetic tunneling junction structure to form a capping layer. The instructions, when executed by the processor, cause the processor to initiate oxidization of a first layer of the capping material to form a first oxidized layer of oxidized material.



Memories and methods for performing column repair

Tue, 26 May 2015 08:00:00 EDT

Memory devices adapted to repair single unprogrammable cells during a program operation, and to repair columns containing unprogrammable cells during a subsequent erase operation. Programming of such memory devices includes determining that a single cell is unprogrammable and repairing the single cell, and repairing a column containing the single cell responsive to a subsequent erase operation.



Storage device

Tue, 26 May 2015 08:00:00 EDT

To provide a storage device with low power consumption. The storage device includes a plurality of cache lines. Each of the cache lines includes a data field which stores cache data; a tag which stores address data corresponding the cache data; and a valid bit which stores valid data indicating whether the cache data stored in the data field is valid or invalid. Whether power is supplied to the tag and the data field in each of the cache lines is determined based on the valid data stored in the valid bit.



Semiconductor device having a memory and calibration circuit that selectively adjusts an impedance of an output buffer dependent upon refresh commands

Tue, 26 May 2015 08:00:00 EDT

A semiconductor device having a circuit that selectively adjusts an impedance of an output buffer. A calibration operation can be performed automatically without issuing a calibration command from a controller. Because a calibration operation to a memory is performed in response to an auto refresh command having been issued for a predetermined number of times, a periodic calibration operation can be secured, and a read operation or a write operation is not requested from a controller during a calibration operation. A start-up circuit activates the calibration circuit when a refresh counter indicates a predetermined value, and prohibits a refresh operation in response to the auto refresh command when the calibration circuit is activated. A temperature detecting circuit may be used to change the frequency of performing a calibration operation.



Clock mode determination in a memory system

Tue, 26 May 2015 08:00:00 EDT

A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.



Nonvolatile random access memory

Tue, 26 May 2015 08:00:00 EDT

According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command.



Power fail protection and recovery using low power states in a data storage device/system

Tue, 26 May 2015 08:00:00 EDT

Systems and methods for early warnings of power loss in solid state storage drives are disclosed. Early warnings of power loss can be used to power the drive to force the drive into a low power states before the energy in backup power sources, such as backup capacitors, is used. The low power states can allow for the reduction of power use by the drive which can provide cost savings and reduction in the risk that the drive will be rendered reconfigurable by a power failure event.



Memory system and method of controlling memory system

Tue, 26 May 2015 08:00:00 EDT

According to one embodiment, a low power direction received from a host device is delayed for a first predetermined time and is output as a first signal, and an internal state is caused to transition to a low power consumption mode that corresponds to the low power direction when a second predetermined time has elapsed after the first signal is asserted.



Control of inputs to a memory device

Tue, 26 May 2015 08:00:00 EDT

A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode.



Refresh method, refresh address generator, volatile memory device including the same

Tue, 26 May 2015 08:00:00 EDT

A refresh method for a volatile memory device includes refreshing memory cells of a first set of rows of an array at a first refresh rate having a first refresh period, the first refresh rate being a lower rate having a longer refresh period than a second refresh rate having a second refresh period, wherein each memory cell in the first set of rows of the array has a retention time longer than the first refresh period; and refreshing memory cells of a second set of rows of the array at a third refresh rate having a third refresh period, the third refresh rate being a higher rate having a shorter refresh period than the second refresh rate having the second refresh period, wherein at least one memory cell of each row of the second set of rows has a retention time longer than the third refresh period and shorter than the first refresh period. The second refresh period corresponds to a refresh period defined in a standard for the volatile memory device.



Sense amplifier scheme

Tue, 26 May 2015 08:00:00 EDT

A sense amplifier circuit comprising a pair of cross-coupled inverters and a data line charging circuit is disclosed. The cross-coupled inverters comprise a first inverter and a second inverter. The first inverter has a first pull-up transistor with a first pull-up terminal. The second inverter has a second pull-up transistor with a second pull-up terminal. The output of the first inverter is coupled to the input of the second inverter at a first sense amp node. The output of the second inverter is coupled to the input of the first inverter at a second sense amp node. The data line charging circuit has a first node connected to a data line and the first pull-up terminal. The data line charging circuit also has a second node connected to a complementary data line and the second pull-up terminal. The first and second pull-up transistors are coupled to different voltage levels when a sense amplifier enable signal is activated.



Semiconductor device and semiconductor system including the same

Tue, 26 May 2015 08:00:00 EDT

A semiconductor device includes two or more memory chips electrically coupled. Each of the memory chips includes global lines, a MUX unit, a selection unit, and an output unit. The global lines transmit data stored in memory cells. The MUX unit receives the data loaded onto the global lines to output a test data. The selection unit is inserted into two or more of the global lines and configured to output the test data instead of the data loaded onto the two or more global lines, in a test mode. The output unit is coupled to the global lines and is configured to output the data in a normal mode, and output the test data received from any one of the two or more global lines connected to the selection unit to an I/O pad based on information about the memory chip in a test mode.



Self-repairing memory

Tue, 26 May 2015 08:00:00 EDT

A memory array has a plurality of rows including a plurality of memory words. Each first bit of a plurality of first bits is associated with a memory word of the each row. A state of the each first bit indicates whether the associated memory word has had an error. Each redundancy row of a plurality of redundancy rows includes a plurality of redundancy words. Each redundancy word is associated with a memory word. A corrected data cache has at least one repair word configured to store corrected data and at least one status bit associated with the at least one repair word, the status bit indicating whether the corrected data stored in the repair word is a pending repair. The corrected data cache is configured to write the corrected data stored in the repair word to at least one of a counterpart memory word or a counterpart redundancy word.



Apparatuses, sense circuits, and methods for compensating for a wordline voltage increase

Tue, 26 May 2015 08:00:00 EDT

Apparatuses, sense circuits, and methods for compensating for a voltage increase on a wordline in a memory is described. An example apparatus includes a bitline, a memory cell coupled to the bitline, a bipolar selector device coupled to the memory cell, a wordline coupled to the bipolar selector device, and a wordline driver coupled to the wordline. The apparatus further includes a model wordline circuit configured to model an impedance of the wordline and an impedance of the wordline driver, and a sense circuit coupled to the bitline and to the model wordline circuit. The sense circuit is configured to sense a state of the memory cell based on a cell current and provide a sense signal indicating a state of the memory cell. The sense circuit is further configured to adjust a bitline voltage responsive to an increase in wordline voltage as modeled by the model wordline circuit.



Semiconductor memory device

Tue, 26 May 2015 08:00:00 EDT

A semiconductor memory device includes: a burst start signal generation unit configured to generate a first burst start signal by delaying a write pulse by a first period, generate a second burst start signal by delaying the write pulse by a second period, and selectively transmit the first or second burst start signal as a select burst start signal in response to a test signal; an input control signal generation unit configured to generate an input control signal in response to the first burst start signal; and a write command generation unit configured to generate a write driver enable signal in response to the select burst start signal.



Memory controller and method of calibrating a memory controller

Tue, 26 May 2015 08:00:00 EDT

A memory controller transmits a data signal, a data strobe signal and a mask signal to a memory, wherein each transition of the data strobe signal indicates a sample point for the data signal and the mask signal indicates a validity of the data signal. A mask signal training procedure is carried out comprising three steps. Writing first and second values to the memory for a predetermined plurality of transitions of the data strobe signal with the mask signal set to indicate that the first data signal is valid and the second data signal is valid except for a selected transition of the predetermined plurality. Reading from the memory for the predetermined plurality of transitions of the data strobe signal. Determining a timing offset for the mask signal for which the value read at the selected transition matches the first value.



Using a reference bit line in a memory

Tue, 26 May 2015 08:00:00 EDT

Methods, memories and systems may include charging a sense node to a logic high voltage level, and supplying charge to a bit line and to a reference bit line for a precharge period that is based, at least in part, on a time for a voltage of the reference bit line to reach a reference voltage. A memory cell that is coupled to the bit line may be selected after the precharge period, and a clamp voltage may be set based, at least in part, on the voltage of the reference bit line. If a voltage level of the bit line is less than the clamp voltage level during a sense period, charge may be drained from the sense node, and a state of the memory cell may be determined based, at least in part, on a voltage level of the sense node near an end of the sense period.



Solid state drive and data erasing method thereof

Tue, 26 May 2015 08:00:00 EDT

A data erasing method of a solid state drive is provided. The solid state drive includes a memory module. The memory module includes a block. A data to be erased is stored in the block. The data erasing method includes steps of performing a first erasing operation to erase the block, programming the block after the first erasing operation, and performing a second erasing operation to erase the block.



Row driver circuit for NAND memories including a decoupling inverter

Tue, 26 May 2015 08:00:00 EDT

Devices, methods, and circuits for row driver architectures that can improve an existing row driver circuit including a boosting capacitor and a level shifter circuit. For example, the improvement can include a decoupling inverter that decouples the level shifter from the boosting capacitor, which can reduce the time for the row driver to turn on and drive appropriate voltages to the matrix array.



Non-volatile memory programming

Tue, 26 May 2015 08:00:00 EDT

Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines associated with different groups of memory cells during a programming operation. Such a method applies the voltages to the data lines associated with a last group of memory cells being programmed in a different fashion from the other groups of memory cells after the other groups of memory cells have been programmed. Other embodiments including additional memory devices and methods are described.



Non-volatile semiconductor memory device having non-volatile memory array

Tue, 26 May 2015 08:00:00 EDT

According to one embodiment, a non-volatile semiconductor memory device which is provided with a memory cell array, bit lines, word lines, and a sense amplifier circuit is presented. The memory cell array includes memory cells. The bit lines are electrically connected to the memory cells. The word lines are electrically connected to gates of the non-volatile memory cells. The sense amplifier circuit includes sense amplifiers which are electrically connected to the bit lines. Each of the sense amplifiers includes a latch circuit which is capable of holding data, and a detection circuit. The sense amplifiers are configured to apply any one of a first voltage and a second voltage higher than the first voltage to the bit lines respectively. The sense amplifiers apply any one of the first voltage and the second voltage s a third voltage to the bit lines, and apply the third voltage to the detection circuit.



Nonvolatile semiconductor memory device and verification control method for the same

Tue, 26 May 2015 08:00:00 EDT

A nonvolatile semiconductor memory device includes a memory cell array, a plurality of local sense amplifiers, a global sense amplifier and an address decoder. The address decoder is configured to switch between a first verification and a second verification. The first verification operates the plurality of local sense amplifiers and simultaneously verifies data of a plurality of memory cells connected to the plurality of local sense amplifiers. The second verification stops the plurality of local sense amplifiers, directly connects the local bit line connected to each of the local sense amplifiers with the global bit line, and simultaneously verifies data of the plurality of memory cells connected to the plurality of local sense amplifiers.



Periodic erase operation for a non-volatile medium

Tue, 26 May 2015 08:00:00 EDT

An apparatus, system, and method are disclosed for managing erase operations for a data storage medium. A method includes determining whether a use threshold for one or more non-volatile storage cells is satisfied. A method includes performing a default erase operation for the one or more storage cells in response to determining that the use threshold is not satisfied. A method includes performing an extended erase operation for the one or more storage cells in response to determining that the use threshold is satisfied. An extended erase operation may include a greater number of erase pulse iterations than a default erase operation.



Charge pump redundancy in a memory

Tue, 26 May 2015 08:00:00 EDT

An integrated circuit includes a circuit block to utilize a load current at a load voltage from a power input and two or more charge pump arrays. The outputs of the charge pump arrays are coupled to the power input of the circuit block. The integrated circuit includes one or more modifiable elements to disable one or more of the two or more charge pump arrays.



Method for writing in and reading data from a semiconductor storage device and semiconductor storage device

Tue, 26 May 2015 08:00:00 EDT

A method for writing data in a semiconductor storage device and a semiconductor storage device are provided, that can reduce variations in readout current from a sub storage region which serves as a reference cell for the memory cells of the semiconductor storage device, thereby preventing an improper determination from being made when determining the readout current from a memory cell. In the method, data is written on a memory cell in two data write steps by applying voltages to the first and second impurity regions of the memory cell, the voltages being different in magnitude from each other.



Program and read trim setting

Tue, 26 May 2015 08:00:00 EDT

A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability.



Semiconductor device and method of operating the same

Tue, 26 May 2015 08:00:00 EDT

A semiconductor device includes first memory blocks arranged in a longitudinal direction, and including a plurality of strings, wherein the strings are formed along a vertical direction, and the strings adjacent to each other share bit lines or source lines with each other, each string including a drain selection transistor coupled to an odd drain selection line or an even drain selection line, memory cells coupled to word lines, and a source selection transistor coupled to an odd source selection line or an even source selection line, page buffers suitable for storing data, a selection switch unit suitable for transferring the data stored in the page buffers or various voltages supplied from an external source to the bit lines and the source lines; and a control circuit suitable for controlling the page buffers and the selection switch unit.



Semiconductor memory device, system having the same and program method thereof

Tue, 26 May 2015 08:00:00 EDT

The present invention relates to a semiconductor memory device and a program method thereof. The program method according to an embodiment of the present invention includes: precharging a plurality of cell strings by providing a positive voltage to the plurality of cell strings through a common source line; and performing a program operation on selected memory cells by applying a program pulse to the selected memory cells.



Non-volatile memory device and read method thereof

Tue, 26 May 2015 08:00:00 EDT

Disclosed is a nonvolatile memory device which includes a memory cell connected to a bit line and a word line; a page buffer electrically connected to the bit line and sensing data stored in the memory cell; and a control logic controlling the page buffer to vary a develop time of the bit line or a sensing node connected to the bit line according to a current temperature during a read operation.



Non-volatile memory cell

Tue, 26 May 2015 08:00:00 EDT

A non-volatile memory cell comprises a coupling device, a first and a second select transistor, and a first and a second floating gate transistor is disclosed. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to the first floating gate transistor and the second select transistor. Moreover, the first select transistor, the first floating gate transistor, and the second select transistor are formed in a second conductivity region. The second floating gate transistor is formed in a third conductivity region, wherein the first conductivity region, the second conductivity region, and the third conductivity region are formed in a fourth conductivity region. The first conductivity region, the second conductivity region, and the third conductivity region are wells, and the fourth conductivity region is a deep well. The third conductivity region surrounds the first conductivity region and the second conductivity region.



Efficient memory sense architecture

Tue, 26 May 2015 08:00:00 EDT

Memory architecture, such as for a flash EEPROM memory embedded within a processor or other large scale integrated circuit, and including differential sense circuitry. The memory includes an array of memory cells in rows and columns, and organized into sectors, each sector split into portions. Columns of the array are grouped into small groups from which a final stage column decode selects a column from the group based on the least significant bits of the column address. Adjacent groups of columns are paired, with a selected column from each group coupled to a differential input of the sense amplifier, but with one of the selected columns associated with an unselected sector portion and thus serving as a dummy bit line. Conductor routing is simplified, and chip area is reduced, by maintaining unselected column groups adjacent or nearby to selected column groups.



Flash memory having dual supply operation

Tue, 26 May 2015 08:00:00 EDT

A flash memory device may operate from two supply voltages, one being provided externally, and the other being generated within the flash memory device from the external supply voltage. The flash memory device may be provided with a selectable-level buffer for interfacing with either low supply voltage or high supply voltage integrated circuits. To provide even greater flexibility, the flash memory device may be provided with the capability of receiving a second supply voltage from an external source, which may take precedence over the internally-generated second supply voltage or may be combined with the internally-generated second supply voltage.



Integrated circuit including a voltage divider and methods of operating the same

Tue, 26 May 2015 08:00:00 EDT

An integrated circuit includes at least one memory array and at least one capacitor array over a substrate. The at least one capacitor array includes a plurality of capacitor cell structures. The capacitor cell structures of the plurality of cell structures comprise a first capacitor electrode over the substrate. A second capacitor electrode is over the first capacitor electrode. A third capacitor electrode is adjacent to first sidewalls of the first and second capacitor electrodes. A fourth capacitor electrode is adjacent to second sidewalls of the first and second capacitor electrodes. A fifth capacitor electrode is over the substrate and adjacent to the fourth capacitor electrode.



Off-die charge pump that supplies multiple flash devices

Tue, 26 May 2015 08:00:00 EDT

A system and method for storing data uses multiple flash memory dies. Each flash memory die includes multiple flash memory cells. A charge pump is adapted to supply charge at a predetermined voltage to each flash memory die of the flash memory dies, and an interface is adapted to receive instructions for controlling the charge pump.



Shifting cell voltage based on grouping of solid-state, non-volatile memory cells

Tue, 26 May 2015 08:00:00 EDT

Cells of a solid-state, non-volatile memory are assigned to one of a plurality of groups. Each group is defined by expected symbols stored in the cells in view of actual symbols read from the cells. Based on cell counts within the groups, it can be determined that a shift in a reference voltage will reduce a collective bit error rate of the cells. The shift can be applied to data access operations affecting the cells.



System and method for improving error distribution in multi-level memory cells

Tue, 26 May 2015 08:00:00 EDT

A system including a state set module to arrange states of a memory cell in three sets. The memory cell stores three bits when programmed to a state. Each set includes three rows of bits. In a set, a row includes one of the three bits of the states. The first, second, and third rows of the first, second, and third sets include a first number of state transitions. The second, third, and first rows of the first, second, and third sets include a second number of state transitions. The third, first, and second rows of the first, second, and third sets include a third number of state transitions. A write module writes first, second, and third portions of data to a plurality of memory cells, each memory cell storing the three bits when programmed to a state, using states selected respectively from the first, second, and third sets.



Phase change memory

Tue, 26 May 2015 08:00:00 EDT

A phase change memory device including a voltage generator that generates an operating voltage by generating at least one modified clock signal, a pulse width of which is maintained constant for at least one clock cycle in response to a pump enable signal being enabled, from at least one reference clock signal, and performing a pump operation on a power supply voltage according to the at least one modified clock signal; and a memory cell array that includes a plurality of phase change memory cells connected between word lines and bit lines. The operating voltage is applied to the memory cell array so as to perform a data access operation.



Magnetoresistive effect element and method of manufacturing magnetoresistive effect element

Tue, 26 May 2015 08:00:00 EDT

A magnetoresistive effect element includes first and second conductive layers, a first magnetic layer between the first and second conductive layers having a magnetization direction that is unchangeable, a second magnetic layer between the first and second conductive layers having a magnetization direction that is changeable, a tunnel barrier layer between the first and second magnetic layers, a nonmagnetic layer between the second magnetic layer and the second conductive layer, and a conductive sidewall film that provides a current path between the second magnetic layer and the second conductive layer that has a lower resistance than a current path through the nonmagnetic layer.



Magnetoresistive effect element, magnetic memory cell using same, and random access memory

Tue, 26 May 2015 08:00:00 EDT

A magnetoresistive effect element uses a perpendicularly magnetized material and has a high TMR ratio. Intermediate layers composed of an element metal having a melting point of 1600° C. or an alloy containing the metal on an outside of a structure consisting of a CoFeB layer, an MgO barrier layer, and a CoFeB layer. By inserting the intermediate layers, crystallization of the CoFeB layer during annealing is advanced from an MgO (001) crystal side, so that the CoFeB layer has a crystalline orientation in bcc (001).



Anti-tampering devices and techniques for magnetoresistive random access memory

Tue, 26 May 2015 08:00:00 EDT

A system may include circuitry and a magnetoresistive random access memory (MRAM) die including at least one MRAM cell. The circuitry may be configured to detect attempted tampering with the MRAM die and generate a signal based on the detected attempted tampering. The signal may be sufficient to damage or destroy at least one layer of the at least one MRAM cell or a fuse electrically connected to a read line of the at least one MRAM cell.



Memory device having a local current sink

Tue, 26 May 2015 08:00:00 EDT

A memory device having a local current sink is disclosed. In a particular embodiment, an electronic device is disclosed. The electronic device includes one or more write drivers. The electronic device includes at least one Magnetic Tunnel Junction (MTJ) coupled to a bit line and coupled to a source line. The electronic device also includes a current sink circuit comprising a single transistor, the single transistor coupled to the bit line and to the source line.



SRAM cells suitable for Fin field-effect transistor (FinFET) process

Tue, 26 May 2015 08:00:00 EDT

A static random access memory (SRAM) cell includes first and second n-channel transistors, first and second p-channel transistors, first and second enable transistors, and first and second pass gates. The first n-channel transistor, the first p-channel transistor, and the first enable transistor are connected in series between first and second reference potentials. The second n-channel transistor, the second p-channel transistor, and the second enable transistor are connected in series between the first and second reference potentials. The first pass gate is configured to selectively connect a first bitline to a first node. The first node is connected to a gate of the first n-channel transistor and a gate of the first p-channel transistor. The second pass gate is configured to selectively connect a second bitline to a second node. The second node is connected to a gate of the second n-channel transistor and a gate of the second p-channel transistor.



Memory device

Tue, 26 May 2015 08:00:00 EDT

In a memory device, memory capacity per unit area is increased while a period in which data is held is ensured. The memory device includes a driver circuit provided over a substrate, and a plurality of memory cell arrays which are provided over the driver circuit and driven by the driver circuit. Each of the plurality of memory cell arrays includes a plurality of memory cells. Each of the plurality of memory cells includes a first transistor including a first gate electrode overlapping with an oxide semiconductor layer, and a capacitor including a source electrode or a drain electrode, a first gate insulating layer, and a conductive layer. The plurality of memory cell arrays is stacked to overlap. Thus, in the memory device, memory capacity per unit area is increased while a period in which data is held is ensured.



Memory device with resistive random access memory (ReRAM)

Tue, 26 May 2015 08:00:00 EDT

A method includes, in a data storage device that includes a non-volatile memory and a resistive random access memory (ReRAM) on the same die, receiving data from a memory controller via a bus. The method also includes routing the data to data latches of the non-volatile memory via a first path and to the ReRAM via a second path distinct from the first path.